Epson S1D16000 Series User manual

MF425-05
Technical Manual
S1D16000 Series
Technical Manual
IEEE1394 Controller
S1R76801F00A
Technical Manual
S1D16000 Series
EPSON Electronic Devices Website
ELECTRONIC DEVICES MARKETING DIVISION
First issue November,1990
Printed May,2001 in Japan H A
4.5mm
This manual was made with recycle paper,
and printed using soy-based inks.
Technical Manual
LCD DRIVERS
S1D16000 Series
http://www.epson.co.jp/device/
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In pursuit of “Saving” Technology, Epson electronic devices.
Our lineup of semiconductors, liquid crystal displays and quartz devices
assists in creating the products of our customers’ dreams.
Epson IS energy savings.
4.5mm
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the
written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this
material without notics. Seiko Epson does not assume any liability of any kind arising out of any
inaccuracies contained in this material or due to its application or use in any product or circuit and,
further, there is no repersesnation that this material is applicable to products requiring high level
reliability, such as, medical products. Moreover, no license to any intellectual property rights is
granted by implication or otherwise, and there is no representation or warranty that anything made
in accordance with this material will be free from any patent or copyright infringement of a third
party. This material or portions thereof may contain technology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may
require an export license from the Ministry of International Trade and Industry or other approval
from another government agency.
©Seiko Epson Corporation 2001, All rights reserved.
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The information of the product number change
StartingApril 1, 2001 the product number will be changed as listed below. To order fromApril 1,
2001 please use the new product number. For further information, please contact Epson sales
representative.
Configuration of product number
●DEVICES
S1 D 16006 D 00A0 00
Packing specification
Specifications
Shape (D:Chip, T:TCP)
Model number
Model name (D:LCD Driver)
Product classification (S1:Semiconductors)
Comparison table between new and previous number
Previous number New number
SED1606D0A S1D16006D00A*
SED1606D0B S1D16006D00B*
SED1606F0A S1D16006F00A*
SED1606D1A S1D16006D01A*
SED1606D1B S1D16006D01B*
SED1640D0B S1D16400D00B*
SED1651D0A S1D16501D00A*
SED1670D0A S1D16700D00A*
SED1670D1A S1D16700D01A*
SED1670D0B S1D16700D00B*
SED1670D1B S1D16700D01B*
SED1672D0A S1D16702D00A*
SED1672D1A S1D16702D01A*
SED1672D0B S1D16702D00B*
SED1672D1B S1D16702D01B*
SED1672F0A S1D16702F00A*
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CONTENTS
S1D 16000 series Selection Guide
<Segment drivers>
S1D 16006...................................................... 1-1
S1D 16400...................................................... 2-1
<Common drivers>
S1D 16501...................................................... 3-1
S1D 16700...................................................... 4-1
S1D 16702...................................................... 5-1
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Selection Guide
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S1D16000 (SED1600) series
ÁSegment drivers
S1D16006D00A*
(SED1606D0A)
S1D16006D00B*
(SED1606D0B)
S1D16006F00A*2.7 to 5.5 8 to 28
(SED1606F1A)
S1D16006D01A*
(SED1606D1A)
S1D16006D01B*
(SED1606D1B)
S1D16400D00B*2.7 to 5.5 8 to 28
(SED1640D0B)
4-bit parallel
Part number
Supply voltage
range (V)
LCD voltage
range (V)
Duty Outputs Data bus
80
1/100 to 1/300
ÁCommon drivers
Package
1/100 to 1/300 80 4-bit parallel
S1D16501D00A*2.7 to 5.5 8 to 28
(SED1651D0A)
S1D16700D00A*
(SED1670D0A)
S1D16700D01A*
(SED1670D1A)2.7 to 5.5 8 to 28
S1D16700D00B*
(SED1670D0B)
S1D16700D01B*
(SED1670D1B)
S1D16702D00A*
(SED1672D0A)
S1D16702D01A*
(SED1672D1A)
S1D16702D00B*2.7 to 5.5 8 to 28
(SED1672D0B)
S1D16702D01B*
(SED1672D1B)
S1D16702F00A*
(SED1672F0A)
Al pad chip (zigzag positioning)
Al pad chip (INH type)
Al pad chip (DOFF type)
Au bump chip (INH type)
Au bump chip (DOFF type)
Al pad chip (INH type)
Al pad chip (DOFF type)
Au bump chip (INH type)
Au bump chip (DOFF type)
QFP5-80pin (INH type)
Part number
Supply voltage
range (V)
LCD voltage
range (V)
Duty Outputs Package
1/64 to 1/300 68
1/64 to 1/300
1/64 to 1/300
100
100
Al pad chip (for COB)
Au bump chip
QFP5-100pin
Al pad chip (DOFF type)
Au bump chip (DOFF type)
Au bump chip (slim chip)
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S1D16006 Series
Rev.2.1
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– i –
CONTENTS
1. DESCRIPTION ...............................................................................................................................................1-1
2. FEATURES ....................................................................................................................................................1-1
3. BLOCK DIAGRAM .........................................................................................................................................1-2
4. PIN DESCRIPTION........................................................................................................................................1-3
5. PAD ................................................................................................................................................................1-4
6. PIN LAYOUT ..................................................................................................................................................1-6
7. FUNCTIONAL DESCRIPTION.......................................................................................................................1-7
8. TIMING CHART .............................................................................................................................................1-8
9. ABSOLUTE MAXIMUM RATINGS.................................................................................................................1-9
10. ELECTRICAL CHARACTERISTICS ............................................................................................................1-10
11. LCD DRIVE POWER....................................................................................................................................1-13
12. TYPICAL CIRCUIT DIAGRAM .....................................................................................................................1-14
Rev. 2.1
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S1D16006 Series
Rev.2.1 EPSON 1–1
1. DESCRIPTION
The S1D16006 Series is an 80 output segment (column) driver which is suitable for driving a very high
capacity dot-matrix LCD panels. It is intended to be used in conjunction with the S1D16700/16702 as a pair.
The S1D16006 Series is featured in a high quality of picture in LCD display. It employs a high-speed enable
chain system which is favorable to a low-power driving. Allowed to be operated with a low voltage in the
logic system power supply, it can meet a wide range of applications.
2. FEATURES
• Number of LCD drive output segments: 80
• Low current consumption
• Low voltage operation: –2.7 V (Max.)
• Wide range of LCD drive voltages: –8 V to –28 V
• High-speed and low-power data transfer enabled by means of a 4-bit bus and chain enable support
Shift clock frequency: 6.5 MHZ (at –2.7 V)
10.0 MHZ (at –4.5 V)
• Selectable pin output shift direction (S1D16006D01A*)
• Adjustable offset bias of LCD power to a VDD level
• Logic system power supply : –2.7 V to –5.5 V
• Non-bias display off function
• Chip packaging
S1D16006D00A*(AL-pad die form)
S1D16006D00B*(Au bump die form)
S1D16006D01A*(AL-pad die form)
S1D16006D01B*(Au bump die form)
PKG S1D16006F00A*(QFP5-100 pin)
• No radial rays countermeasure taken in designing
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S1D16006 Series
1–2 EPSON Rev.2.1
O 0 O79
······································
V0 V2
V5 V3
FR
LP
V
V
D3 to D0
SHL
EIO1 EIO2
XSCL
LCD driver 80 bit
Level shifter 80 bit
Enable shift register
Latch 80 bit
Data register 80 bit
DSPOFF
SS
DD
*1 Dummy terminal NC when S1D16006D00
**
is used.
DSPOFF terminal when S1D16006D01
**
is used
*1
3. BLOCK DIAGRAM
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S1D16006 Series
Rev.2.1 EPSON 1–3
Function
Segment (column) output for LCD driving
The output changes at the LP falling edge.
Display data input
Display data shift clock input (Falling edge trigger)
Display data latch pulse input (Falling edge trigger)
Enable input/output
To be set to input or output according to the SHL input level.
The output is reset by the LP input. Upon the end of fetching of
80-bit data, the system starts up automatically to HIGH.
Shift direction selection and EIO pin I/O control input When data
is input to (D3, D2 ... D0 ) pins sequentially in order of (a3, a2,
a1, a0), (b3, b2, b1, b0) ... (t3, t2, t1, t0), the relationship
between the data and segment output becomes as shown in the
table below:
(Note) The relationship between the data and segment output is
determined irrespective of the number of shift clock
inputs.
LCD drive output AC converted signal input
Force input of blank
V0 level is forcibly set by entering LOW level (available with
S1D16006D01**alone).
Logic power supply VDD: 0 V VSS: –2.7 V to –5.5 V
LCD drive circuit power supply VDD: 0 V V5: –8 V to –28 V
VDD ≥V0≥V2≥6/9 V5
3/9 V5≥V3≥V5
When used at a same potential, V0and VDD are used by
grounding them close to the IC chip.
Number
of pins
Pin name
O0 ~ O79
D0 ~ D3
XSCL
LP
EIO1, EIO2
SHL
FR
DSPOFF
VDD, VSS
V0, V2,
V3, V5
*1
80
4
1
1
2
1
1
1
2
4
O Output EIO
SHL 79 78 77 2 1 0 EIO1 EIO2
LOW a3 b2 c1 . . . t2 t1 t0 Output Input
HIGH t0 t1 t2 . . . a1 a2 a3 Input Output
I/O
O
I
I
I
I/O
I
I
I
Power supply
Power supply
*1 Be sure to connect V0to V5to their LCD power, respectively. Total: 100
S1D16006D00** (including four NC’4)
S1D16006D01** (including four NC’3)
4. PIN DESCRIPTION
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S1D16006 Series
1–4 EPSON Rev.2.1
5. PAD
ÁPad Layout
Chip size: ........................... 5.59 mm ×3.50 mm
Pad pitch: ........................... 0.153 mm (Min.)
Chip thickness:................... 0.400 mm (AL-pad die form)
0.525 mm (Au-bump die form)
Au bump specifications [Reference values]
Bump size: 117µm ×109µm ±20 um
Bump height: 17µm to 28µm (Details shall be stipulated in the delivery specification.)
AL-pad die form
Pad Opening 87×76µm
(0.0)
Y
X
75 50
6580 60
70
55
85
90
95
100 1510 15 20 25 30
35
40
45
D1606D
0B
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S1D16006 Series
Rev.2.1 EPSON 1–5
PAD Actual dimensions
NO. NAME X Y
1 O0 –2227 –1578
2 O1 –2073
3 O2 –1920
4 O3 –1766
5 O4 –1612
6 O5 –1459
7 O6 –1305
8 O7 –1152
9 O8 –998
10 O9 –845
11 O10 –691
12 O10 –537
13 O12 –384
14 O13 –230
15 O14 –76
16 O15 77
17 O16 231
18 O17 384
19 O18 538
20 O19 692
21 O20 845
22 O21 999
23 O22 1152
24 O23 1306
25 O24 1460
26 O25 1613
27 O26 1767
28 O27 1921
29 O28 2074
30 O29 2228
31 O30 2381
32 O31 2622 –1346
33 O32 –1188
34 O33 –1029
Unit (µm)
PAD Actual dimensions
NO. NAME X Y
69 O68 –537 1578
70 O69 –691
71 O70 –846
72 O71 –998
73 O72 –1152
74 O73 –1305
75 O74 –1459
76 O75 –1613
77 O76 –1766
78 O77 –1920
79 O78 –2073
80 O79 –2227
81 EIO2 –2381
82 D0 –2622 1346
83 D1 1192
84 D2 1039
85 D3 885
86 Dummy 732
87 Dummy 578
88 Dummy 424
89 *1 271
90 VDD 106
91 VSS –58
92 V0 –224
93 V2 –389
94 V3 –553
95 V5 –718
96 SHL –2611 –885
97 XSCL –1039
98 LP –1192
99 FR –1346
100 EIO1 –2381 –1578
PAD Actual dimensions
NO. NAME X Y
35 O34 2622 –871
36 O35 –713
37 O36 –554
38 O37 –396
39 O38 –238
40 O39 –79
41 O40 79
42 O41 238
43 O42 396
44 O43 554
45 O44 713
46 O45 871
47 O46 1029
48 O47 1188
49 O48 1346
50 O49 2381 1578
51 O50 2228
52 O51 2074
53 O52 1921
54 O53 1767
55 O51 1613
56 O55 1460
57 O56 1306
58 O57 1152
59 O58 999
60 O59 845
61 O60 692
62 O61 538
63 O62 384
64 O63 231
65 O64 77
66 O65 –76
67 O66 –230
68 O67 –384
*1: Pad No.89 is dummy when S1D16006D00**is used.
It will be DSPOFF with S1D16006D01**.
ÁPad center coordinate
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S1D16006 Series
1–6 EPSON Rev.2.1
1O0
2O1
3O2
4O3
5O4
6O5
7O6
8O7
9O8
10 O9
11 O10
12 O11
13 O12
14 O13
15 O14
16 O15
17 O16
18 O17
19 O18
20 O19
21 O20
22 O21
23 O22
24 O23
25 O24
26 O25
27 O26
28 O27
29 O28
30 O29
31 O30
32 O31
33 O32
34 O33
35 O34
36 O35
37 O36
38 O37
39 O38
40 O39
41 O40
42 O41
43 O42
44 O43
45 O44
46 O45
47 O46
48 O47
49 O48
50 O49
51 O50
52 O51
53 O52
54 O53
55 O54
56 O55
57 O56
58 O57
59 O58
60 O59
61 O60
62 O61
63 O62
64 O63
65 O64
66 O65
67 O66
68 O67
69 O68
70 O69
71 O70
72 O71
73 O72
74 O73
75 O74
76 O75
77 O76
78 O77
79 O78
80 O79
81 EIO2
82 D0
83 D1
84 D2
85 D3
86 NC
87 NC
88 NC
89 *1
90 VDD
91 VSS
92 V0
93 V2
94 V3
95 V5
96 SHL
97 XSCL
98 LP
99 FR
100 EIO1
PIN No. NAME PIN No. NAME PIN No. NAME PIN No. NAME PIN No. NAME
S1D16006F
INDEX
Package Type: QFP–5 100pin
50
81
130
80 51
*1: Pad No.89 is dummy when S1D16006D00**is used.
It will be DSPOFF with S1D16006D01**.
6. PIN LAYOUT
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S1D16006 Series
Rev.2.1 EPSON 1–7
7. FUNCTIONAL DESCRIPTION
Enable shift register
This is a bidirectional shift register with which the shift direction is selected by SHL input. The output of this
shift register is used to store the data bus signals to data register.
When the enable signal is in the disable status, the internal clock signal and data bus are fixed to LOW and
the system is made into the power save mode.
When using two or more segment drivers, connect the EIO pin of each driver in a cascade arrangement and
the EIO pin of the leading driver to VDD.
Since the enable controller circuit automatically detects that the data for 80 bits have been fetched thoroughly
and then transfers the enable signal to the controller, it is not necessary to provide the control signal using the
control LSI.
Data register
This is a register used to convert the data bus signal into serial or parallel signal through the enable shift register
output. Consequently, the relationship between the serial display data and segment output is determined
irrespective of the number of shift clock inputs.
Latch
This latch is used to fetch the content of data register at the LP falling edge trigger and to send its output to
the level shifter.
Level shifter
This is a level interface circuit used to convert the signal voltage level from the logic system level to LCD drive
level.
LCD driver
This driver outputs the LCD drive voltage.
The relationship among the data bus signal, AC converted signal FR and segment output voltage is as shown
in the table below:
Data bus FR O output voltage
signal
HIGH V0
HIGH LOW V5
HIGH V2
LOW LOW V3
(S1D16006D00**)
(S1D16006D01**)
DSPOFF Data bus FR O output voltage
signal
HIGH HIGH HIGH V0
LOW V5
HIGH LOW HIGH V2
LOW V3
LOW — — V0
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S1D16006 Series
1–8 EPSON Rev.2.1
1 to 3 stand for a cascaade No. of driver.
EIO 3
LP
LP
LP
LATCH
DATA
LATCH
DATA
FR
DSPOFF
XSCL
D0 to D3
EIO 1
EIO 2
FR
V
0
V 2
V 3
V 5
H
HH
LL
LL
HH
LL
HH
HH
LL
L
20 1 2 3 123 20 123 123 20 20
200 2001991 2 1 200199 1234
When the duty is 1/200 (Reference Example)
S1D16006D00
**
S1D16006D01
**
When S1D16006D01
**
is used:
The driver output is forcibly switched to
V0 output upon switching of DSPOFF
8.TIMING CHART
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S1D16006 Series
Rev.2.1 EPSON 1–9
9. ABSOLUTE MAXIMUM RATINGS
Notes:
1. All the above voltage is based on VDD = 0V.
2. The storage temperature 1 stipulates the temperature by unit of a chip.
3. The voltage of V0, V2and V3must always satisfy the condition of VDD≥V0≥V2≥V3≥V5.
4. Floating of the logic system power during while the LCD drive system power is applied, or exceeding VSS
= –2.6 V can cause permanent damage to the LSI. Functional operation under these conditions is not
implied.
Care should be taken to the power supply sequence especially in the system power ON or OFF.
Parameter Symbol Rating Unit
Power voltage (1) VSS –7.0 to +0.3 V
Power voltage (2) V5–30.0 to +0.3 V
Power voltage (3) V0, V2, V3V5–0.3 to VDD+0.3 V
Input voltage VIVSS–0.3 to VDD+0.3 V
Output voltage VOVSS–0.3 to VDD+0.3 V
EIO output current IO20 mA
Operating temperature Topr –40 to + 85 °C
Storing temperature 1 Tstg 1–65 to +150 °C
VDD=0V
System side
VV
V
V
V
V
V
V
CC DD
SS
5
3
2
GND 5V
DD
–5V
–28V
0
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S1D16006 Series
1–10 EPSON Rev.2.1
Symbol
VSS
V5
V5
V0
V2
V3
VIH
VIL
VOH
VOL
ILI
ILI/O
ISS
RSEG
ISS
I5
CI
CI/O
Condition
–
VSS=–2.7 to –5.5V
Function
Recommended value
Recommended value
Recommended value
VSS=–2.7 to –5.5V
VSS=–2.7 to –5.5V
IOH=–0.6mA
IOL=0.6mA
VSS ≤VIN ≤VDD
VSS ≤VIN ≤VDD
V5=–28.0 to –14.0V
VIH=VDD, VIL=VSS
∆VON=0.5V
V5=–20.0V V3=13/15·V5
V2=2/15·V5V0=VDD
Ta=25°C
VSS=–5.0V, VIH=VDD
VIL=VSS,fXSCL=2.69MHz
fLP=16.8KHz, fFR=70Hz
Input data: Dice display at no
load
VSS=–3.0V
Other conditions are the
same as VSS = -5 V
VSS=–5.0V,
V0=0.0V, V2=–9.3V
V3=–18.6V, V5=–28.0V
Other conditions are the
same as in the item of ISS.
Freq.=1MHz
Ta=25°C
By unit of a chip
Min.
–5.5
–28.0
–
VDD–2.5
3/9V5
V5
0.2VSS
–
VDD–0.4
–
–
–
–
–
–
–
–
–
–
Typ.
–5.0
–
–
–
–
–
–
–
–
–
–
–
–
1.2
0.10
0.07
0.05
–
–
Max.
–2.7
–12.0
–8.0
VDD
–
6/9V5
–
0.8VSS
–
VSS+0.4
2.0
5.0
25
1.6
0.2
0.15
0.08
8
15
Unit
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
kΩ
mA
mA
pF
pF
Applicable pin
VSS
V5
V5
V0
V2
V3
EIO1, EIO2, FR,
D0 to D3, XSCL,
SHL, LP
EIO1, EIO2
D0 to D3, LP, FR
XSCL, SHL
EIO1, EIO2
VSS
O0 to O79
VSS
V5
D0 to D3, LP, FR
XSCL, SHL
EIO1, EIO2
Parameter
Supply voltage (1)
Recommended
operating voltage
Operation enable voltage
Supply voltage (2)
Supply voltage (3)
Supply voltage (4)
HIGH input voltage
LOW input voltage
HIGH output voltage
LOW output voltage
Input leakage
current
Input/output
leakage current
Static current
Output resistance
Average operating
current
consumption (1)
Average operating
current
consumption (2)
Input pin
capacitance
Input/output pin
capacitance
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Unless otherwise specified, VDD = V0= 0V, VSS = –5.0V±10% and Ta = –40 to 85°C.
10. ELECTRICAL CHARACTERISTICS
DC characteristics
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S1D16006 Series
Rev.2.1 EPSON 1–11
VSS=–5.0V±0.5V, Ta=–40 to 85°C
Parameter Symbol Condition Min. Max. Unit
XSCL period tC– 100 – ns
XSCL HIGH pulsewidth tWCH –30–ns
XSCL LOW pulsewidth tWCL –30–ns
Data setup time tDS –20–ns
Data hold time tDH –10–ns
XSCL-rise to LP-rise time tLD –0–ns
LP-fall to XSCL-fall time tLH –40–ns
LP HIGH pulsewidth tWLH *3 40 – ns
Allowable FR delay time tDF – –900 +900 ns
EIO setup time tSUE –35–ns
VSS=–4.5V to –2.7V, Ta=–40 to 85°C
Parameter Symbol Condition Min. Max. Unit
VSS=–2.7V *1 153 –
XSCL period tCns
VSS=–3.0V *2 133 –
XSCL HIGH pulsewidth tWCH –50–ns
XSCL LOW pulsewidth tWCL –50–ns
Data setup time tDS –30–ns
Data hold time tDH –15–ns
XSCL-rise to LP-rise time tLD –0–ns
VSS=–2.7V 75 –
LP-fall to XSCL-fall time tLH ns
VSS=–3.0V 65 –
VSS=–2.7V *3 75 –
LP HIGH pulsewidth tWLH ns
VSS=–3.0V *3 65 –
Allowable FR delay time tDF – –900 +900 ns
VSS=–2.7V 60 –
EIO setup time tSUE ns
VSS=–3.0V 51 –
*1 Equivalent to 6.5 MHz
*2 Equivalent to 7.5 MHz
*3 tWLH stipulates the time when LP is HIGH and XSCL is LOW.
*4 trand tfof input signal are stipulated by unit of 20 ns.
*5 At a high-speed operation, trand tf = {tC– (tDCL + tSUE)}/2
t WLH t DF
t LH
t WCH t WCL
t C
t
SUE
t DH t DS
t LD
FR
LP
XSCL
D3 to D0
EI01,2
(IN)
V IH =0.2 ×V SS
V IL =0.8 ×V SS
AC Characteristics
Input timing characteristics
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S1D16006 Series
1–12 EPSON Rev.2.1
FR
LP t
ER
t LSD
t FRSD
t DCL
XSCL
EIO1, 2
(OUT) V
ON =0.2 ×V SS
V OL =0.8 ×V SS
O n
(SEG) Vn–0.5 Vn+0.5
V IH =0.2 ×V SS
V IL =0.8 ×V SS
VDD=–5.0±0.5V, V5=–12.0 to –28.0V
Parament Symbol Condition Min. Max. Unit
EIO reset time tER –90ns
CL=15pF (EIO)
EIO output delay time tDCL –55ns
LP to SEG output delay time tLSD – 200 ns
CL=100pF (On)
FR to SEG output delay time tFRSD – 400 ns
VDD=–4.5V to 2.7V, V5=–12.0 to –28.0V
Parament Symbol Condition Min. Max. Unit
EIO reset time tER – 150 ns
CL=15pF
VSS=–2.7V – 88 ns
EIO output delay time tDCL (EIO) VSS=–3.0V – 77 ns
LP to SEG output delay time tLSD – 400 ns
CL=100pF (On)
FR to SEG output delay time tFRSD – 800 ns
*1 trand tf of input signal are stipulated by unit of 20 ns.
*2 At a high-speed operation, trand tf= {tC– (tDCL + tSUE)}/2
Output timing characteristics
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