Epson S1R72105 User manual

Technical Manual
SCSI Interface Controller
S1R72105
MF1530-01

NOTICE
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permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
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©SEIKO EPSON CORPORATION 2002, All rights reserved.
All other product names mentioned herein are trademarks and/or registered trademarks of their respective
companies.

Configuration of product number
DEVICES
S1 R 72105 F 00A0 00
Packing specifications
00: Besides tape & reel
0A: TCP BL 2 directions
0B: Tape & reel Back
0C: TCP BR 2 directions
0D: TCP BT 2 directions
0E: TCP BD 2 directions
0F: Tape & reel FRONT
0G:TCP BT 4 directions
0H: TCP BD 4 directions
0J: TCP SL 2 directions
0K: TCP SR 2 directions
0L: Tape & reel LEFT
0M:TCP ST 2 directions
0N: TCP SD 2 directions
0P: TCP ST 4 directions
0Q:TCP SD 4 directions
0R: Tape & reel RIGHT
99: Specs not fixed
Specifications
Shape
(F : QFP)
Model number
Model name
(R : Exclusive use controller, Peripheral)
Product classification
(S1:Semiconductors)

Rev.1.0 EPSON i
CONTENTS
1. DESCRIPTION..................................................................................................................................1
2. FEATURES .......................................................................................................................................1
3. BLOCK DIAGRAM ...........................................................................................................................2
4. PIN ASSIGNMENT ...........................................................................................................................3
5. PIN DESCRIPTION...........................................................................................................................4
6. FUNCTIONAL DESCRIPTION.........................................................................................................6
6.1 CPU Interface Circuit..................................................................................................................6
6.2 Internal Registers........................................................................................................................6
6.3 Port Interface Circuit...................................................................................................................6
6.4 DMA Control Circuit....................................................................................................................6
6.5 SCSI-2 (3) Interface Circuit ........................................................................................................6
6.6 USB Interface Circuit..................................................................................................................7
6.7 PLL Circuit (Internal System Clock Generating Section)...........................................................7
7. FUNCTION OF REGISTERS............................................................................................................9
7.1 List of Registers..........................................................................................................................9
7.1.1 List of Register/Window Settings (USB) ......................................................................11
7.2 List of Registers/Bits.................................................................................................................13
7.2.1 List of Registers/Bits/List of Window Configuration (USB) List of Bits ........................15
7.3 Detailed Description of Each Register......................................................................................17
7.3.1 Main Interrupt Status (MainIntStat) R/W ...................................................................17
7.3.2 EPr Interrupt Status(EPrIntStat) R/W........................................................................18
7.3.3 Interrupt Status Window 0(IntStatWindow_0) R/W...................................................18
7.3.4 Interrupt Status Window 1(IntStatWindow_1) R/W...................................................19
7.3.5 Main Interrupt Enable(MainIntEnb) R/W ...................................................................19
7.3.6 EPr Interrupt Enable(EPrIntEnb) R/W.......................................................................19
7.3.7 Interrupt Enable Window 0(IntEnbWindow_0) R/W..................................................20
7.3.8 Interrupt Enable Window 1(IntEnbWindow_1) R/W..................................................20
7.3.9 Interrupt Index(IntIndex) R/W....................................................................................20
7.3.10 System Control(SystemCtrl) R/W...............................................................................21
7.3.11 USB Common(USBCommon) R/W............................................................................21
7.3.12 Reset(Reset) R/W......................................................................................................22
7.3.13 Port DMA Control(PortDMACtrl) R/W ........................................................................22
7.3.14 Port DMA Size High(PortDMASize_H) R/W ..............................................................23
7.3.15 Port DMA Size Middle(PortDMASize_M) R/W...........................................................23
7.3.16 Port DMA Size Low(PortDMASize_L) R/W................................................................23
7.3.17 Port Config 0 (PortConfig_0) R/W..............................................................................24
7.3.18 Port Config 1(PortConfig_1) R/W...............................................................................25
7.3.19 USB Index(USBIndex) R/W .......................................................................................26
7.3.20 USB Window 0(USBWindow_0) R/W........................................................................26
7.3.21 USB Window 1(USBWindow_1) R/W........................................................................26
7.3.22 USB Window 2(USBWindow_2) R/W........................................................................27
7.3.23 USB Window 3(USBWindow_3) R/W........................................................................27
7.3.24 USB Window 4(USBWindow_4) R/W........................................................................27
7.3.25 USB Window 5(USBWindow_5) R/W........................................................................28

ii EPSON Rev.1.0
7.3.26 USB Window 6(USBWindow_6) R/W........................................................................28
7.3.27 USB Window 7(USBWindow_7) R/W........................................................................28
7.3.28 Main Interrupt Status SCSI (MAININTS) R/W ...........................................................29
7.3.29 SCSI Interrupt Status 1 (SCSIINT1) R/W ..................................................................30
7.3.30 SCSI Interrupt Status 2 (SCSIINT2) R/W ..................................................................31
7.3.31 SCSI Mode Select0 (SCSIMODE0) R/W...................................................................32
7.3.32 SCSI Mode Select1 (SCSIMODE1) R/W...................................................................33
7.3.33 SCSI Control (SCSICTL) R/W....................................................................................34
7.3.34 SCSI Data (SCSIDATA) R/W .....................................................................................34
7.3.35 Synchronize Transfer Mode (SYNCMODE) R/W.......................................................35
7.3.36 SCSI Own ID (OWNID) R/W......................................................................................35
7.3.37 Source/Destination ID (SDID) R/W............................................................................36
7.3.38 Selection Timeout Counter (SLTIME) R/W ................................................................36
7.3.39 FIFO Control (FIFOCTL) R/W....................................................................................37
7.3.40 FIFO Data(FIFODATA) R/W.......................................................................................37
7.3.41 Non DMA Transfer Size (NDMASIZ) R/W .................................................................37
7.3.42 SCSI Command (COMMAND) R/W...........................................................................38
7.3.43 Test(TEST) R..............................................................................................................38
7.3.44 Revision Reg. (REVISION) R.....................................................................................38
7.4 Detailed Description of Set Values of INTINDEX Register ......................................................39
7.4.1 Register Showing IntStatWindow_0,1 and IntEnbWindow_0,1 for Set Values of
IntIndex Register.........................................................................................................39
7.4.2 EP{r}(r=0,a,b,c) Interrupt Status(EP{r}IntStat) R/W ..................................................39
7.4.3 EP{r}(r=0,a,b,c) Interrupt Enable(EP{r}IntEnb) R/W .................................................40
7.5 Detailed Description of Set Values of USBIndex Register.......................................................41
7.5.1 List of Registers Showing USBWindow Register (8 bytes) Corresponding to
Set Values of USBIndex Register(17h)......................................................................41
7.5.2 Description of Registers by Set Value of USBIndex....................................................42
7.5.2.1 USB Address(USBAddress) R/W................................................................42
7.5.2.2 EP0 Config 1(EP0Config_1) R/W................................................................42
7.5.2.3 EP0 In Transaction Control(EP0InControl) R/W .........................................43
7.5.2.4 EP0 OUT Transaction Control(EP0OutControl) R/W..................................44
7.5.2.5 EP0 FIFO remain Counter(EP0FIFOremain) R ..........................................45
7.5.2.6 EP0 FIFO for CPU(EP0FIFOforCPU) R/W .................................................45
7.5.2.7 EP0 FIFO Control(EP0FIFOCtrl) R/W.........................................................46
7.5.2.8 EP{r}(r=a,b,c) Config 0(EPrConfig_0) R/W...............................................47
7.5.2.9 EP{r}(r=a,b,c) Config 1(EPrConfig_1) R/W...............................................47
7.5.2.10 EP{r}(r=a,b,c) Control(EPrControl) R/W....................................................48
7.5.2.11 EP{r}(r=a,b,c) FIFO remain Counter(EPrFIFOremain) R..........................49
7.5.2.12 EPr FIFO for CPU(EPrFIFOforCPU) R/W.................................................49
7.5.2.13 EPr FIFO Control(EPrFIFOCtrl) R/W ........................................................50
7.5.2.14 EP0 SETUP[n](n=0,1,2,3,4,5,6,7) (EP0SETUP[n]) R...............................50
7.5.2.15 Frame Number H(FrameNumber_H) R.....................................................51
7.5.2.16 Frame NumberL(FrameNumber_L) R.......................................................51
7.6 SCSI Control Commands.........................................................................................................52
7.6.1 Control Commands and Command Codes..................................................................52
7.6.2 Description of Each Control Command........................................................................52
7.6.3 Command Execution and Change of State..................................................................60

Rev.1.0 EPSON iii
7.7 Others and Cautions in Operation............................................................................................60
8. ELECTRICAL CHARACTERISTICS..............................................................................................62
8.1 Absolute Maximum Ratings......................................................................................................62
8.2 Recommended Operating Conditions......................................................................................62
8.3 DC Characteristics....................................................................................................................62
8.4 AC Characteristics....................................................................................................................65
8.4.1 CPU Interface...............................................................................................................66
8.4.1.1 Register Read Timing..................................................................................66
8.4.1.2 Register Write Timing ..................................................................................67
8.4.2 SCSI Interface..............................................................................................................68
8.4.2.1 Selection Timing ..........................................................................................68
8.4.2.2 Re-selection Timing.....................................................................................69
8.4.2.3 Timing of Being Selected ...........................................................................70
8.4.2.4 Timing of Being Selected.............................................................................71
8.4.2.5 XSATN Output Timing..................................................................................72
8.4.2.6 Initiator Asynchronous Data-out Timing (Data output)................................73
8.4.2.7 Initiator Asynchronous Data-in Timing (Data input) ...................................74
8.4.2.8 Initiator Synchronous Data-out Timing (Data output) ................................75
8.4.2.9 Initiator Synchronous Data-in Timing (Data input) ....................................76
8.4.2.10 Target Asynchronous Data-in Timing (Data output) ...................................77
8.4.2.11 Target Asynchronous Data-out Timing (Data input) ...................................78
8.4.2.12 Target Synchronous Data-in Timing (Data output) .....................................79
8.4.2.13 Target Synchronous Data-out Timing (Data input) .....................................80
8.4.3 Port Interface................................................................................................................81
8.4.3.1 DMA Read (PSLV=1: Slave mode) ............................................................81
8.4.3.2 DMA Write (PSLV=1: Slave mode) ............................................................82
8.4.3.3 DMA Write (PSLV=0: Master mode) ..........................................................83
8.4.3.4 DMA Read (PSLV=0: Master mode) ..........................................................84
8.4.4 Others...........................................................................................................................85
8.4.4.1 OSCIN Input Clock ( ex.40MHz)..................................................................85
8.4.4.2 EXCLK Input Clock (48MHz).......................................................................86
8.4.4.3 XRESET Input Pulse Width.........................................................................87
8.4.4.4 USB Interface Access Timing......................................................................87
9. EXAMPLES OF CONNECTION.....................................................................................................88
10. EXTERNAL DIMENSIONS DRAWING..........................................................................................90

S1R72105 Technical Manual
Rev.1.0 EPSON 1
1. DESCRIPTION
S1R72105 contains the SCSI-3 interface controller and the USB 1.1 controller that support SCAM and FAST20
transfer, which is capable of bridging general-purpose I/O port and IDE DMA port as well as SCSI and USB
interfaces.
2. FEATURES
«CPU Interface»
 It can be connected to a general-purpose CPU
«SCSI Interface»
 Compatible with SCSI-2 (10Mbps (synchronous), 5Mbps (asynchronous))
 Compatible with SCSI-3 FAST20 (20Mbps (synchronous)) transfer
 Compatible with SCAM Lv.1 (compatible with Lv.2 with firmware)
 Automatic processing of phase control
 Built-in single end driver
 Active negation I/O mounted
«USB Interface»
 Compatible with full speed mode (12Mbps) transfer
 Compatible with control transfer by endpoint 0 and bulk and interrupt transfers by three individual
endpoints
 Split of the built-in SRAM (256 bytes) is programmable by user definition
In addition to two-way endpoint 0, a maximum of three endpoints can be set
«PORT Interface»
 General-purpose 8/16 bit-selectable purpose interface
 It allows selection between master and slave
 Since it allows DMA connection to IDE(ATAPI), IDE (ATAPI) equipment can be easily turned into the
SCSI and USB equipment
«Others»
 Built-in oscillation circuit: 20MHz/40MHz
 Built-in PLL circuit (generates both USB and SCSI clocks from 20MHz oscillation)
 100 pin QFP (0.5 mm pitch)
 Supply voltage: 5.0V±10% and 3.3V±0.3V
 No anti-radiation design

S1R72105 Technical Manual
2 EPSON Rev.1.0
3. BLOCK DIAGRAM
Port interface section
Master mode control
Slave mode control
SCSI-3 interface section
XPDREQ
XPDACK
PD15-0
XPRD
XPWR
Sequence
control
Command
analysis and
execution
Asynchro-
nous transfer
control
Parity
GEN/CHK
FIFO
(16Byte)
DMA control
FIFO control
Synchronous
transfer
SCAM
control
XSRST
XSDP
XSREQ
XSATN
XSIO
XSCD
XSMSG
XSSEL
XSD7-0
XPUENB
XSACK
CPU interface section
Timing control
Interrupt control
Data MPX
DMA control section
Start-up/stop control
AD5-0
XCS
XRD
Phase
control
USB1.1 interface
FIFO (256Byte)
Serial
Interface
Engine
Transfer
control
ENDPOINTs
control
XUSBOE
V BUS
DP
DM
Internal register
DB7-0
XWR
XRESET
TEST
Bus control
Clock control section
Clock
distribution
40/48 MHz
Generating PLL
EXCLK
V
C
OSCOUT
OSCIN
CLKSEL
X-NT
XSDP
XSBSY

S1R72105 Technical Manual
Rev.1.0 EPSON 3
4. PIN ASSIGNMENT
S1R72105F0A (QFP15-100pin)
VSS XSRST XSMSG VSS XSSEL XSCD VSS XSREQ HVDD XSIO VSS VC CLKSEL EXCLK LVDD OSCOUT OSCIN VSS PD7(15) PD8(14) PD6(13) PD9(12) PD5(11) PD10 HVDD
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
LVDD 76 50 VSS
HVDD 77 49 PD4(9)
XSACK 78 48 PD11(8)
VSS 79 47 PD3(7)
XSBSY 80 46 PD12(6)
XSATN 81 45 PD2(5)
HVDD 82 44 HVDD
XSDBP 83 43 PD13(4)
VSS 84 42 PD1(3)
XSDB7 85 41 PD14(2)
HVDD 86 40 PD0(1)
XSDB6 87 39 PD15(0)
VSS 88 38 VSS
XSDB5 89 37 PDREQ
HVDD 90 36 XPWR
XSDB4 91 35 XPRD
VSS 92 34 XPDACK
XSDB3 93 33 HVDD
HVDD 94 32 XRESET
XSDB2 95 31 XCS
VSS 96 30 XINTU
XSDB1 97 29 XINTS
HVDD 98 28 XRD
XSDB0 99 27 XWR
VSS 100 26 LVDD
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
LVDD
DM
DP
VSS
XPUENB
VBUS
XUSBOE
TESTMON
TESTEN
DB0 DB1 DB2 DB3
HVDD
DB4 DB5 DB6 DB7 AD0 AD1 AD2 AD3 AD4 AD5
VSS
INDEX
EPSO
TOP View
INDEX
S1R72105
EPSO
TOP View
INDEX
EPSO
TOP View
INDEX
EPSON

S1R72105 Technical Manual
4 EPSON Rev.1.0
5. PIN DESCRIPTION
The control signal with “X” at the head of a pin name is LOW-active.
Pin No. Symbol I/O Functional description Remarks
SCSI interface-related matters (18)
99 XSDB0
97 XSDB1
95 XSDB2
93 XSDB3
91 XSDB4
89 XSDB5
87 XSDB6
85 XSDB7
SCSI data signal (SD0 to SD7) Drive capability 48mA
83 XSDBP
Is/Otr
SCSI data parity signal Drive capability 48mA
81 XSATN I/Ood SCSI ATN signal Drive capability 48mA
80 XSBSY I/Ood SCSI BSY signal Drive capability 48mA
78 XSACK Is/Otr SCSI ACK signal Drive capability 48mA
74 XSRST I/Ood SCSI RST signal Drive capability 48mA
73 XSMSG I/Ood SCSI MSG signal Drive capability 48mA
71 XSSEL I/Ood SCSI SEL signal Drive capability 48mA
70 XSCD I/Ood SCSI C/D signal Drive capability 48mA
68 XSREQ Is/Otr SCSI REQ signal Drive capability 48mA
66 XSIO I/Ood SCSI I/O signal Drive capability 48mA
USB interface-related matters (5)
2 DM I/O USB data port
3 DP I/O USB data port
(Configure to pull up to 3.3V by a 1.5kΩresistor externally.
The register can be controlled by “XPUENB.”)
5 XPUENB Ood Control signal connecting a 1.5kΩpull-up resistor to “DP”
pin Ood.
VBUS = 5V and HIGH EnPullUp(USBCommon_b1) brings
about LOW output.
Drive capability 6mA
6 VBUS Is USB bus power detection input (Pull down externally).
7 XUSBOE O LOW output while this IC outputs a signal to DP and DM
pins. Drive capability 3mA
Port interface-related matters (20)
35 XPRD Is/O Port read signal Drive capability 3mA
36 XPWR Is/O Port write signal Drive capability 3mA
37 PDREQ Is/O Port DMA request signal (also operable in negative logic) Drive capability 6mA
34 XPDACK Is/O Port DMA ACK signal Drive capability 3mA
40 PD0
42 PD1
45 PD2
47 PD3
49 PD4
53 PD5
55 PD6
57 PD7
56 PD8
54 PD9
52 PD10
48 PD11
46 PD12
43 PD13
41 PD14
39 PD15
I/O Port DMA data bus signal (PD0 to 15) Drive capability 3mA

S1R72105 Technical Manual
Rev.1.0 EPSON 5
Pin No. Symbol I/O Functional description Remarks
CPU interface-related matters (19)
19 AD0 I Address input pin (AD0 to AD5)
20 AD1
21 AD2
22 AD3
23 AD4
24 AD5
10 DB0 I/O Data pin (DB0 to DB7)
11 DB1
12 DB2
13 DB3
15 DB4
16 DB5
17 DB6
18 DB7
Drive capability 3mA
31 XCS Is Chip select signal for accessing internal register
30 XINTU O USB interrupt request output signal Drive capability 6mA
29 XINTS O SCSI interrupt request output signal Drive capability 6mA
28 XRD Is Data read signal
27 XWR Is Data write signal
Others (17)
59 OSCIN I Input to built-in oscillation circuit (40MHz or 20MHz)
60 OSCOUT O Output from built-in oscillation circuit
8 TESTMON O Monitor output for testing (open LOW output usually) Drive capability 2mA
32 XRESET Ispu System reset input signal
9 TESTEN Ipd Pin for testing (connected to LOW (GND) usually)
63 CLKSEL I Input clock and PLL operation selection
HIGH (LVDD): Generates clock (SCSI_40MHz,USB_48MHz)
in internal PLL.
20MHz oscillation in OSCIN/OUT or input
20MHz(3.3V) to OSCIN
EXCLK is connected to LOW (GND) or HIGH
(LVDD).
LOW (GND): PLL stop (power-down) , external clock in
operation
40MHz oscillation in OSCIN/OUT or input
40MHz(3.3V) to OSCIN
Input 48MHz(3.3V) to EXCLK
62 EXCLK I External clock input pin for 3.3V level USB
(Connected to LOW (GND) or HIGH (LVDD) while it is not
used).
64 VCO For instructions as to how to connect internal VCO control
pins, refer to the description of PLL circuit.
HVDD:5V (5)
14,33,44,51,
67,77,82,86,
90,94,98
HVDD P Power supply for 5V interface
LVDD:3.3V (6)
1,26,61,76
LVDD P Power supply for internal operation
VSS:0V (17)
4,25,38,50,
58,65,69,72,
75,79,84,88,
92,96,100
VSS P GND
(Note) I : Input O : Output
Is : Schmitt input Ood : Open-drain output
Ipu : Pull-up input Otr : Try state output
Ispu : Pull-up Schmitt input Ipd : Pull-down input

S1R72105 Technical Manual
6 EPSON Rev.1.0
6. FUNCTIONAL DESCRIPTION
6.1 CPU Interface Circuit
This block can be interfaced to a general-purpose CPU. It generally controls the interface with the CPU.
When the XCS signal from the CPU is LOW, the block can access the internal register. It decodes the address
bus AD5 to AD0 to generate the address of the internal register. At this time, it generates the read/write strobe
signal from the XRD/XWR signal, transferring data between the internal register. A wait signal to the CPU is
not generated because of no-wait operation.
6.2 Internal Registers
Refer to the section of Register Functions as for the addresses of the internal registers and description of each
bit. The main functions of this block are as follows:
(1) It generates control signals to each block according to the address, write-data and write-strobe signals
generated by the CPU interface circuit.
(2) It stores the status signals from each block, and outputs data according to the address and read-strobe
signals sent from the CPU interface circuit.
6.3 Port Interface Circuit
This is a block controlling the transfer to and from the external DMA port. It has the following functions:
(1) It controls the linkage operation of each functional block according to the control signal and the
stop-operation signal sent from the DMA control circuit.
(2) It controls the transfer status of the external port according to PDREQ/XPDACK signals.
(3) It reads/writes data of the data bus PD15-0 of the port from/to FIFO in the SCSI-2 block. When transfer
is disabled in the full/empty state of SCSI_FIFO, transfer to and from the port is temporarily halted
according to the timing specified by the PDREQ/XPDACK signals.
(4) The port allows selection of bit width betweem 8 and 16.
(5) The port interface allows selection between the master and slave function (toward PDREQ/XPDACK/XPRD/XPWR
direction).
6.4 DMA Control Circuit
This block controls the transfer between the DMA port and FIFO in the SCSI block and FIFO in the USB block.
It has the following functions:
(1) It controls the linkage operation of each functional block according to the control signal from the internal
register and the information and stop-operation signals from each block.
(2) It stores the status of each of functional blocks when their linkage operation ends, reporting it to the
internal register at the specified timing.
6.5 SCSI-2 (3) Interface Circuit
This block generally controls the interfaces conforming to the SCSI-2 standard. It has the following functions:
(1) It automatically performs the SCSI protocol control on hardware.
(2) It has 16-staged off-set counter to control the off-set and transfer rate during synchronous transfer.
(3) In the command phase, it automatically distinguishes groups of commands received (in Target mode).
(4) It controls the automatic status/message transfer function. It supports the messages 00h/0Ah/0Bh.
(in Target mode).
(5) It allows SCSI-3 FAST20(20Mbps) transfer.
SCAM compatibility
In addition to conventional SCSI, this LSI has SCAM (SCSI Configured Auto Magnify)-compatible functions
as listed below:
These functions enable the device to operate as a SCAM Lv.1 drive.
(1) It monitors and recognizes the SCAM selection and causes an interruption.
(2) It responds to the selection response delay of 4ms or more, which enables distinction between SCAM and
ordinary selections.
(3) It can operate SCSI bus’s signal line directly because of its actual operation responding to the SCAM
selection and sending/receiving data.

S1R72105 Technical Manual
Rev.1.0 EPSON 7
6.6 USB Interface Circuit
(1) It supports full speed device in conformity to the USB1.1 (It does not support low speed).
It supports control transfer (endpoint 0), bulk transfer, and interrupt transfer (It does not support
isochronous transfer).
(2) Split of the built-in SRAM (256 bytes) is programmable by user definition.
In addition to two-way endpoint 0, a maximum of three endpoints can be set.
Three endpoints can be independently set to IN/OUT direction, any of four maximum packet lengths (8, 16,
32 or 64 bytes), any endpoint number, and buffer size (single or double).
6.7 PLL Circuit (Internal System Clock Generating Section)
This IC has the function to generate 40MHz(SCSI) and 48MHz(USB) required for the internal circuit from the
clock generated by the oscillation circuit by using the PLL circuit.
The block diagram around the oscillation section is shown below:
• The IC enables easy setup of an oscillation circuit by connecting a crystal vibrator and feedback resistor
(For characteristics of the crystal vibrator, contact us separately).
• It allows oscillation of 20MHz by means of the oscillation circuit mentioned above.
In this case, 40MHz and 48MHz required for each block of SCSI and USB are generated by using the
internal PLL. So connect the EXCLK pin to LVDD or GND (CLKSEL = LVDD).
• The IC allows operation by inputting a 40MHz external clock of 3.3V level to the OSCIN pin or 40MHz
oscillation and inputting a 48MHz external clock of 3.3V level to the EXCLK pin without using the
internal PLL. In this case, connect the CLKSEL to the “GND” to stop operation of the PLL block.
PLL
LV
DD
or GND
V
C
4.7k
Ω
100pF
GND
(20MHz/40MHz)
OSCOUT
5pF
GND
5pF
GND
OSCIN
1M
Ω
EXCLK
B(0)
Y
A(1)
S
B(0)
Y
A(1)
S
SCSI
40MHz
USB
48MHz
GND
3pF
CLKSEL
Internal clock

S1R72105 Technical Manual
8 EPSON Rev.1.0
Depending on the usage, set the control signal as shown below:
- When an oscillator circuit (20MHz) is
used
- When a 20 MHz clock of 3.3V level is
input from the OSCIN pin
(PLL is used)
- When an oscillator circuit (40MHz) is
used
- When a 40 MHz clock of 3.3V level is
input from the OSCIN pin
(PLL is not used)
Oscillation/input
clock 20MHz 40MHz
CLKSEL LVDD GND
EXCLK LVDD or GND Input 48MHz(3.3V)
• PLLcircuitspecifications Ta=0to70°C LVDD=3.3V±0.3V
Item Specifications
Lock-up time Within 1ms after oscillation was stabilized
Jitter Within ±1ns

S1R72105 Technical Manual
Rev.1.0 EPSON 9
7. FUNCTION OF REGISTERS
7.1 List of Registers
Address Register name Abbreviated name
00h Main Interrupt Status MainIntStat
01h Epr Interrupt Status EPrIntStat
02h Interrupt Status Window_0 IntStatWindow_0
03h Interrupt Status Window_1 IntStatWindow_1
04h Main Interrupt Enable MainIntEnb
05h Epr Interrupt Enable EPrIntEnb
06h Interrupt Enable Window_0 IntEnbWindow_0
07h Interrupt Enable Window_1 IntEnbWindow_1
08h Interrupt Index IntIndex
09h System Control SystemCtrl
0Ah USB Common USBCommon
0Bh - Reserved -
-
0Ch - Reserved -
-
0Dh Reset Reset
0Eh - Reserved -
-
0Fh - Reserved -
-
10h Port DMA Control PortDMACtrl
11h Port DMA Size_H PortDMASize_H
12h Port DMA Size_M PortDMASize_M
13h Port DMA Size_L PortDMASize_L
14h Port Configuration_0 PortConfig_0
15h Port Configuration_1 PortConfig_1
16h - Reserved -
-
17h USB Index USBIndex
18h USB Window_0 USBWindow_0
19h USB Window_1 USBWindow_1
1Ah USB Window_2 USBWindow_2
1Bh USB Window_3 USBWindow_3
1Ch USB Window_4 USBWindow_4
1Dh USB Window_5 USBWindow_5
1Eh USB Window_6 USBWindow_6
1Fh USB Window_7 USBWindow_7

S1R72105 Technical Manual
10 EPSON Rev.1.0
Address Register name Abbreviated name
20h Main Interrupt Status SCSI MAININTS
21h SCSI Interrupt status 1 SCSIINT1
22h SCSI Interrupt status 2 SCSIINT2
23h - Reserved -
-
24h - Reserved -
-
25h - Reserved -
-
26h - Reserved -
-
27h - Reserved -
-
28h - Reserved -
-
29h SCSI Mode 0 SCSIMODE0
2Ah SCSI Mode 1 SCSIMODE1
2Bh SCSI Control SCSICTL
2Ch SCSI Synchronous data transfer Mode SCSIDATA
2Dh SCSI DATA SYNCMODE
2Eh SCSI Own ID OWNID
2Fh SCSI Source/Destination ID SDID
30h SCSI Selection Timeout Counter SELTIME
31h SCSI FIFO Control FIFOCTL
32h SCSI FIFO Data FIFODATA
33h SCSI Non-DMA Transfer Size NDMASIZE
34h SCSI Command COMMAND
35h - Reserved -
-
36h - Reserved -
-
37h - Reserved -
-
38h - Reserved -
-
39h - Reserved -
-
3Ah - Reserved -
-
3Bh - Reserved -
-
3Ch - Reserved -
-
3Dh - Reserved -
-
3Eh Test TEST
3Fh REVISION REVISION

S1R72105 Technical Manual
Rev.1.0 EPSON 11
7.1.1 List of Register/Window Settings (USB)
• Details appearing in IntStatWindow_0(02h)
IntIndex(08h) 4 higher
order bits
(bit7,6,5,4)
Function of IntStatWindow_0
register Description on display
0h EP0IntStat Endpoint 0 status display/clear
1h EPaIntStat Endpoint a status display/clear
2h EPbIntStat Endpoint b status display/clear
3h EPcIntStat Endpoint c status display/clear
• Details appearing in IntStatWindow_1(03h)
IntIndex(08h) 4 lower
order bits
(BIT3,2,1,0)
Function of IntStatWindow_1
register Description on display
0h EP0IntStat Endpoint 0 status display/clear
1h EPaIntStat Endpoint a status display/clear
2h EPbIntStat Endpoint b status display/clear
3h EPcIntStat Endpoint c status display/clear
• Details appearing in IntEnbWindow_0(06h)
IntIndex(08h) higher
order 4 bits
(bit7,6,5,4)
Function of IntEnbWindow_0
register Description on display
0h EP0IntEnb Endpoint 0 status interrupt enabled
1h EPaIntEnb Endpoint a status interrupt enabled
2h EPbIntEnb Endpoint b status interrupt enabled
3h EPcIntEnb Endpoint c status interrupt enabled
• Details appearing in IntEnbWindow_1(07h)
IntIndex(08h) 4 lower
order bits
(bit3,2,1,0)
Function of IntEnbWindow_1
register Description on display
0h EP0IntEnb Endpoint 0 status interrupt enabled
1h EPaIntEnb Endpoint a status interrupt enabled
2h EPbIntEnb Endpoint b status interrupt enabled
3h EPcIntEnb Endpoint c status interrupt enabled

S1R72105 Technical Manual
12 EPSON Rev.1.0
• Details appearing in USBWindow_0(18h) to USBWindow_0(1Fh)
USBIndex(17h) Register name Description on display
00h USBWindow_0(18h) USBAddress: USB address
USBWindow_1(19h) EP0Config_1：EP0 configuration
USBWindow_2(1Ah) EP0InControl: EP0 IN Transaction control
USBWindow_3(1Bh) EP0OutControl: EP0 OUT Transaction control
USBWindow_4(1Ch) (Reserved)
USBWindow_5(1Dh) EP0FIFOremain: EP0 FIFO counter
USBWindow_6(1Eh) EP0FIFOforCPU: EP0 FIFO for CPU access
USBWindow_7(1Fh) EP0FIFOCtrl: EP0 FIFO control
01h to 03h USBWindow_0(18h) EPrConfig_0:EP{r}(r=a,b,c) configuration
USBWindow_1(19h) EPrConfig_1:EP{r}(r=a,b,c) configuration
USBWindow_2(1Ah) EPrControl：EP {r} (r=a,b,c) Transaction control
USBWindow_3(1Bh) (Reserved)
USBWindow_4(1Ch) (Reserved)
USBWindow_5(1Dh) EPrFIFOremain：EP {r} (r=a,b,c) FIFO counter
USBWindow_6(1Eh) EPrFIFOforCPU：EP {r} (r=a,b,c) FIFO for CPU access
USBWindow_7(1Fh) EPrFIFOCtrl：EP {r} (r=a,b,c) FIFO control
08h USBWindow_0(18h) EP0_SETUP_0：EP0 SETUP stage receive data
USBWindow_1(19h) EP0_SETUP_1：EP0 SETUP stage receive data
USBWindow_2(1Ah) EP0_SETUP_2：EP0 SETUP stage receive data
USBWindow_3(1Bh) EP0_SETUP_3：EP0 SETUP stage receive data
USBWindow_4(1Ch) EP0_SETUP_4：EP0 SETUP stage receive data
USBWindow_5(1Dh) EP0_SETUP_5：EP0 SETUP stage receive data
USBWindow_6(1Eh) EP0_SETUP_6：EP0 SETUP stage receive data
USBWindow_7(1Fh) EP0_SETUP_7：EP0 SETUP stage receive data
09h USBWindow_0(18h)
FrameNumber_H: Higher order 3 bits in the FrameNumber field of the
SOF Packet received
USBWindow_1(19h)
FrameNumber_L: Lower order 8 bits in the FrameNumber field of the
SOF Packet received
USBWindow_2(1Ah) (Reserved)
USBWindow_3(1Bh) (Reserved)
USBWindow_4(1Ch) (Reserved)
USBWindow_5(1Dh) (Reserved)
USBWindow_6(1Eh) (Reserved)
USBWindow_7(1Fh) (Reserved)

S1R72105 Technical Manual
Rev.1.0 EPSON 13
7.2 List of Registers/Bits
Address Type Register name Default
value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
00h R/W MainIntStat 40/00h USB
resume USB
reset USB suspend Detect SOF Port
DMACmp SCSI RcvEP0
SETUP EPrlnt Stat
01h R/W EPrIntStat 00h
- - - -
EPclnt
Stat EPblnt Stat EPalnt Stat EP0lnt Stat
02h R/W IntStatWindow_0 00h IntStatWindow_0 (swiching by IntIndex_0)
03h R/W IntStatWindow_1 00h IntStatWindow_1 (swiching by IntIndex_1)
04h R/W MainIntEnb 00h EnUSB
resume EnUSB reset EnUSB suspend EnDetect SOF EnPort
DMACmp EnSCSI EnRcv
SETUP EnEPr IntStat
05h R/W EPrIntEnb 00h
- - - -
EnEPc
lnt EnEPb lnt EnEPa lnt EnEP0 lnt
06h R/W IntEnbWindow_0 00h IntEnWindow_0 (swiching by IntIndex_0)
07h R/W IntEnbWindow_1 00h IntEnWindow_1 (swiching by IntIndex_1)
08h R/W IntIndex 01h IntIndex_0 IntIndex_1
09h R/W SystemCtrl 03h
- - -
Go
Suspend Send Wakeup
-
xINT
mode1 xINT mode0
0Ah R/W USBCommon xxh VBUS
- - - -
IgnrTgl
Mis EnPull
Up Active USB
0Bh R/W
-
00h
- - - - - - - -
0Ch R/W
-
00h
- - - - - - - -
0Dh R/W Reset 00h PORT SCSI USB
0Eh R/W
-
00h
- - - - - - - -
0Fh R/W
-
00h
- - - - - - - -
10h R/W PortDMACtrl 00h MODE1 MODE0
- - - -
S_FIFO DTGO
11h R/W PortDMASize_H 00h DBC23 DBC22 DBC21 DBC20 DBC19 DBC18 DBC17 DBC16
12h R/W PortDMASize_M 00h DBC15 DBC14 DBC13 DBC12 DBC11 DBC10 DBC9 DBC8
13h R/W PortDMASize_L 00h DBC7 DBC6 DBC5 DBC4 DBC3 DBC2 DBC1 DBC0
14h R/W PortConfig_0 00h ACP BUSC PSLV
-
PRQLV SWAP ODS BUS8
15h R/W PortConfig_1 00h AP3 AP2 AP1 AP0 NP3 NP2 NP1 NP0
16h
- - - - - - - - - - -
17h R/W USBIndex 00h USBIndex
18h R/W USBWindow_0 00h USBWindow_0 (swiching by USBIndex)
19h R/W USBWindow_1 00h USBWindow_1 (swiching by USBIndex)
1Ah R/W USBWindow_2 00h USBWindow_2 (swiching by USBIndex)
1Bh R/W USBWindow_3 00h USBWindow_3 (swiching by USBIndex)
1Ch R/W USBWindow_4 00h USBWindow_4 (swiching by USBIndex)
1Dh R/W USBWindow_5 00h USBWindow_5 (swiching by USBIndex)
1Eh R/W USBWindow_6 00h USBWindow_6 (swiching by USBIndex)
1Fh R/W USBWindow_7 00h USBWindow_7 (swiching by USBIndex)

S1R72105 Technical Manual
14 EPSON Rev.1.0
Address Type Register name Default
value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
20h R/W MAININTS 00h GOOD SABT EXEC SCSI1 SCSI2
-
DTCMP ASCMP
21h R/W SCSIINT1 00h SPERR IDERR SELTO SATN BFREE ILPHS SCSEL WOATN
22h R/W SCSIINT2 00h
-
SRST OFERR UNDEF CMDER RESEL SEL LARBT
23h
- - - - - - - - - - -
24h
- - - - - - - - - - -
25h
- - - - - - - - - - -
26h
- - - - - - - - - - -
27h
- - - - - - - - - - -
28h
- - - - - - - - - - -
29h R/W SCSIMODE0 00h
- - -
ULTRA AUTO1 AUTO2 AN_C AN_D
2Ah R/W SCSIMODE1 00h STPPE ATNPE STATN AUTO RINH SINH DACS SPCEN
2Bh R/W SCSICTL 00h ACK ATN SEL BSY REQ MSG I/O C/D
2Ch R/W SCSIDATA 00h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
2Dh R/W SYNCMODE 00h RATE3 RATE2 RATE1 RATE0 OFF3 OFF2 OFF1 OFF0
2Eh R/W OWNID 00h
- - - - -
OID2 OID1 OID0
2Fh R/W SDID xxh
-
SID2 SID1 SID0
-
DID2 DID1 DID0
30h R/W SELTIME 00h ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0
31h R/W FIFOCTL 01h
- - - - -
FCLR FULL EMPTY
32h R/W FIFODATA xxh FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0
33h R/W NDMASIZE FFh NSZ7 NSZ6 NSZ5 NSZ4 NSZ3 NSZ2 NSZ1 NSZ0
34h R/W COMMAND 00h CMD7 CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0
35h
- - - - - - - - - - -
36h
- - - - - - - - - - -
37h
- - - - - - - - - - -
38h
- - - - - - - - - - -
39h
- - - - - - - - - - -
3Ah
- - - - - - - - - - -
3Bh
- - - - - - - - - - -
3Ch
- - - - - - - - - - -
3Dh
- - - - - - - - - - -
3Eh R TEST 00h TM2 TM1 TM0 USEL1 USEL0 OFST SCBC DMBC
3Fh R/W REVISION 00h REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0