Epson S1D13700 User manual

Technical Manual
LCD Controller ICs
S1D13700
MF1542-01

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✽In this manual, Zilog's Z80-CPU or its equivalent shall be called Z80, Intel's 8085A or its equivalent shall
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® stands for registered trade mark.
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S5U 13705 P00C0 00
Packing specification
Specification
Corresponding model number (13705: for S1D13705)
Product classification (S5U: development tool for semiconductor)
S1 D 13706 F 00A0 00
Devices
Configuration of product number
Packing specification
Specification
Package (B: CSP, F: QFP)
Corresponding model number
Model name (D: driver, digital products)
Product classification (S1: semiconductor)
Evaluation Board

CONTENTS
S1D13700 Technical Manual
EPSON
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Table of Contents
1 Overview...............................................................................................................................1
1.1 Features.......................................................................................................................................1
1.2 System Overview.........................................................................................................................2
1.3 List of Abbreviations.....................................................................................................................4
2 Pins .......................................................................................................................................5
2.1 Pin Connection.............................................................................................................................5
2.1.1 Pin Assignments.............................................................................................................5
2.1.2 Pin Description...............................................................................................................6
2.1.3 Package Dimensions......................................................................................................8
2.2 Pin Functions...............................................................................................................................9
2.2.1 Power Supply Pins .........................................................................................................9
2.2.2 Oscillator and Clock Input Pins ......................................................................................9
2.2.3 System Bus Connecting Pins.......................................................................................10
2.2.4 LCD Driver Control Pins...............................................................................................13
2.2.5 TEST Control Pins........................................................................................................13
3 Commands and Command Registers..............................................................................14
3.1 Types of Commands (when Indirectly Interfaced)......................................................................14
3.2 Command Register Map (when Directly Interfaced)..................................................................15
3.3 Command Description ...............................................................................................................17
3.3.1 Operation Control Commands......................................................................................17
3.3.2 Display Control Commands..........................................................................................25
3.3.3 Drawing Control Commands........................................................................................43
3.3.4 Memory Control Commands ........................................................................................44
4 Function Description.........................................................................................................45
4.1 Display Functions.......................................................................................................................45
4.1.1 Screen Management....................................................................................................45
4.1.2 Character Generator (CG)............................................................................................47
4.1.3 Screen Configuration....................................................................................................50
4.1.4 Cursor...........................................................................................................................61
4.1.5 Relationship between Display Memory and Screens...................................................62
4.1.6 Determining Various Parameters..................................................................................64
4.1.7 Scrolling........................................................................................................................65
4.1.8 Attribute Display using the Layered Function...............................................................68
4.2 Oscillator Circuit.........................................................................................................................70
4.3 Example of Initial Settings..........................................................................................................71
4.4 Character Codes and Character Fonts......................................................................................81
4.4.1 Character Fonts (Internal CG)......................................................................................81
4.4.2 Character Codes..........................................................................................................82
5 Specifications.....................................................................................................................83
5.1 Absolute Maximum Ratings.......................................................................................................83
5.2 Recommended Operating Conditions........................................................................................83
5.3 Electrical Characteristics ...........................................................................................................84
5.4 Timing Characteristics ...............................................................................................................86
5.4.1 System Bus (Generic Bus/80-series MPU)..................................................................86
5.4.2 System Bus Read/write characteristics II (MC68K-series MPU)..................................89
5.4.3 External Clock Input Characteristics ............................................................................92
5.4.4 LCD Control SignalTiming Characteristics..................................................................93
6 MPU Interface.....................................................................................................................95
6.1 Connection to the System Bus...................................................................................................95
6.1.1 80-series MPU..............................................................................................................95
6.1.2 68-series MPU..............................................................................................................95
6.2 Interfaces with the MPU (Reference).........................................................................................96

CONTENTS
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EPSON
S1D13700 Technical Manual
Table of Figures
Figure 1-1 Block diagram of the S1D13700 ............................................................................................ 2
Figure 3-1 Combination of IV and HDOT SCR...................................................................................... 20
Figure 3-2 Typical relationship between FX/FY and display addresses................................................ 21
Figure 3-3 Example of screen compositions ......................................................................................... 37
Figure 3-4 Prioritized overlay ................................................................................................................ 38
Figure 4-1 Character display ([FX] ≤ 8 dots) ......................................................................................... 45
Figure 4-2 Example of character generator definition ........................................................................... 45
Figure 4-3 Example of character configuration consisting of two or more memory addresses
(when [FX] = 9) ................................................................................................................... 46
Figure 4-4 Relationship between virtual and physical screens ............................................................. 50
Figure 4-5 Basic read cycle of display memory..................................................................................... 60
Figure 4-6 Relationship between TC/R and C/R................................................................................... 60
Figure 4-7 Relationship between display memory and screens............................................................ 62
Figure 4-8 Window and display memory settings.................................................................................. 63
Figure 4-9 Example of display memory mapping.................................................................................. 63
Figure 4-10 Example of using HDOT SCR ([FX] = 8).............................................................................. 67
List ofTables
Table 3-1 W/S Related Registers ......................................................................................................... 20
Table 4-1 Row Select Addresses ......................................................................................................... 48
Table 4-2 Example of Parameters for the LCD Unit ............................................................................. 64
Table 4-3 Character Codes .................................................................................................................. 82

1: OVERVIEW
S1D13700 Technical Manual
EPSON
1
1O
VERVIEW
The S1D13700 Controller displays text and graphics on a midsize, dot-matrix liquid crystal display
(LCD). A very flexible, low-power display system can be configured using the S1D13700 in
combination with various LCD modules. The character code or bitmap display data from the
microprocessor is temporarily stored in frame buffer memory, then periodically read out and
converted into LCD module signals for output to the LCD. Its abundant command functions make
it possible to overlay the text and graphic screens, scroll the screen in any direction (except in
grayscale mode), and split the screen for multi-window display, as well as display pictures in
grayscale mode. Moreover, the embedded-type 32-KB SRAM display buffer, built-in LCD module
control circuit, and high-speed character generator allow you to build an LCD control block with
only a few external circuits.
1.1 Features
● Number of display dots:...........................Text display mode
80 columns x 30 rows (monochrome, 1 bpp)
40 columns x 30 rows (4 gray shades, 2 bpp)
30 columns x 20 rows (16 gray shades, 4 bpp) +
graphic screen overlay
Graphic display mode
640 dots x 240 dots (monochrome, 1 bpp)
320 dots x 240 dots (4 gray shades, 2 bpp)
240 dots x 160 dots (16 gray shades, 4 bpp) x three-
screen overlay
● Three display modes: ..............................Text display mode, graphic display mode, and text/
graphic overlay mode (Layered display functions)
● Grayscale display function: ....................1 bpp, 2 bpp, or 4 bpp selectable
● Flexible scroll function: ..........................The text/graphics display screen can be easily moved
and smoothly scrolled horizontally.
● Frame buffer: ..........................................Up to 32 KB of SRAM, virtual screen configuration
● Internal character generator: ...................160 characters (Internal mask ROM dots 5 x 7 dots) +
64 characters (internal CGRAM 8 dots x 16 dots) or
256 characters (internal CGRAM 8 dots x 16 dots)
● Drive duty cycle: .....................................Can be set without any required increments from 1/2
up to 1/256 duty cycles.
● MPU interface .........................................Generic, 6800 series or M68K series
Direct access or indirect access selectable
● Power supply voltage ..............................5 V/3.3 V (dual power supplies) with MPU interface
and LCD interface pins independently selectable or
3.3 V (single power supply)
● Package: ..................................................64-pin QFP13 (Pd-free)

1: OVERVIEW
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EPSON
S1D13700 Technical Manual
1.2 System Overview
Positioned midway between the MPU and LCD panel, the S1D13700 enables the sending and
receiving of control commands and data, and access of registers by the MPU for display, thus
making it possible to control up to 32 Kbytes of internal display memory (VRAM).
Moreover, because the S1D13700 has a built-in a control circuit for LCD units, it is possible to
take full advantage of the features of midsize, dot-matrix liquid crystal display units without using
any external circuit.
Figure 1-1 Block diagram of the S1D13700
The S1D13700 divides the display memory space into the four areas shown below. When this
configuration is combined with the layered (overlaid) display and flexible scroll functions of the
S1D13700, it is possible to greatly reduce the MPU load when inverting or underlining text,
displaying graphs with text, or creating simple animation.
The S1D13700 uses the display memory space by dividing it into the four areas shown below to
realize the layered display functions using only a single controller.
Microprocessor Interface
Display Address
Generator
Dot Clock
Generator
Cursor Address
Controller Layered
Controller
Layered
Video RAM
Arbitrate
Character
Generator RAM Character
Generator ROM LCD Controller
LCD
EPDAT# to FFDAT0 FESHIFT XECL YSCL FPLINE EPFLAME MOD YDIS
AB0 to AB15 DB0 to DB7 CS# RD# WR# AS# WAIT# RESET#
CLK1 XCO1 XCD1
CNF0 to CFN4 TSTEN
Video RAM
GrayScale
FRM Controller Dot Counter Internal Clock
Oscillator

1: OVERVIEW
S1D13700 Technical Manual
EPSON
3
Example of display memory mapping by the S1D13700
(1)Character code table
• A memory area to store character code when displaying text
• 1 character = 8 bits
• Variable table mapping (by altering the scroll start address)
(2)Graphic data table
• A memory area to store bitmap data
• 1 word = 8 bits
• Variable table mapping
(3)CG RAM table (for external characters)
• A character generator whose character patterns can be altered by the MPU as desired
• Maximum 8 x 16 bits (16 bytes per character)
• Maximum 64 discrete characters, or 256 characters when not using CGROM
• Internal CG RAM used
• Variable table mapping
(4)CG ROM table
• Maximum 5 x 7 bits
• Maximum 160 characters
• Mapped to addresses 8030h–85AFh. Data cannot be read out by the MPU.
To make the most of the above-mentioned functions of the S1D13700, a high-speed interfacing
method is used to enable pipelined command processing between the MPU and S1D13700. Most
commands of the S1D13700 are processed so that the controller completes the processing of any
input command before the next command is issued from the MPU. Therefore, the MPU does not
need to frequently check the status of the S1D13700, and is not kept waiting by the S1D13700.
Thus, the high-speed interfacing method adopted for the S1D13700 helps minimize possible
reduction in the MPU’s processing capability.
Moreover, the MPU can access the above display space at any time irrespective of display mode
(except in sleep mode).

1: OVERVIEW
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S1D13700 Technical Manual
1.3 List of Abbreviations
Abbreviation Meaning
•AB
............................ Address
•AP
............................ Address pitch
•C
.............................. Text display mode (Denotes a command in command code descriptions.)
•CD
............................ Cursor movement direction
•CG
............................ Character generator
• CGRAM ADR
........... Character generator memory offset address
•CM
........................... Cursor shape
• C/R
........................... Number of characters per line
• CRX
......................... Cursor size in the X direction
•CRY
.......................... Cursor size in theY direction
• CSRDIR
.................... Direction of cursor movement
• CSRFORM
................ Cursor shape
• CSRR
........................ Cursor address read
• CSRW
....................... Cursor address write
•DM
........................... Display mode
•FC
............................ Flashing cursor
•f
FR
............................ Frame frequency
•f
OSC
.......................... Oscillation frequency
•FP
............................. Layer flashing
•FY
............................ Character field in theY direction
•G
.............................. Graphic display mode
• GLC
.......................... Graphic liquid crystal unit controller
• HDOT SCR
............... Smooth scrolling in horizontal direction
•IV
............................. Inverse
•L
............................... Layer
• L/F
............................ Number of lines per screen
• MREAD
.................... Display memory readout
•MX
........................... Screen composition method
• MWRITE
.................. Display memory write
•OV
............................ Screen overlay
• OVRAY
..................... Screen overlay
•P
............................... Parameter
•R
.............................. Row
• RAM
......................... Random access memory
•ROM
......................... Read-only memory
• SAD
.......................... Display start address
•SL
............................. Number of scanning lines
• TC/R
......................... Total number of characters per line
• VRAM
...................... Display memory
• MOD(WF)
................. AC drive waveform
• W/S
.......................... Double common/single common
• XDr
.......................... X direction driver
• YDr
.......................... Y direction driver

2: PINS
S1D13700 Technical Manual
EPSON
5
2P
INS
2.1 Pin Connection
2.1.1 Pin Assignments
S1D13700F00A
Index
16117
32
48
64
49 NIOVDD
YDIS
FPFRAME
YSCL
VSS
MOD
FPLI NE
COREVDD
XECL
FPSHI FT
NIOVDD
FPDAT0
FPDAT1
FPDAT2
FPDAT3
VSS
DB3
DB2
DB1
DB0
VSS
WAI T#
HIOVDD1
CNF0
CNF1
CNF2
CNF3
CNF4
AS#
AB15
AB14
AB13
VSS
AB12
AB11
AB10
AB9 AB8
HIOVDD
AB7
AB6 AB5 AB4
COREVDD
AB3 AB2 AB1 AB0
HIOVDD DB4 DB5 DB6 DB7 CS# WR# RD# COREVDD CLKI TESTEN SCANEN RESET# XCG1 XCD1 VSS
33

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EPSON
S1D13700 Technical Manual
2.1.2 Pin Description
Key :
I =
Input
O = Output
IO =
Input/output
P =
Power supply
HIBC =
CMOS input
HIBH =
CMOS Schmitt input
HIBCD1 =
CMOS input with pulldown resistor (60 ohms typ. at 5.0 V)
HOB2T =
Normal buffer (8 mA/-8 mA at 5 V)
HBC2T =
LVTTL I/O buffer (6 mA/-6 mA at 3.3 V)
HTB2T =
Tri-state output (6 mA/-6 mA at 3.3 V)
HLIN = Transparent input
HLOT = Transparent output
ITST1 =
Test mode control input with pulldown resistor (50 ohms typ. at 3.3 V)
Pin Name Pin No. I/O
Type I/O Voltage I/O Cell RESET# State Description
HIOVDD(V
DD
)7 • 48 • 55 P HIOVDD — — Power supply for host interface
NIOVDD(V
DD
)22 • 32 P NIOVDD — — Power supply for LCD interface
COREVDD(V
DD
)12 • 25 • 40 P COREVDD — — Power supply for core logic
V
SS
1 • 17 • 28 • 33 • 53 P V
SS
— — Ground
CLKI 39 I HIOVDD HIBH — Externally sourced system clock
XCG1(XG) 35 I HIOVDD HLOT — Gate input for oscillator
XCD1(XD) 34 O HIOVDD HLIN — Drain output for oscillator
CNF0 – CNF4
(SEL0 – SEL4) 56-60 I HIOVDD HIBH 0 Input pin for S1D13700 settings
DB0 – DB7
(D0 – D7) 44-47 • 49-52 IO HIOVDD HBC2T Hi-Z Data bus for MPU interface
AB0 – AB15
(A0 – A15) 2-6 • 8-11 • 13-16 I HIOVDD HIBC 0 Address bus for MPU interface
RD# 41 I HIOVDD HIBH 1 Read strobe for MPU interface
WR# 42 I HIOVDD HIBH 1 Write strobe for MPU interface
CS# 43 I HIOVDD HIBH 1 Chip select for MPU interface
WAIT# 54 O HIOVDD HOB2T Hi-Z Wait output for MPU interface
AS# 61 I HIOVDD HIBC 1 Address strobe for MPU
interface
FPDAT0 –
FPDAT3(XD0 – XD3) 18-21 O NIOVDD HOB2T X Data bus for X driver
FPSHIFT(XSCL) 23 O NIOVDD HOB2T X Shift clock for X driver
XECL 24 O NIOVDD HOB2T X X driver enable chain clock
FPLINE(LP) 26 O NIOVDD HOB2T X Latch pulse
MOD(WF) 27 O NIOVDD HOB2T X Frame signal
YSCL 29 O NIOVDD HOB2T X Scan shift clock
FPFRAME (YD) 30 O NIOVDD HOB2T X Scan start pulse

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S1D13700
Technical Manual EPSON 7
Note: The corresponding pin names of the earlier LCD controller (i.e., S1D13305) are enclosed in
parentheses.
YDIS 31 O NIOVDD HOB2T L LCD power-down output
RESET# (RES) 36 I HIOVDD HIBH 0 Reset input
TESTEN 38 I HIOVDD ITST1 0 Test mode setup input
SCANEN 37 I HIOVDD HIBCD1 0 Test mode setup input
Pin Name Pin No. I/O
Type I/O Voltage I/O Cell RESET# State Description

2: PINS
8EPSON S1D13700 Technical Manual
2.1.3 Package Dimensions
HD
ED
E
ICL
L2L1
R1
RD
L
Amax
A1 A2
D
48 PIN
49 PIN
64 PIN
1 PIN 16 PIN
17 PIN
32 PIN
33 PIN
e
Symbol Dimension in Milimeters
Min. Nom. Max.
E 10.1 10.2 10.3
D 10.1 10.2 10.3
Amax 1.2
AL 0.1
AP 0.9 1 1.1
e 0.5
ICL 0.17 0.2 0.27
CL 0.125 0.15 0.2
É∆0° 10°
L 0.3 0.5 0.7
L1 1
L2 0.5
HE 11.6 12 12.4
HD 11.6 12 12.4
É∆2 15°
É∆3 15°
R 0.1
R1 0.1
*
*
*
*
E,D Excluding the tie bar cutting stub.
ICL Lead width of basemetal.
CL Lead thickness of basemetal.
1 = 1mm
*

2: PINS
S1D13700 Technical Manual EPSON 9
2.2 Pin Functions
2.2.1 Power Supply Pins
Note 1: Because the spike power supply current in the S1D13700 could reach levels that are several
tens higher than the average amount of dynamically consumed current, measures must be
taken to minimize the power supply impedance of the S1D13700. For example, use thick
power supply wiring from the power supply to the S1D13700 or insert a capacitor of 0.47 mF or
more (with good frequency characteristics) between VDD and VSS close to the S1D13700.
These measures will help to reduce power supply impedance.
2.2.2 Oscillator and Clock Input Pins
Note 2: Because the external clock fed in from the CLKI pin is needed to internally generate the
fundamental timing in the S1D13700, the oscillation characteristic requirements given in
Section 5.4.3 “External Clock Input Characteristics”on page 92 must be met.
Pin Name Function
HIOVDD Power supply for host interface I/O drive. Connect a 5 V or 3.3V power supply to this pin. (Shared
with MPU power supply pin,VCC) Note 1
NIOVDD Power supply for LCD I/O drive other than host of interface I/O. Connect a 5V or 3.3 V power supply
to this pin. Note 1
COREVDD Power supply for internal logic. Connect a 3.3 V power supply to this pin. Note 1
VSS Connects to 0 V earth ground (GND).
CLKI Generally used as the input clock source for the bus and memory clocks.
XCG1
XCD1
These pins are used to connect a crystal resonator for the internal clock-generating oscillator. For
details, see Section 4.2 “Oscillator Circuit” on page 70. To use the external clock (fed in from the
CLKI pin), fix XCG1 for input with a pullup resistor and leave XCD1 open. Note 2
CNF0
CNF1
Input, active low
Set the frequency divide ratio of the display clock (pixel clock) relative to CLKI or an internally gener-
ated system clock.
CNF3 CNF2 Clock Retio
0 0 1/4
0 1 1/8
1 0 1/16
1 1 Not USE

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10 EPSON S1D13700 Technical Manual
2.2.3 System Bus Connecting Pins
Note 3: Normally, CNF2 and CNF3 should be corrected directly to power supply VDD or VSS to prevent
the mixture of noise. Should noise be mixed in, insert a capacitor between the CNF2 and
CNF3 lines and VSS, as close to the IC pins as possible.This will help to effectively eliminate
noise.
DB0 – DB7 Tristate input/output, active high
These pins comprise an 8-bit bidirectional data bus, which is connected to the 8-bit or 16-bit MPU data bus.
CNF2
CNF3
Input, active high
The S1D13700 allows the MPU interface format to be changed depending on how CNF2 and CNF3 are set,
so that it can be connected directly to the 80-series MPU (e.g., Z80®or GenericBus), 68-series MPU (6809
or 6802), or the MC68K-series MPU (68000) bus.
AB15 – AB1
AB0
Input, active high
Normally, the MPU address bus is connected to these pins. The data bus signal is discriminated by a combi-
nation of RD# and WR# signals, or R/W#, E, and LDS signals, as listed in the table below.
CMF4
Input: CNF4 = 0 selects direct access; CNF4 = 1 selects indirect access.
<Direct access for the 80-series interface>
<Indirect access for the 80-series interface>
CNF3 CNF2 Mode AB15
– AB1 AB0 RD# WR# CS# DB7 – DB0 WAIT# AS#
0 0 80 series ↑↑↑↑↑↑ ↑–
01 * ****** **
1 0 6800 ↑↑E R/W# ↑↑ ––
1 1 MC68K ↑↑LDS# R/W# ↑↑DTACK# ↑
Settings marked with * are inhibited. Note 3
CNF4 AB15
– AB1 AB0 RD# WR# Function
0 0or1 0or1 0 1 Read from command/parameter
registers
0 0or1 0or1 1 0 Write to command/parameter registers
*AB15–AB0 are used as register addresses.
CNF4 AB15
– AB1 AB0 RD# WR# Function
1–001 –
1–101
Data (display data and cursor address)
read
1–010
Data (display data and parameter)
write
1–110Command write (code only)

2: PINS
S1D13700 Technical Manual EPSON 11
CMF4
Input: CNF4 = 0 selects direct access; CNF4 = 1 selects indirect access.
<Direct access for the 68-series interface>
<Indirect access for the 68-series interface>
RD# (E)
• When the 80-series MPU is connected
Input, active low
This is the strobe signal used by the MPU as it reads data or status flags from the S1D13700. The data bus
of the S1D13700 is in output mode while this signal remains low.
• When the 68-series MPU is connected
Input, active high
This is an enable clock input pin of the 68-series MPU.
• When the MC68K-series MPU is connected
Input, active low
Normally, this is an LDS# input pin of the MC68K-series MPU.
WR# (R/W#)
• When the 80-series MPU is connected
Input, active low
This is the strobe signal used by the 80-series MPU as it writes data or parameters to the S1D13700. The
S1D13700 latches the data bus signal at the rising edge of WR#.
• When the 68-series MPU is connected
Input
This is a R/W# control signal input pin of the 68-series MPU.
R/W# = HIGH : READ
R/W# = LOW : WRITE
• When the MC68K-series MPU is connected
Input
This is a R/W# control signal input pin of the MC68K-series MPU.
R/W# = HIGH : READ
R/W# = LOW : WRITE
CS# Input, active low This chip select signal is used by the MPU to activate the S1D13700 before accessing it, and is normally
derived by decoding the address bus signal.
CNF4 AB15
– AB1 AB0 WR# (R/W#) RD# (E) Function
0 0or1 0or1 1 1 Read from command/parameter
registers
0 0or1 0or1 0 1 Write to command/parameter registers
*A15–A0 are used as register addresses.
CNF4 AB15
– AB1 AB0 WR# (R/W#) RD# (E) Function
1–011 –
1–111
Data (display data and cursor address)
read
1–001
Data (display data and parameter)
write
1–101Command write (code only)

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12 EPSON S1D13700 Technical Manual
Note 4: Although this pin is a Schmitt trigger input to prevent the S1D13700 from being inavertently
reset by noise, care must be taken when intentionally lowering the power supply voltage.
WAIT#
This signal forcibly inserts a wait state into the system during data transfer. When this signal is deasserted,
data transfer is completed. After data transfer is complete, this signal is left free (placed in high-impedance
state).
• When the 80-series MPU is connected
Tri-state output, active low (wait state when asserted low)
Connect this pin to WAIT# of the 80-series MPU.
• When the 68-series MPU is connected
Unused. Therefore, leave this pin open.
• When the MC68K-series MPU is connected
Tri-state output, active low (no wait state when asserted low)
This pin serves as the DTACK# pin of the MC68K-series MPU.
AS#
• When the 80-series MPU is connected
Unused. Therefore, fix this pin low.
• When the 68-series MPU is connected
Unused. Therefore, fix this pin low.
• When the MC68K-series MPU is connected
Input, active low
Connect this pin to the address strobe AS# pin of the MC68K-series MPU.
RESET# Input, active low The RESET# input is used to initially reset the S1D13700 in hardware. Note 4

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S1D13700 Technical Manual EPSON 13
2.2.4 LCD Driver Control Pins
The S1D13700 can directly control both the X and Y drivers based on an enable chain, which is a method of
effectively reducing the amount of current consumption needed to drive dot-matrix liquid crystal display
elements.
Note 5: TheYDIS signal goes low at a time equivalent to one to two frames after the sleep command is
written. When the YDIS signal goes low, all Y driver outputs are forcibly brought to an
intermediate level (unselected), thus causing display to turn off. Therefore, to power off the
LCD unit, the liquid crystal drive power supply (with relatively large steady-state current) must
be turned off at the same time display is turned off by using theYDIS signal.
2.2.5 TEST Control Pins
FPDAT0 –
FPDAT3 Output, active high This 4-bit dot data bus for the X driver (column driver) is connected to the data input pins of the X driver.
FPSHIFT
Output, falling edge triggered
This signal causes the dot data bus signals (FPDAT0–FPDAT3) to be stored in the X driver at the signal’s
falling edge, and thus functions as a shift clock for the internal shift register of the X driver.
To reduce power consumption, this clock is turned off until the MPU starts sending data for the next display
line after outputting the LP signal. (For details, see Section 5.4.4 “LCD Control Signal Timing
Characteristics” on page 93.)
XECL Output, falling edge triggered XECL is a dedicated clock signal for the X drivers cascaded by an enable chain. It causes the enable signal
to be successively passed to the next X driver every 16 XSCL periods.
FPLINE Output, falling edge triggered For the liquid crystal display elements to be successively driven, the X driver contains a circuit to latch each
output bit of the internal shift register at the falling edge of LP. This signal is output for every display line.
MOD
Output
This signal provides a one-frame interval for the X and Y drivers to determine the AC drive waveform for
the LCD panel. Two types of cyclic signals are output depending on how the System Set command
parameters are set.
YSCL Output, active high, rising edge triggered This signal is a clock for the Y driver, and is equivalent to XSCL for the X driver. The Y data signal (YD) is
stored in the Y driver at the beginning of a frame, and YSCL is used as an internal shift clock.
FPFRAME
Output, active high
YD is data for the Y driver, and is a cyclic signal output at the first display line interval of a frame. The
electrodes on the common side of liquid crystal display elements are sequentially scanned as the YD signal
is sequentially shifted inside the Y driver synchronously with the YSCL signal.
YDIS Output, active high
This signal is used to power down the LCD unit and is held high during the display period. Note 5
TESTEN Input, active high
Test-enable input used only for production testing (with type-1 pulldown resistor, 50 ohms typ. at 3.3 V).
SCANEN Input, active high
Test-enable input used only for production testing (with type-1 pulldown resistor, 50 ohms typ. at 3.3 V).

3: COMMANDS AND COMMAND REGISTERS
14 EPSON S1D13700 Technical Manual
3COMMANDS AND COMMAND REGISTERS
3.1 Types of Commands (when Indirectly Interfaced)
When indirect mode is selected for the system interface, use commands to set up the display.
The table below lists the types of commands, including the code of each command.
Note 1: As a rule, each command is executed every time a parameter for the command is input to the
S1D13700, and completed before the next parameter (P) or command (C) is input.Therefore,
the MPU can stop sending parameters in the middle and send the next command. In this case,
the parameters that have already been sent are effective and other parameters not input to the
S1D13700 retain their original values. However, two-byte parameters are handled as
described below.
Note 1:
1. CSRW and CSRR commands: The parameter is executed one byte at a time. Therefore, the MPU
can only alter or check the low-order byte.
2. Commands other than CSRW and CSRR: The parameter is not executed until its second byte is
input. SYSTEM SET
SCROLL
CGRAM ADR
3. Two-byte parameters consist of two bytes of data (as in the case of APL and APH).
4. Because the value of each register after power-on is indeterminate, make sure all command
parameters are set.
Purpose Command Code Command
description
Parameters
following the
command Remarks
WR# RD# AB0 DB BIN
7 6 5 4 3 2 1 0 DB HEX No. of
parameters See
pages
Operation
control SYSTM SET 1 0 1 0 1 0 0 0 0 0 0 40 Sets initial operation
and window size. 819
SLEEP IN 1 0 1 0 1 0 1 0 0 1 1 53 Sleep operation. 0 27 Note 1
Display
control
DISPON/OFF 1 0 1 0 1 0 1 1 0 0 D 58 •
59
Instructs to turn
display on or off and
make the screen flash
on and off.
1 28 Note 1
SCROLL 1 0 1 0 1 0 0 0 1 0 0 44 Sets the display start address and display
area. 10 29
CSRFORM 1 0 1 0 1 0 1 1 1 0 1 5D Sets the cursor shape,
etc. 237
CSRDIR 1 0 1
CD CD
01001110 4C – 4F Sets the direction of cursor movement. 038
OVLAY 1 0 1 0 1 0 1 1 0 1 1 5B Instructs screen
overlay mode. 139
CGRAM ADR 1 0 1 0 1 0 1 1 1 0 0 5C Sets the start address
of CG RAM. 243
HDOT SCR 1 0 1 0 1 0 1 1 0 1 0 5A Sets the horizontal direction dot unit and
scroll position. 144
GRAY SCALE 1 0 1 0 1 1 0 0 0 0 0 60 Sets grayscale mode. 0 45
Drawing
control
CSRW 1 0 1 0 1 0 0 0 1 1 0 46 Sets the cursor
address. 2 45 Note 1
CSRR 1 0 1 0 1 0 0 0 1 1 1 47 Instructs to read the
cursor address. 2 46 Note 1
Memory
control
MWRITE 1 0 1 0 1 0 0 0 0 1 0 42 Instructs to write to
display memory. — 47 Note 1
MREAD 1 0 1 0 1 0 0 0 0 1 1 43 Instructs to read
display memory data. —47

3: COMMANDS AND COMMAND REGISTERS
S1D13700 Technical Manual EPSON 15
3.2 Command Register Map (when Directly Interfaced)
When direct mode is selected for the system interface, directly access the registers to set up the display.
Address Hard
Reset Register name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0 x 8000 0 x 10 R_P1_
SystemSet 0 0 IV 1 WSM2M1M0
0 x 8001 0 x 00 R_P2_
SystemSet WF 0 0 0 FX
0 x 8002 0 x 00 R_P3_
SystemSet 0000 FY
0 x 8003 0 x 00 R_P4_
SystemSet CR
0 x 8004 0 x 00 R_P5_
SystemSet TCR
0 x 8005 0 x 00 R_P6_
SystemSet LF
0 x 8006 0 x 00 R_P7_
SystemSet APL
0 x 8007 0 x 00 R_P8_
SystemSet APH
0 x 8008 *20 x 01 R_SleepIn 0000000
Sleep
In
0 x 8009 0 x 00 r_DispOnOff 0000000
Disp
On
0 x 800A 0 x 00 r_P1_
DispOnOff FP5 FP4 FP3 FP2 FP1 FP0 FC1 FC0
0 x 800B 0 x 00 r_P1_Scroll SAD1L
A7 SAD1L A6 SAD1L A5 SAD1L A4 SAD1L A3 SAD1L A2 SAD1L A1 SAD1L A0
0 x 800C *10 x 00 r_P2_Scroll SAD1H
A15 SAD1H A14 SAD1H A13 SAD1H A12 SAD1H A11 SAD1H A10 SAD1H A9 SAD1H A8
0 x 800D 0 x 00 r_P3_Scroll SL1L7 SL1L6 SL1L5 SL1L4 SL1L3 SL1L2 SL1L1 SL1L0
0 x 800E 0 x 00 r_P4_Scroll SAD2L
A7 SAD2L A6 SAD2L A5 SAD2L A4 SAD2L A3 SAD2L A2 SAD2L A1 SAD2L A0
0 x 800F *10 x 00 r_P5_Scroll SAD2H
A15 SAD2H A14 SAD2H A13 SAD2H A12 SAD2H A11 SAD2H A10 SAD2H A9 SAD2H A8
0 x 8010 0 x 00 r_P6_Scroll SL2L7 SL2L6 SL2L5 SL2L4 SL2L3 SL2L2 SL2L1 SL2L0
0 x 8011 0 x 00 r_P7_Scroll SAD3L
A7 SAD3L A6 SAD3L A5 SAD3L A4 SAD3L A3 SAD3L A2 SAD3L A1 SAD3L A0
0 x 8012 *10 x 00 r_P8_Scroll SAD3H
A15 SAD3H A14 SAD3H A13 SAD3H A12 SAD3H A11 SAD3H A10 SAD3H A9 SAD3H A8
0 x 8013 0 x 00 r_P9_Scroll SAD4L
A7 SAD4L A6 SAD4L A5 SAD4L A4 SAD4L A3 SAD4L A2 SAD4L A1 SAD4L A0
0 x 8014 *10 x 00 r_P10_Scroll SAD4H
A15 SAD4H A14 SAD4H A13 SAD4H A12 SAD4H A11 SAD4H A10 SAD4H A9 SAD4H A8
0 x 8015 0 x 00 r_P1_
CsrForm 0000CRX3 CRX2 CRX1 CRX0
0 x 8016 0 x 00 r_P2_
CsrForm CM 0 0 0 CRY3 CRY2 CRY1 CRY0
0 x 8017 0 x 00 r_P1_CsrDir 000000CD1CD2
0 x 8018 0 x 00 r_P1_OvLay 0 0 0 OV DM2 DM1 MX1 MX0