Epson SED1352 User manual

SED1352 Graphics LCD Controller
SED1352
TECHNICAL MANUAL
Document Number: X16B-Q-001-06
Copyright © 1997, 1998 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your ownuse in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

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Vancouver Design Center
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Epson Research and Development Page iii
Vancouver Design Center
Issue Date: 98/10/08 SED1352
CUSTOMER SUPPORT INFORMATION
Comprehensive Support Tools
Seiko Epson Corp. provides to the system designer and computer OEM manufacturer a complete set ofresources and tools
forthe development of imbedded graphics systems.
Evaluation / Demonstration Board
•Assembled and fully tested graphics evaluation board with installation guide and schematics
•To borrow an evaluation board, please contact yourlocal Seiko Epson Corp. sales representative
Chip Documentation
•Technical manual includes Data Sheet, Application Notes, and Programmer’s Reference
Software
•OEM Utilities
•User Utilities
•Evaluation Software
•To obtain these programs, contact Application Engineering Support
Application Engineering Support
Engineering and Sales Support is provided by:
Japan
Seiko Epson Corporation
ElectronicDevices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: [phone]
Fax: [phone]
http://www.epson.co.jp
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: [phone]
Fax: [phone]
Taiwan, R.O.C.
Epson Taiwan Technology
& Trading Ltd.
10F, No.287
Nanking East Road
Sec. 3, Taipei,Taiwan,R.O.C.
Tel: [phone]
Fax: [phone]
Singapore
Epson Singapore Pte., Ltd.
No.1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: [phone]
Fax: [phone]
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: [phone]
Fax: [phone]
NorthAmerica
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134,USA
Tel: [phone]
Fax: [phone]
http://www.erd.epson.com

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Epson Research and Development Page v
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Issue Date: 98/10/08 SED1352
TABLE OF CONTENTS
INTRODUCTION
SED1352 Graphics LCD Controller Data Sheet
SPECIFICATION
SED1352 Hardware Functional Specification
PROGRAMMER’S REFERENCE
SED1352 Programming Notes and Examples
UTILITIES
1352SHOW.EXE Display Utility
VIRTUAL.EXE Display Utility
BIOS1352.COM Utility
1352GRAY.EXE Display Utility
1352PD.EXE Power Down Utility
1352READ.EXE Diagnostic Utility
EVALUATION
SDU1352B0C Rev 1.0 Evaluation Board User Manual
APPLICATION NOTES
Power Consumption
ISA Bus Interface Considerations
MC68340 Interface Considerations
LCD Panel Options / Memory Requirements

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GRAPHICS
SED1352
X16B-C-001-06 1
October 1998
SED1352 GRAPHICS LCD CONTROLLER
■DESCRIPTION
The SED1352 is a graphics display LCD controller capable of displaying a maximum of 16 levels of gray on single and dual
scan Liquid Crystal Displays. A 16x4 lookup table is provided to allow remapping of the 16 possible gray shades displayed on
the LCD panel. The SED1352 can interface to the MC68000 microprocessor and 8/16 bit MPUs with READY (WAIT#) signal
with minimum external “glue” logic. This chip can directly control up to 128 Kbytes of static SRAM.
Optimized for cost and power savings, the SED1352 can operate from 2.7 volts to 5.5 volts and up to 25MHz.
■FEATURES
•16-bit 16 MHz MC68000 MPU interface
•8/16-bit MPU interface controlled by a READY (or
WAIT#) signal
•option to use built-in index register or direct-mapping to
access one of fifteen internal registers
•2-terminal crystal input for internal or external
crystal oscillator
•8/16-bit SRAM interface configurations
•two software power-save modes
•low power consumption
•display modes:
2 bit/pixel, 4-level gray-scale display
4 bit/pixel, 16-level gray-scale display
•virtual display support
•display memory interface:
one 1 Mbit SRAM(64Kx16)
one or two 32Kbyte SRAM(s)
one or two 8Kbyte SRAM(s)
one 8Kbyte and one 32Kbyte SRAM
•LCD panel configurations:
single-panel, single-drive display
dual-panel, dual-drive display
•maximum number of vertical lines:
1,024 lines (single-panel, single-drive display)
2,048 lines (dual-panel, dual-drive display)
•split screen display support at single-panel mode
•package:
QFP5-100-S2 package (F0B)
or QFP15-100-STD package (F1B)
■SYSTEM BLOCK DIAGRAM
LCD PANEL
MPU SED1352
SRAM
CLOCK
80xx
Z80
68xxx
DATA
CONTROL
ADDRESS

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SED1352
X16B-C-001-06
2
■INTERFACE OPTIONS
Note: Example implementation, actual may vary.
Note: Example implementation, actual may vary.
SED1352
MEMCS#
IOCS#
MC68xxx
DTACK#
D0 to D15
A1 to A19 AB1 to AB19
DB0 to DB15
IOW#
IOR#
Decoder
AS#
R/W#
BHE#
UDS#
READY
A20 to A23
AB0
LDS#
Decoder
A16.. A14
A10 to A19
FC0 to FC1
Interface with 16-Bit MC68xxx MPU and 16Kbytes SRAM (2 of 8K x 8)
64 Kbit
VWE#
VD0-7
VCS0#
VCS1#
VA0-12
WE#
CS#
64 Kbit
WE#
CS#
VD8-15
MEMCS#
MEMW#
MEMR#
READY
DB0 to DB7
AB0 to AB15
IOCS#
IOW#
IOR#
RESET
SED1352
Z80
RESET#
D0 to D7
WAIT#
A0 to A15
WR#
RD#
Decoder
IORQ#
A10 to A15
Decoder
MREQ#
Interface with 8-Bit Z80 MPU and 16Kbytes SRAM (2 of 8K x 8)
64 Kbit
VWE#
VD0-7
VCS0#
VCS1#
VA0-12
WE#
CS#
64 Kbit
WE#
CS#
MI#

GRAPHICS
SED1352
X16B-C-001-06 3
Note: Example implementation, actual may vary.
Note: Example implementation, actual may vary.
8086
(Maximum mode)
CLK
READY
RESET#
RDY
MEMW#
MEMR#
READY
DB0 to DB15
AB0 to AB15
IOW#
IOR#
RESET
SED1352
8284A
D0 to D15
T
OE
CLK
S2#
S1#
S0#
DEN
MRDC#
AMWC#
IORC#
AIOWC#
DT/R
CLK
READY
RESET#
8288
AB16 to AB19
M/IO#
BHE#
A0 to A16
STB
Decoder
A16 to A19
S2#
S1#
S0#
ALE
BHE#
AD0 to AD15 A16 BHE#
MEMCS#
IOCS#
Interface with 16-Bit 8086 MPU and 64Kbytes SRAM (2 of 32K x 8)
256 Kbit
VWE#
VD0-7
VCS0#
VCS1#
VA0-14
WE#
CS#
256 Kbit
WE#
CS#
VD8-15
Interface with 8-Bit ISA Bus and 40Kbytes SRAM (1 of 8K x 8 and 1 of 32K x 8)
SED1352
MEMCS#
MEMW#
MEMR#
READY
8-Bit ISA Bus
SMEMW#
SMEMR#
IOCHRDY
REFRESH
SA0 to SA19
SD0 to SD7 DB0 to DB7
AB0 to AB19
Decoder
SA16.. SA13
IOCS#
IOW#
IOR#
RESET
RESET#
SA10 to SA15
AEN
IOW#
IOR#
Decoder
0WS#
optional
SA(1 or 4) to SA9
Decoder
64 Kbit
VWE#
VD0-7
VCS0#
VCS1#
VA0-14
WE#
CS#
256 Kbit
WE#
CS#

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SED1352
X16B-C-001-06
4
Note: Example implementation, actual may vary.
■SUPPORTED RESOLUTIONS
Display
RAM
Example Display Size SRAM
Type CPU Interface SRAM Interface
4 Grays 16 Grays
X Y X Y
8 Kbytes 256 x 128 128 x 128 1 of 8Kx8 8-bit 8-bit
16 Kbytes 320 x 200 200 x 160 2 of 8Kx8 8-bit 8-bit/16-bit
16-bit 16-bit
32 Kbytes 512 x 256 256 x 256 1 of 32Kx8 8-bit 8-bit
40 Kbytes 512 x 320 320 x 256 1 of 8Kx8 and
1 of 32Kx8 8-bit 8-bit
64 Kbytes 512 x 512 512 x 256 2 of 32Kx8 8-bit 8-bit/16-bit
16-bit 16-bit
128 Kbytes 1024 x 512 512 x 512 1 of 64Kx16 16-bit 16-bit
Interface with 16-Bit ISA Bus and 128Kbytes SRAM (1 of 128K x 8)
SED1352
MEMCS#
MEMW#
MEMR#
READY
16-bit ISA Bus
SMEMW#
SMEMR#
IOCHRDY
REFRESH
SA0 to SA19
SD0 to SD15 DB0 to DB15
AB0 to AB19
Decoder
IOCS#
IOW#
IOR#
RESET
RESET#
Decoder
SA10 to SA15
AEN
IOW#
IOR#
IOCS16#
SA(1 or 4) to SA9
BHE#
SBHE#
Decoder
MEMCS16#
LA17 to LA23
SA16.. SA14
Decoder
VWE#
VD0-7
VD8-15
VCS0#
VCS1#
VA0-15
1 Mbit
WE#
UB#
LB#
A0-15
I/O 1-8
I/O 9-16

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SED1352
X16B-C-001-06 5
■BLOCK DIAGRAM
Bus
Control Registers
Signal
Translation
Port
Memory
Data Bus
Timing Generator
Sequence
Address
CPU/CRT
SRAM Interface
Look-Up LCD
Decoder
Decoder
Conversion
Oscillator
Power Save
Selector
Display
Data
Formatter
Generator
Table
Controller
Panel
Interface
LCDENB
UD[3:0]
LD[3:0]
LP, YD,
WF,
OSC1
OSC2
VWE# VOE# VA[15:0] VSC0#, VSC1# VD[15:0]
IOR#, IOW#, IOCS#,
MEMCS#, MEMR#,
MEMW#, BHE#,
AB[19:0]
READY
DB[15:0] XSCL

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SED1352
X16B-C-001-066
■FUNCTIONAL BLOCK DESCRIPTIONS
Bus Signal Translation
According to configuration setting VD2, Bus Signal Trans-
lation translates MC68000 type CPU signals, or READY
type MPU signals, to internal bus interface signals.
Control Registers
The fifteen internal Control and Configuration Registers
are accessed by direct-mapping or by using the built-in
internal index register.
Sequence Controller
The Sequence Controller generates horizontal and vertical
display timings according to the configuration registers
settings.
LCD Panel Interface
The LCD Interface performs frame rate modulation for
passive monochrome LCD panels.
Look-Up Table
The Look-Up Table contains sixteen 4-bit wide palettes
that can be configured as one 16x4 palette or four 4x4
palettes used for the re-mapping of gray-scale outputs.
Port Decoder
According to configuration settings VD1, VD12 - VD4,
IOCS# and address lines AB9-1, the Port Decoder
validates a given I/O cycle.
Memory Decoder
According to configuration settings VD15 - VD13,
MEMCS# and address lines AB19-17, the Memory
Decoder validates a given memory cycle.
Data Bus Conversion
According to configuration setting VD0, the Data Bus
Conversion maps the external data bus, either 8-bit or 16-
bit, into the internal odd and even data bus.
Address Generator
The Address Generator generates display refresh addresses
used to access display memory.
CPU / CRT Selector
The CPU / CRT Selector accesses the display memory
from the CPU or the display refresh circuitry.
Display Data Formatter
The Display Data Formatter reads the display data from the
display memory and outputs the correct format for all
supported LCD panel types and gray-scale selections.
Clock Inputs / Timing
Clock Inputs / Timing generates the internal master clock
according to the gray-level selected and display memory
interface.The master clock (MCLK) can be:
MCLK = input clock
MCLK = 1/2 input clock
MCLK = 1/4 input clock
Pixel clock = input clock.
SRAM Interface
The SRAM Interface generates the necessary signals to
interface to the Display memory (SRAM).

GRAPHICS
SED1352
X16B-C-001-06 7
■DC SPECIFICATIONS
Absolute Maximum Ratings
Recommended Operating Conditions
Input Specifications
Symbol Parameter Rating Units
VDD Supply Voltage VSS - 0.3 to + 6.5 V
VIN Input Voltage VSS - 0.3 to VDD + 0.3 V
VOUT Output Voltage VSS - 0.3 to VDD + 0.3 V
TSTG Storage Temperature -65 to 150 °C
TSOL Solder Temperature/Time 260 for 10 sec. max at lead °C
Symbol Parameter Condition Min Typ Max Units
VDD Supply Voltage VSS = 0V 2.7 3.0/3.3/5.0 5.5 V
VIN Input Voltage VSS -- VDD V
IOPR Operating Current fOSC = 6 MHz,
16 grays 3.0/3.5/7.0 mA
TOPR Operating Temperature -40 25 85 °C
PTYP Typical Active Power Consumption fOSC = 6 MHz,
16 grays 9.0/11.55/ 35.0 mW
Symbol Parameter Condition Min Typ Max Units
VIL Low Level Input Voltage VDD = 4.5V
VDD = 3.0V
VDD = 2.7V
0.8
0.6
0.5 V
VIH High Level Input Voltage VDD = 5.5V
VDD = 3.6V
VDD = 3.3V
2.0
2.5
2.3 V
VT+ Positive-going Threshold VDD = 5.0
VDD = 3.3
VDD = 3.0
2.4
2.4
2.3 V
VT- Negative-going Threshold VDD = 5.0
VDD = 3.3
VDD = 3.0
0.6
0.6
0.5 V
VHHysteresis Voltage VDD = 5.0
VDD = 3.3
VDD = 3.0
0.1
0.1
0.1 V
IIZ Input Leakage Current -- -1 1 µA

GRAPHICS
SED1352
X16B-C-001-06
8
Output Specifications
Symbol Parameter Condition Min Typ Max Units
VOL (5.0V)
Low Level Output Voltage
Type 2 - TS2, CO2, TS2D2
Type 3 - TS3
Type 4 - TS4, CO4
IOL = 6 mA
IOL = 12 mA
IOL = 24 mA
VSS + 0.4 V
VOL (3.3V)
Low Level Output Voltage
Type 2 - TS2, CO2, TS2D2
Type 3 - TS3
Type 4 - TS4, CO4
IOL = 3mA
IOL = 6mA
IOL = 12mA
VSS + 0.3 V
VOL (3.0V)
Low Level Output Voltage
Type 2 - TS2, CO2, TS2D2
Type 3 - TS3
Type 4 - TS4, CO4
IOL = 3mA
IOL = 5 mA
IOL = 10mA
VSS + 0.3 V
VOH (5.0V)
High Level Output Voltage
Type 2 - TS2, CO2, TS2D2
Type 3 - TS3
Type 4 - TS4, CO4
IOH = -2 mA
IOH = -4 mA
IOH = -8 mA
VDD-0.4 V
VOH (3.3V)
Low Level Output Voltage
Type 2 - TS2, CO2, TS2D2
Type 3 - TS3
Type 4 - TS4, CO4
IOL = -1 mA
IOL = -2 mA
IOL = -4 mA
VDD-0.3 V
VOH (3.0V)
High Level Output Voltage
Type 2- TS2, CO2, TS2D2
Type 3- TS3
Type 4- TS4, CO4
IOH = -1 mA
IOH = -1.8 mA
IOH = -3.5 mA
VDD-0.3 V
IOZ Output Leakage Current -1 1 µA
COUT Output Pin Capacitance 6pF
CBID Bidirectional Pin Capacitance 10 pF

GRAPHICS
SED1352
X16B-C-001-06 9
■SED1352 PIN OUTS
1 2 3 4 5 6
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
81
82
83
84
85
32
33
34
35
36
37
38
39
40
41
42
43
44
45
50
49
48
47
46
31
7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DB6
DB5
DB4
DB3
DB2
DB1
DB0
OSC2
OSC1
BHE#
READY
MEMR#
MEMW#
MEMCS#
IOR#
IOW#
IOCS#
VOE#
LCDENB
XSCL
AB19
VA0
VA1
VA2
VA3
VA4
VA5
VA6
VA7
VA8
VA9
VA10
VD0
VD1
VD2
VD3
VD4
VD5
VD6
SED1352F0B
DB7
VSS
VDD DB8 DB9
DB10 DB11 DB12 DB13 DB15
AB0 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9
AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 DB14
WF LP YD LD0 LD1 LD2 LD3 UD0 UD1
UD2
UD3 VCS1# VCS0# VWE# VA15 VA14 VA13 VA12 VA11 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 VDD
VSS VD7
RESET

GRAPHICS
SED1352
X16B-C-001-06
10
1 2 3 4 5 6
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
81
82
83
84
85
32
33
34
35
36
37
38
39
40
41
42
43
44
45
50
49
48
47
46
31
7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
26
27
28
29
30
80
79
78
77
76
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DB6
DB5
DB4
DB3
DB2
DB1
DB0
OSC2
OSC1
BHE#
READY
MEMR#
MEMW#
MEMCS#
IOR#
IOW#
IOCS#
VOE#
LCDENB
XSCL
AB19
VA0
VA1
VA2
VA3
VA4
VA5
VA6
VA7
VA8
VA9
VA10
VD0
VD1
VD2
VD3
VD4
VD5
VD6
SED1352F1B
DB7
VDD
VSS
DB8 DB9
DB10 DB11 DB12 DB13 DB15
AB0 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9
AB10 AB11 AB12 AB13
AB14 AB15 AB16
AB17
AB18
DB14
WF
LP
YD LD0 LD1 LD2 LD3 UD0 UD1
UD2
UD3 VCS1# VCS0# VWE# VA15 VA14 VA13 VA12 VA11 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8
VSS
VD7
RESET
VDD

GRAPHICS
SED1352
X16B-C-001-06 11
DB7
VSS
VDD
DB8 DB9 DB10 DB11 DB12 DB13 DB15 AB0 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 DB14 AB14 AB15 AB16
AB17
AB18
AB19
VA0
VA1
VA2
VA3
VA4
VA5
VA6
VA7
VA8
VA9
VA10
VD0
VD1
VD2
VD3
VD4
VD5
VD6
RESET
WF
LP
YD
LD0 LD1 LD2 LD3
UD0 UD1 UD2 UD3
VCS1# VCS0#
VWE#
VA15 VA14 VA13 VA12 VA11
VD15 VD14 VD13 VD12 VD11 VD10
VD9 VD8
VDD
VSS
VD7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
OSC2
OSC1
BHE#
READY
MEMR#
MEMW#
MEMCS#
IOR#
IOW#
IOCS#
VOE#
LCDENB
XSCL
110 20
30
40
50
60
70
80
90
100
Dummy Pad
Dummy Pad
Chip Size
Chip Thickness
Pad Size
Pad Pitch
4.400 mm x 4.400 mm
0.400 mm
0.090 mm x 0.090 mm
0.140 mm (Min.)
=
=
=
=
SED1352D0B

GRAPHICS
SED1352
X16B-C-001-06
12
PAD Coordinates
Pad
No. Pin Name
Pad Center
Coordinate Pad
No. Pin Name
Pad Center
Coordinate
XY XY
1 DB8 -1.850 -2.071 37 VA7 2.071 -0.140
2 DB9 -1.670 -2.071 38 VA8 2.071 0.000
3 DB10 -1.496 -2.071 39 VA9 2.071 0.140
4 DB11 -1.330 -2.071 40 VA10 2.071 0.281
5 DB12 -1.168 -2.071 41 VD0 2.071 0.423
6 DB13 -1.012 -2.071 42 VD1 2.071 0.566
7 DB14 -0.860 -2.071 43 VD2 2.071 0.712
8 DB15 -0.712 -2.071 44 VD3 2.071 0.860
9 AB0 -0.566 -2.071 45 VD4 2.071 1.012
10 AB1 -0.423 -2.071 46 VD5 2.071 1.168
11 AB2 -0.281 -2.071 47 VD6 2.071 1.330
12 AB3 -0.140 -2.071 48 VD7 2.071 1.496
13 AB4 0.000 -2.071 49 VSS 2.071 1.670
14 AB5 0.140 -2.071 50 VDD 2.071 1.850
15 AB6 0.281 -2.071 51 VD8 1.850 2.071
16 AB7 0.423 -2.071 52 VD9 1.670 2.071
17 AB8 0.566 -2.071 53 VD10 1.496 2.071
18 AB9 0.712 -2.071 54 VD11 1.330 2.071
19 AB10 0.860 -2.071 55 VD12 1.168 2.071
20 AB11 1.012 -2.071 56 VD13 1.012 2.071
21 AB12 1.168 -2.071 57 VD14 0.860 2.071
22 AB13 1.330 -2.071 58 VD15 0.712 2.071
23 AB14 1.496 -2.071 59 VA11 0.566 2.071
24 AB15 1.670 -2.071 60 VA12 0.423 2.071
25 AB16 1.850 -2.071 61 VA13 0.281 2.071
26 AB17 2.071 -2.021 62 VA14 0.140 2.071
27 AB18 2.071 -1.670 63 VA15 0.000 2.071
28 AB19 2.071 -1.496 64 VWE# -0.140 2.071
29 RESET 2.071 -1.330 65 VCS0# -0.281 2.071
30 VA0 2.071 -1.168 66 VCS1# -0.423 2.071
31 VA1 2.071 -1.012 67 UD3 -0.566 2.071
32 VA2 2.071 -0.860 68 UD2 -0.712 2.071
33 VA3 2.071 -0.712 69 UD1 -0.860 2.071
34 VA4 2.071 -0.566 70 UD0 -1.012 2.071
35 VA5 2.071 -0.423 71 LD3 -1.168 2.071
36 VA6 2.071 -0.281 72 LD2 -1.330 2.071

GRAPHICS
SED1352
X16B-C-001-06 13
73 LD1 -1.496 2.071 88 BHE# -2.071 0.000
74 LD0 -1.670 2.071 89 OSC1 -2.071 -0.140
75 YD -2.021 2.071 90 OSC2 -2.071 -0.281
76 LP -2.071 1.850 91 DB0 -2.071 -0.423
77 WF -2.071 1.670 92 DB1 -2.071 -0.566
78 XSCL -2.071 1.496 93 DB2 -2.071 -0.712
79 LCDENB -2.071 1.330 94 DB3 -2.071 -0.860
80 VOE# -2.071 1.168 95 DB4 -2.071 -1.012
81 IOCS# -2.071 1.012 96 DB5 -2.071 -1.168
82 IOW# -2.071 0.860 97 DB6 -2.071 -1.330
83 IOR# -2.071 0.712 98 DB7 -2.071 -1.496
84 MEMCS# -2.071 0.566 99 VSS -2.071 -1.670
85 MEMW# -2.071 0.423 100 VDD -2.071 -1.850
86 MEMR# -2.071 0.281 101 Dummy Pad 2.071 2.071
87 READY -2.071 0.140 102 Dummy Pad -2.071 -2.071
Pad
No. Pin Name
Pad Center
Coordinate Pad
No. Pin Name
Pad Center
Coordinate
XY XY

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SED1352
X16B-C-001-06
14
■PIN DESCRIPTION
Key
Bus Interface
A=Analog
I = Input
O = Output
I/O = Bidirectional
P=Power
Pin Name Type F0B Pin # F1B Pin # D0B Pad
#Description
DB0-DB15 I/O 94 - 100, 1,
4 -11 91 - 98, 1 - 8 These pins are connected to the system data bus. In 8-bit bus mode, DB8-DB15 must be tied to VDD.
AB0 I 12 9 In MC68000 MPU interface, this pin is connected to the Upper Data Strobe (UDS#) pin of MC68000. In other bus interfaces, this pin is connected to the
system address bus.
AB1-AB19 I 13 - 31 10 - 28 These pins are connected to the system address bus.
BHE# I 91 88 In MC68000 MPU interface, this pin is connected to the Lower Data Strobe (LDS#) pin of MC68000. In other bus interfaces, this pin is the Bus High Enable
input for use with 16-bit system. In 8-bit bus mode, tie BHE# input to VDD.
IOCS# I 84 81 Active low input to select one of fifteen internal registers.
IOW# I 85 82
In MC68000 MPU interface, this pin is connected to the R/W# pin of MC68000.
This input pin will define whether the data transfer is a read (active high) or write
(active low) cycle. In other bus interfaces, this is the active low input to write data
into an internal register.
IOR# I 86 83 In MC68000 MPU interface, this pin is connected to the AS# pin of MC68000. This input pin will indicate a valid address is available on the address bus. In other
bus interfaces, this is the active low input to read data from an internal register.
MEMCS# I 87 84 Active low input to indicate the attempt to access the display memory.
MEMW# I 88 85 Active low input to write data to the display memory. This pin should be tied to
VDD in an MC68000 MPU interface.
MEMR# I 89 86 Active low input to read data from the display memory. This pin should be tied to
VDD in an MC68000 MPU interface.
READY O 90 87
For MC68000 MPU interface, this pin is connected to the DTACK# pin of
MC68000 and will be driven low when ever a data transfer is complete. In other
bus interfaces, this output is driven low to force the system to insert wait states
when needed.
READY is placed in a high-impedance (Hi-Z) state after the transfer is completed.
RESET I 32 29 Active high input to force all signals to their inactive states.