Epson S2R72V18 User manual

Rev.1.00
S2R72V18
Technical Manual

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Scope
This document applies to the S2R72V18 USB 2.0 device/host controller LSI.

S2R72V18 Technical Manual (Rev.1.00) EPSON i
Table of Contents
1. Functions........................................................................................................................................... 1
1.1 USB Ports................................................................................................................................ 1
1.2 USB Device/Host Selection ..................................................................................................... 2
1.2.1 USB Device/Host Function Selection Procedure............................................................... 2
1.2.2 USB Port State Change Detection Status.......................................................................... 2
1.2.2.1 USB Port State Change Detection Status Usage Examples........................................... 2
1.2.2.1.1 Device Port Change Status..................................................................................... 2
1.2.2.1.2 Host Port Change Status ........................................................................................ 3
1.2.2.2 Signal Line Change Status Usage.................................................................................. 3
1.3 USB Device Control................................................................................................................. 6
1.3.1 Endpoints.......................................................................................................................... 6
1.3.2 Transactions...................................................................................................................... 8
1.3.2.1 SETUP Transactions .................................................................................................... 10
1.3.2.2 Bulk/Interrupt OUT Transactions .................................................................................. 11
1.3.2.3 Isochronous OUT Transactions .................................................................................... 12
1.3.2.4 Bulk/Interrupt IN Transactions ...................................................................................... 13
1.3.2.5 Isochronous IN Transaction.......................................................................................... 14
1.3.2.6 PING Transactions .......................................................................................................15
1.3.3 Control Transfers............................................................................................................. 16
1.3.3.1 Setup Stage.................................................................................................................. 17
1.3.3.2 Data Stage/Status Stage............................................................................................... 18
1.3.3.3 Automatic Address Setup Function .............................................................................. 18
1.3.3.4 Descriptor Reply Function ............................................................................................ 18
1.3.4 Bulk/Interrupt/Isochronous Transfers............................................................................... 19
1.3.5 Data Flow ........................................................................................................................ 19
1.3.5.1 OUT Transfer................................................................................................................ 19
1.3.5.2 IN Transfer.................................................................................................................... 20
1.3.6 Bulk-Only Support ........................................................................................................... 20
1.3.6.1 CBW Support............................................................................................................... 21
1.3.6.2 CSW Support............................................................................................................... 22
1.3.7 Cable Negotiation Function (Auto Negotiator) ................................................................. 23
1.3.7.1 Auto Negotiator ............................................................................................................ 24
1.3.7.1.1 DISABLE .............................................................................................................. 24
1.3.7.1.2 IDLE...................................................................................................................... 24
1.3.7.1.3 WAIT_TIM3US...................................................................................................... 24

ii EPSON S2R72V18 Technical Manual (Rev.1.00)
1.3.7.1.4 WAIT_CHIRP........................................................................................................ 25
1.3.7.1.5 WAIT_RSTEND .................................................................................................... 25
1.3.7.1.6 DET_SUSPEND ................................................................................................... 25
1.3.7.1.7 IN_SUSPEND....................................................................................................... 25
1.3.7.1.8 CHK_EVENT........................................................................................................ 26
1.3.7.1.9 WAIT_RESTORE.................................................................................................. 26
1.3.7.1.10 ERR ...................................................................................................................... 26
1.3.7.2 Operation for Individual Bus Events ............................................................................. 26
1.3.7.2.1 Suspend Detection in HS Mode............................................................................ 26
1.3.7.2.2 Suspend Detection in FS Mode ............................................................................ 28
1.3.7.2.3 Reset Detection in HS Mode ................................................................................ 30
1.3.7.2.4 Reset Detection in FS Mode................................................................................. 31
1.3.7.2.5 HS Detection Handshake..................................................................................... 32
1.3.7.2.5.1 When Connected to the FS Host Downstream Port ....................................... 33
1.3.7.2.5.2 When Connected to the HS Host Downstream Port....................................... 35
1.3.7.2.5.3 If Reset During Sleep ..................................................................................... 37
1.3.7.2.6 Resume Issue....................................................................................................... 39
1.3.7.2.7 Resume Detection ................................................................................................ 41
1.3.7.2.8 Cable Attachment ................................................................................................. 43
1.4 USB Host Control .................................................................................................................. 45
1.4.1 Channels ......................................................................................................................... 45
1.4.1.1 Channel Outline............................................................................................................ 45
1.4.1.2 Dedicated Control Channel .......................................................................................... 47
1.4.1.3 General Channels ........................................................................................................48
1.4.1.4 Channel Usage Examples............................................................................................ 50
1.4.1.4.1 With One Storage Device Connected ................................................................... 50
1.4.1.4.2 With One Communication Device Connected....................................................... 51
1.4.1.4.3 With One Human Interface Device Connected ..................................................... 52
1.4.1.4.4 With Two Storage Devices Connected Via a Hub ................................................. 53
1.4.2 Scheduling....................................................................................................................... 54
1.4.3 Transactions.................................................................................................................... 55
1.4.3.1 SETUP Transaction...................................................................................................... 56
1.4.3.2 Bulk OUTTransaction .................................................................................................. 57
1.4.3.3 Interrupt OUT Transaction............................................................................................ 59
1.4.3.4 Isochronous OUT Transaction...................................................................................... 60
1.4.3.5 Bulk IN Transaction ...................................................................................................... 61
1.4.3.6 Interrupt IN Transaction................................................................................................63
1.4.3.7 Isochronous IN Transaction.......................................................................................... 65

S2R72V18 Technical Manual (Rev.1.00) EPSON iii
1.4.3.8 PING Transaction ......................................................................................................... 67
1.4.3.9 Low-speed (LS) Transaction ........................................................................................ 69
1.4.3.10 Split Transaction ........................................................................................................... 71
1.4.4 Control Transfers............................................................................................................. 72
1.4.4.1 Setup stage .................................................................................................................. 73
1.4.4.2 Data Stage/Status Stage............................................................................................... 73
1.4.4.3 Control Transfer Support Function ............................................................................... 74
1.4.5 Bulk/Interrupt/Isochronous Transfers............................................................................... 77
1.4.6 Data Flow ........................................................................................................................ 77
1.4.6.1 OUT Transfers.............................................................................................................. 77
1.4.6.2 IN Transfers.................................................................................................................. 78
1.4.7 Zero Length Packet Automatic Issuing Function ............................................................. 79
1.4.7.1 Bulk/Interrupt OUT Transfer Zero-Length Packet Automatic Issuing Function ............. 79
1.4.8 Bulk-Only Support Function............................................................................................. 80
1.4.9 Audio Class Assist Function ............................................................................................ 85
1.4.10 Host State Management Support Function...................................................................... 86
1.4.10.1 Host State..................................................................................................................... 86
1.4.10.1.1 IDLE...................................................................................................................... 88
1.4.10.1.2 WAIT_CONNECT ................................................................................................. 89
1.4.10.1.3 DISABLED............................................................................................................ 90
1.4.10.1.4 RESET.................................................................................................................. 90
1.4.10.1.5 OPERATIONAL .................................................................................................... 92
1.4.10.1.6 SUSPEND ............................................................................................................ 92
1.4.10.1.7 RESUME .............................................................................................................. 93
1.4.10.2 Detection Functions...................................................................................................... 94
1.4.10.2.1 VBUS Error Detection........................................................................................... 94
1.4.10.2.2 Disconnect Detection............................................................................................ 96
1.4.10.2.2.1 If HS Device is Disconnected ......................................................................... 96
1.4.10.2.2.2 If FS or LS Device is Disconnected ................................................................ 97
1.4.10.2.3 Remote Wakeup Detection ................................................................................... 98
1.4.10.2.3.1 If HS Device is Connected.............................................................................. 98
1.4.10.2.3.2 If FS Device is Connected............................................................................ 100
1.4.10.2.3.3 If LS Device is Connected............................................................................ 101
1.4.10.2.4 Device Chirp Detection Function ........................................................................ 102
1.4.10.2.4.1 If a Correct Device Chirp is Detected ........................................................... 102
1.4.10.2.4.2 If an Error Device Chirp is Detected ............................................................. 104
1.4.10.2.5 Port Error Detection ............................................................................................ 105
1.4.10.3 Individual Host State Management Support Function Explanations ........................... 106

iv EPSON S2R72V18 Technical Manual (Rev.1.00)
1.4.10.3.1 GoIDLE...............................................................................................................106
1.4.10.3.2 GoWAIT_CONNECT .......................................................................................... 108
1.4.10.3.2.1 If an FS Device is Connected ....................................................................... 108
1.4.10.3.2.2 If an LS Device is Connected ....................................................................... 110
1.4.10.3.3 GoDISABLED ..................................................................................................... 112
1.4.10.3.3.1 If an HS Device is Connected....................................................................... 112
1.4.10.3.3.2 If an FS Device is Connected ....................................................................... 114
1.4.10.3.3.3 If an LS Device is Connected ....................................................................... 116
1.4.10.3.4 GoRESET........................................................................................................... 118
1.4.10.3.4.1 Resetting for HS Device ............................................................................... 118
1.4.10.3.4.2 Error Device Chirp Detection........................................................................ 121
1.4.10.3.4.2.1 If Chirp Completion Disable
(H_NegoControl_1.DisChirpFinish) Setting is 0 ....................................... 121
1.4.10.3.4.2.2 If Chirp Completion Disable
(H_NegoControl_1.DisChirpFinish) Setting is 1 ....................................... 123
1.4.10.3.4.3 Resetting for FS Device................................................................................ 126
1.4.10.3.4.4 Resetting for LS Device................................................................................ 128
1.4.10.3.5 GoOPERATIONAL.............................................................................................. 129
1.4.10.3.6 GoSUSPEND...................................................................................................... 130
1.4.10.3.6.1 If HS Device is Connected............................................................................ 130
1.4.10.3.6.2 If FS Device is Connected............................................................................ 132
1.4.10.3.6.3 If LS Device is Connected............................................................................ 134
1.4.10.3.7 GoRESUME........................................................................................................ 136
1.4.10.3.7.1 If HS Device is Connected............................................................................ 136
1.4.10.3.7.2 If FS Device is Connected............................................................................ 138
1.4.10.3.7.3 If LS Device is Connected............................................................................ 140
1.4.10.3.8 GoWAIT_CONNECTtoDIS ................................................................................. 142
1.4.10.3.9 GoWAIT_CONNECTtoOP .................................................................................. 143
1.4.10.3.9.1 If HS Device is Connected............................................................................ 143
1.4.10.3.9.2 If FS or LS Device is Connected .................................................................. 145
1.4.10.3.10 GoRESETtoOP................................................................................................... 147
1.4.10.3.10.1 If HS Device is Connected............................................................................ 147
1.4.10.3.10.2 If FS or LS Device is Connected .................................................................. 148
1.4.10.3.11 GoSUSPENDtoOP ............................................................................................. 149
1.4.10.3.12 GoRESUMEtoOP ............................................................................................... 151
1.5 Power Management Functions ............................................................................................ 152
1.5.1 SLEEP........................................................................................................................... 153
1.5.2 ACTIVE ......................................................................................................................... 153
1.6 FIFO Management .............................................................................................................. 154

S2R72V18 Technical Manual (Rev.1.00) EPSON v
1.6.1 FIFO Memory Map ........................................................................................................ 154
1.6.2 Descriptor Area.............................................................................................................. 155
1.6.2.1 Writing Data to Descriptor Area .................................................................................. 155
1.6.2.2 Executing Data Stage (IN) with Descriptor Area ......................................................... 156
1.6.3 CBW Area...................................................................................................................... 156
1.6.3.1 CBW Area (for USB device) ....................................................................................... 156
1.6.3.2 CBW Area (for USB host) ........................................................................................... 156
1.6.4 CSW Area...................................................................................................................... 157
1.6.4.1 CSW Area (for USB device) ....................................................................................... 157
1.6.4.2 CSW Area (for USB host) ........................................................................................... 157
1.6.5 FIFO Access Methods ................................................................................................... 157
1.6.5.1 RAM Access (RAM_Rd) ............................................................................................. 157
1.6.5.2 RAM Access (RAM_WrDoor) ..................................................................................... 158
1.6.5.3 FIFO Access (Register Access).................................................................................. 158
1.6.5.4 FIFO Access (DMA) ................................................................................................... 158
1.6.5.5 FIFO Access Restrictions ........................................................................................... 159
1.7 CPUIF.................................................................................................................................. 160
1.7.1 CPUIF Mode.................................................................................................................. 160
1.7.2 CPUIF Mode Setup ....................................................................................................... 161
1.7.3 Block Configuration .......................................................................................................163
1.7.3.1 REG (Registers) .........................................................................................................163
1.7.3.1.1 Synchronous Register Access (Write) ................................................................ 163
1.7.3.1.2 Synchronous Register Access (Read) ................................................................ 163
1.7.3.1.3 FIFO Access (Write) ........................................................................................... 164
1.7.3.1.4 FIFO Access (Read) ........................................................................................... 164
1.7.3.1.5 FIFO Access Fractional Number Processing ...................................................... 165
1.7.3.1.6 RAM_Rd Access................................................................................................. 168
1.7.3.1.7 Asynchronous Register Access (Writing)............................................................ 168
1.7.3.1.8 Asynchronous Register Access (Reading).......................................................... 168
1.7.3.2 DMA0/DMA1(DMA ch.0/ch.1)..................................................................................... 169
1.7.3.2.1 Basic Functions .................................................................................................. 169
1.7.3.2.2 Terminal Setup.................................................................................................... 171
1.7.3.2.3 Count Mode (Write) ............................................................................................ 171
1.7.3.2.4 Count Mode (Read) ............................................................................................ 173
1.7.3.2.5 Free-run Mode (Write) ........................................................................................ 175
1.7.3.2.6 Free-run Mode (Read) ........................................................................................ 175
1.7.3.2.7 REQ Assert Count Option (Write) ....................................................................... 176
1.7.3.2.8 REQ Assert Count Option (Read) ....................................................................... 177

vi EPSON S2R72V18 Technical Manual (Rev.1.00)
1.7.3.2.9 DMA FIFO Access Fractional Number Processing ............................................. 177
2. Register Maps ............................................................................................................................... 178
2.1 Register Configuration......................................................................................................... 178
2.2 Initial Register Map.............................................................................................................. 179
2.3 Port 0 Register Maps........................................................................................................... 180
2.3.1 Device/Host Common Register Map ............................................................................. 180
2.3.2 Device Register Map ..................................................................................................... 186
2.3.3 Host Register Map.........................................................................................................190
2.4 Port 1 Register Maps........................................................................................................... 195
2.4.1 Device/Host Common Register Map ............................................................................. 195
2.4.2 Host Register Map.........................................................................................................201
3. Register Details............................................................................................................................. 206
3.1 Device/Host Common Register Details ............................................................................... 206
3.1.1 Port0:000h / Port1:200h MainIntStat (Main Interrupt Status) ...................................... 207
3.1.2 Port0:001h / Port1:N/A USB_DeviceIntStat (USB Device Interrupt Status)................. 209
3.1.3 Port0:002h / Port1:202h USB_HostIntStat (USB Host Interrupt Status)...................... 211
3.1.4 Port0:003h / Port1:203h CPU_IntStat (CPU Interrupt Status) ..................................... 213
3.1.5 Port0:004h / Port1:204h FIFO_IntStat (FIFO Interrupt Status).................................... 214
3.1.6 Port0:006h / Port1:206h RootIntStat (Root Interrupt Status)....................................... 215
3.1.7 Port0:008h / Port1:208h MainIntEnb (Main Interrupt Enable) ..................................... 216
3.1.8 Port0:009h / Port1:N/A USB_DeviceIntEnb (Device Interrupt Enable)........................ 217
3.1.9 Port0:00Ah / Port1:20Ah USB_HostIntEnb (Host Interrupt Enable)............................ 218
3.1.10 Port0:00Bh / Port1:20Bh CPU_IntEnb
(CPU Interrupt Enable)................................... 219
3.1.11 Port0:00Ch / Port1:20Ch FIFO_IntEnb (FIFO Interrupt Enable) ................................. 220
3.1.12 Port0:010h / Port1:210h RevisionNum (Revision Number)......................................... 221
3.1.13 Port0:011h / Port1:211h ChipReset (Chip Reset)........................................................ 222
3.1.14 Port0:012h / Port1:212h PM_Control (Power Management Control) .......................... 223
3.1.15 Port0:014h-015h / Port1:214h-215h WakeupTim_H,L (Wakeup Time High, Low)...... 225
3.1.16 Port0:016h / Port1:216h H_USB_Control (Host USB Control )................................... 226
3.1.17 Port0:017h / Port1:217h H_XcvrControl (Host Xcvr Control) ...................................... 227
3.1.18 Port0:018h / Port1:N/A D_USB_Status (Device USB Status) ..................................... 229
3.1.19 Port0:019h / Port1:219h H_USB_Status (Host USB Status)....................................... 230
3.1.20 Port0:01Bh / Port1 MTM_Config (Multi Transceiver Macro Config) ............................ 231
3.1.21 Port0:01Fh / Port1:21Fh HostDeviceSel (Host Device Select) ................................... 232
3.1.22 Port0:020h / Port1:220h FIFO_Rd_0
(FIFO Read 0) .................................................. 233
3.1.23 Port0:021h / Port1:221h FIFO_Rd_1
(FIFO Read 1) .................................................. 233
3.1.24 Port0:022h / Port1:222h FIFO_Wr_0(FIFO Write 0) ................................................... 234

S2R72V18 Technical Manual (Rev.1.00) EPSON vii
3.1.25 Port0:023h / Port1:223h FIFO_Wr_1(FIFO Write 1) ................................................... 234
3.1.26 Port0:024h-025h / Port1:224h-225h FIFO_RdRemain_H,L
(FIFO Read Remain High, Low) .................................................................................... 235
3.1.27 Port0:026h-027h / Port1:226h-227h FIFO_WrRemain_H,L
(FIFO Write Remain High, Low) ..................................................................................... 236
3.1.28 Port0:028h / Port1:228h FIFO_ByteRd(FIFO Byte Read)........................................... 237
3.1.29 Port0:02Ah / Port1:22Ah FIFO_ByteWr(FIFO Byte Write) .......................................... 238
3.1.30 Port0:030h-031h / Port1:230h-231h RAM_RdAdrs_H,L
(RAM Read Address High, Low) ................................................................................... 239
3.1.31 Port0:032h / Port1:232h RAM_RdControl (RAM Read Control) ................................. 240
3.1.32 Port0:035h / Port1:235h RAM_RdCount (RAM Read Counter) .................................. 241
3.1.33 Port0:038h-039h / Port1:238h-239h RAM_WrAdrs_H,L
(RAM Write Address High, Low).................................................................................... 242
3.1.34 Port0:03Ah / Port1:23Ah RAM_WrDoor_0 (RAM Write Door 0).................................. 243
3.1.35 Port0:03Bh / Port1:23Bh RAM_WrDoor_1 (RAM Write Door 1).................................. 243
3.1.36 Port0:040h / Port1:240h RAM_Rd_00 (RAM Read 00) .............................................. 244
3.1.37 Port0:041h / Port1:241h RAM_Rd_01 (RAM Read 01) .............................................. 244
3.1.38 Port0:042h / Port1:242h RAM_Rd_02 (RAM Read 02) .............................................. 244
3.1.39 Port0:043h / Port1:243h RAM_Rd_03 (RAM Read 03) .............................................. 244
3.1.40 Port0:044h / Port1:244h RAM_Rd_04 (RAM Read 04) .............................................. 244
3.1.41 Port0:045h / Port1:245h RAM_Rd_05 (RAM Read 05) .............................................. 244
3.1.42 Port0:046h / Port1:246h RAM_Rd_06 (RAM Read 06) .............................................. 244
3.1.43 Port0:047h / Port1:247h RAM_Rd_07 (RAM Read 07) .............................................. 244
3.1.44 Port0:048h / Port1:248h RAM_Rd_08 (RAM Read 08) .............................................. 244
3.1.45 Port0:049h / Port1:249h RAM_Rd_09 (RAM Read 09) .............................................. 244
3.1.46 Port0:04Ah / Port1:24Ah RAM_Rd_0A(RAM Read 0A) ............................................. 244
3.1.47 Port0:04Bh / Port1:24Bh RAM_Rd_0B (RAM Read 0B) ............................................. 244
3.1.48 Port0:04Ch / Port1:24Ch RAM_Rd_0C
(RAM Read 0C) ............................................ 244
3.1.49 Port0:04Dh / Port1:24Dh RAM_Rd_0D
(RAM Read 0D) ............................................ 244
3.1.50 Port0:04Eh / Port1:24Eh RAM_Rd_0E (RAM Read 0E) ............................................. 244
3.1.51 Port0:04Fh / Port1:24Fh RAM_Rd_0F
(RAM Read 0F).............................................. 244
3.1.52 Port0:050h / Port1:250h RAM_Rd_10 (RAM Read 10) .............................................. 244
3.1.53 Port0:051h / Port1:251h RAM_Rd_11 (RAM Read 11) ............................................... 244
3.1.54 Port0:052h / Port1:252h RAM_Rd_12 (RAM Read 12) .............................................. 244
3.1.55 Port0:053h / Port1:253h RAM_Rd_13 (RAM Read 13) .............................................. 244
3.1.56 Port0:054h / Port1:254h RAM_Rd_14 (RAM Read 14) .............................................. 244
3.1.57 Port0:055h / Port1:255h RAM_Rd_15 (RAM Read 15) .............................................. 244
3.1.58 Port0:056h / Port1:256h RAM_Rd_16 (RAM Read 16) .............................................. 244
3.1.59 Port0:057h / Port1:257h RAM_Rd_17 (RAM Read 17) .............................................. 244