Epson S5U13A04B00C User manual

Rev. 3.1
S1D13A04 LCD/USB Companion Chip
S5U13A04B00C Rev. 1.0
Evaluation Board User Manual
Document Number: X37A-G-004-03.1

NOTICE
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©SEIKO EPSON CORPORATION 2001-2018. All rights reserved.
Evaluation Board/Kit and Development Tool Important Notice
1. This evaluation board/kit or development tool is designed for use for engineering evaluation, demonstration, or develop-
ment purposes only. Do not use it for other purposes. It is not intended to meet the requirements of design for finished
products.
2. This evaluation board/kit or development tool is intended for use by an electronics engineer and is not a consumer product.
The user should use it properly and in a safe manner. Seiko Epson does not assume any responsibility or liability of any
kind of damage and/or fire caused by the use of it. The user should cease to use it when any abnormal issue occurs even
during proper and safe use.
3. The part used for this evaluation board/kit or development tool may be changed without any notice.
2Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board
Rev. 3.1

S5U13A04B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 3
Rev. 3.1
Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Configuration DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 CPU Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 CPU Bus Connector Pin Mapping . . . . . . . . . . . . . . . . . . . . . . 13
5 LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 PCI Bus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 Direct Host Bus Interface Support . . . . . . . . . . . . . . . . . . . . . . 18
6.3 S1D13A04 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 Adjustable LCD Panel Negative Power Supply . . . . . . . . . . . . . . . . . 18
6.5 Adjustable LCD Panel Positive Power Supply . . . . . . . . . . . . . . . . . . 19
6.6 Software Adjustable LCD Backlight Intensity Support Using PWM . . . . . . . . . 19
6.7 LCD Panel Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.7.1 Direct LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.7.2 Extended LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.8 USB Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.8.1 USB IRQ Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 Clock Synthesizer and Clock Options . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
10 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
11 Change Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
12 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board
Rev. 3.1

Introduction
S5U13A04B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 5
Rev. 3.1
1 Introduction
This manual describes the setup and operation of the S5U13A04B00C Rev. 1.0 Evaluation
Board. The board is designed as an evaluation platform for the S1D13A04 LCD/USB
Companion Chip.
This document is updated as appropriate. Please check for the latest revision of this
document before beginning any development. The latest revision can be downloaded at
vdc.epson.com.
We appreciate your comments on our documentation. Please contact us via email at
[e-mail].

Features
6Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board
Rev. 3.1
2 Features
Following are some features of the S5U13A04B00C Rev. 1.0 Evaluation Board:
• 121-pin PFBGA S1D13A04 Embedded Memory LCD Controller with 160K bytes of
embedded SRAM.
• PCI bus operation through onboard PCI bridge.
• CPU/Bus interface header strips for non-PCI bus operation.
• Configuration options.
• On-board adjustable positive LCD bias power supply from +23V to +40V.
• On-board adjustable negative LCD bias power supply from -14V to -24V.
• Software adjustable backlight intensity support using PWMOUT.
• 4/8-bit 3.3V or 5V single monochrome passive LCD panel support.
• 4/8/16-bit 3.3V or 5V single color passive LCD panel support.
• 9/12/18-bit 3.3V or 5V active matrix TFT LCD panel support.
• Direct interface for 18-bit Epson D-TFD LCD panel support.
• Direct interface for 18-bit Sharp HR-TFT LCD panel support.
• Programmable clock synthesizer to CLKI and CLKI2 for maximum clock flexibility.
• Connector for USB client support.
• Software initiated power save mode.
• Selectable clock source for CLKI and CLKI2.
• External oscillator support for CLKI and CLKI2.

Installation and Configuration
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Rev. 3.1
3 Installation and Configuration
The S5U13A04B00C is designed to support as many platforms as possible. The
S5U13A04B00C incorporates a DIP switch and five jumpers which allow both the evalu-
ation board and the S1D13A04 LCD controller to be configured for a specified evaluation
platform.
3.1 Configuration DIP Switches
The S1D13A04 has configuration inputs (CNF[6:0]) which are read on the rising edge of
RESET#. In order to configure the S1D13A04 for multiple Host Bus Interfaces an eight-
position DIP switch (SW1) is required. The following figure shows the location of DIP
switch SW1 on the S5U13A04B00C.
Figure 3-1: Configuration DIP Switch (SW1) Location
DIP Switch - SW1

Installation and Configuration
8Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board
Rev. 3.1
The S1D13A04 has seven configuration inputs (CONF[6:0]) which are read on the rising
edge of RESET#. All S1D13A04 configuration inputs are fully configurable using an eight
position DIP switch as described below.
Table 3-1: Configuration DIP Switch Settings
Switch
(SW1)
S1D13A04
Signal
Value on this pin at rising edge of RESET# is used to configure:
Closed (On/1) Open (Off/0)
SW1-5,
SW1-[3:1]
CNF4,
CNF[2:0]
Select host bus interface as follows:
CNF4 CNF2 CNF1 CNF0 Host Bus Interface
1 0 0 0 SH-4/SH-3 interface, Big Endian
0 0 0 0 SH-4/SH-3 interface, Little Endian
1 0 0 1 MC68K #1, Big Endian
0 0 0 1 Reserved
1 0 1 0 MC68K #2, Big Endian
0 0 1 0 Reserved
1 0 1 1 Generic #1, Big Endian
0 0 1 1 Generic #1, Little Endian
1 1 0 0 Reserved
0 1 0 0 Generic #2, Little Endian
1 1 0 1 RedCap 2, Big Endian
0 1 0 1 Reserved
1 1 1 0 DragonBall, Big Endian
0 1 1 0 Reserved
X 1 1 1 Reserved
SW1-4 CNF3 Configure GPIO pins as inputs at power-on
Configure GPIO[7:6] and GPIO[4:0] as outputs
and GPIO5 as an input at power-on (for use
when USB is selected)
SW1-6 CNF5 WAIT# is active high WAIT# is active low
SW1-7 CNF6 CLKI to BCLK Divide ratio 2:1 CLKI to BCLK divide ratio 1:1
SW1-8 - Disable PCI bridge for non-PCI host Enable PCI bridge for PCI host
= Required settings when used with PCI Bridge FPGA

Installation and Configuration
S5U13A04B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 9
Rev. 3.1
3.2 Configuration Jumpers
The S5U13A04B00C has five jumper blocks which configure various setting on the board.
The jumper positions for each function are shown below.
JP1 - CLKI Source
JP1 selects the source for the CLKI input pin.
Position 1-2 sets the CLKI source to VCLKOUT from the Cypress clock synthesizer
(default setting).
Position 2-3 sets the CLKI source to the external oscillator at U7.
When no jumper is installed, the CLKI source is set to the BUSCLK signal from Header
H4.
Figure 3-2: Configuration Jumper (JP1) Location
Table 3-2: Jumper Summary
Jumper Function Position 1-2 Position 2-3 No Jumper
JP1 CLKI Source VCLKOUT from clock
synthesizer External oscillator (U7) BUSCLK from Header H4
JP2 CLKI2 Source MCLKOUT from clock
synthesizer External oscillator (U8) —
JP3 LCD Panel Voltage +5V LCDVCC +3.3V LCDVCC —
JP4 GP0I0 Polarity on H1 Normal (Active High) Inverted (Active Low) GPIO0 not sent to H1
JP5 GPIO0 function select GPIO0 HR-TFT PS signal —
= recommended settings
JP1
VCLKOUT from
clock synthesizer
External
oscillator (U7)
BUSCLK from
Header H4

Installation and Configuration
10 Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board
Rev. 3.1
JP2 - CLKI2 Source
JP2 selects the source for the CLKI2 input pin.
Position 1-2 sets the CLKI2 source to MCLKOUT from the Cypress clock synthesizer
(default setting).
Position 2-3 sets the CLKI2 source to the external oscillator at U8.
Figure 3-3: Configuration Jumper (JP2) Location
JP3 - LCD Panel Voltage
JP3 selects the voltage level to the LCD panel.
Position 1-2 sets the voltage level to 5.0V (default setting).
Position 2-3 sets the voltage level to 3.3V.
Note
When configured for Sharp HR-TFT or Epson D-TFD panels, JP3 and JP5 must be set
to position 2-3.
Figure 3-4: Configuration Jumper (JP3) Location
JP2
MCLKOUT from
clock synthesizer
External
oscillator (U8)
+5 LCDVCC +3.3 LCDVCC
JP3

Installation and Configuration
S5U13A04B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 11
Rev. 3.1
JP4 - GPIO0 Polarity on H1
JP4 selects the polarity of the GPIO0 signal available on the LCD Connector H1.
Position 1-2 sends the GPIO0 signal directly to H1 (default setting).
Position 2-3 inverts the GPIO0 signal before sending it to H1.
When no jumper is installed, GPIO0 is not sent to H1.
Figure 3-5: Configuration Jumper (JP4) Location
JP5 - GPIO0 Selection
JP5 selects the function of the GPIO0 signal.
Position 1-2 GPIO0 used to control the LCD bias power supplies for STN panels.
Position 2-3 GPIO0 used as the PS signal when the S1D13A04 is configured for HR-TFT
panel type.
Figure 3-6: Configuration Jumper (JP5) Location
Normal Inverted GPIO0 not
JP4
(Active High) (Active Low) sent to H1
JP5
GPIO0 HR-TFT PS
signal

CPU Interface
12 Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board
Rev. 3.1
4 CPU Interface
4.1 CPU Interface Pin Mapping
Note
1 A0 for these busses is not used internally by the S1D13A04 and should be connected
to VSS.
2 If the target MC68K bus is 32-bit, then these signals should be connected to D[31:16].
3 These pins are not used in their corresponding host interface mode. Systems are
responsible for externally connecting them to Host Interface IO VDD.
Table 4-1: CPU Interface Pin Mapping
S1D13A04 Pin Name Generic #1 Generic #2 Hitachi
SH-3 /SH-4
Motorola
MC68K #1
Motorola
MC68K #2
Motorola
REDCAP2
Motorola
MC68EZ328/
MC68VZ328
DragonBall
AB[17:1] A[17:1] A[17:1] A[17:1] A[17:1] A[17:1] A[17:1] A[17:1]
AB0 A01A0 A01LDS# A0 A01A01
DB[15:0] D[15:0] D[15:0] D[15:0] D[15:0] D[15:0]2D[15:0] D[15:0]
CS# External Decode CSn# External Decode CSn CSX
M/R# External Decode
CLKI BUSCLK BUSCLK CKIO CLK CLK CLK CLK
BS# Connected to HIOVDD3BS# AS# AS# Connected to HIOVDD3
RD/WR# RD1# Connected
to HIOVDD3RD/WR# R/W# R/W# R/W Connected to HIOVDD3
RD# RD0# RD# RD# Connected
to HIOVDD3SIZ1 OE OE
WE0# WE0# WE# WE0# Connected
to HIOVDD3SIZ0 EB1 LWE
WE1# WE1# BHE# WE1# UDS# DS# EB0 UWE
WAIT# WAIT# WAIT# WAIT#/
RDY# DTACK# DSACK1# N/A DTACK
RESET# RESET# RESET# RESET# RESET# RESET# RESET_OUT RESET

CPU Interface
S5U13A04B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 13
Rev. 3.1
4.2 CPU Bus Connector Pin Mapping
Table 4-2: CPU Bus Connector (H3) Pinout
Connector
Pin No. Comments
1Connected to DB0 of the S1D13A04
2Connected to DB1 of the S1D13A04
3Connected to DB2 of the S1D13A04
4Connected to DB3 of the S1D13A04
5Ground
6Ground
7Connected to DB4 of the S1D13A04
8Connected to DB5 of the S1D13A04
9Connected to DB6 of the S1D13A04
10 Connected to DB7 of the S1D13A04
11 Ground
12 Ground
13 Connected to DB8 of the S1D13A04
14 Connected to DB9 of the S1D13A04
15 Connected to DB10 of the S1D13A04
16 Connected to DB11 of the S1D13A04
17 Ground
18 Ground
19 Connected to DB12 of the S1D13A04
20 Connected to DB13 of the S1D13A04
21 Connected to DB14 of the S1D13A04
22 Connected to DB15 of the S1D13A04
23 Connected to RESET# of the S1D13A04
24 Ground
25 Ground
26 Ground
27 +12 volt supply
28 +12 volt supply
29 Connected to WE0# of the S1D13A04
30 Connected to WAIT# of the S1D13A04
31 Connected to CS# of the S1D13A04
32 Connected to MR# of the S1D13A04
33 Connected to WE1# of the S1D13A04
34 Connected to +3.3V

CPU Interface
14 Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board
Rev. 3.1
Table 4-3: CPU Bus Connector (H4) Pinout
Connector
Pin No. Comments
1Connected to AB0 of the S1D13A04
2Connected to AB1 of the S1D13A04
3Connected to AB2 of the S1D13A04
4Connected to AB3 of the S1D13A04
5Connected to AB4 of the S1D13A04
6Connected to AB5 of the S1D13A04
7Connected to AB6 of the S1D13A04
8Connected to AB7 of the S1D13A04
9Ground
10 Ground
11 Connected to AB8 of the S1D13A04
12 Connected to AB9 of the S1D13A04
13 Connected to AB10 of the S1D13A04
14 Connected to AB11 of the S1D13A04
15 Connected to AB12 of the S1D13A04
16 Connected to AB13 of the S1D13A04
17 Ground
18 Ground
19 Connected to AB14 of the S1D13A04
20 Connected to AB15 of the S1D13A04
21 Connected to AB16 of the S1D13A04
22 Connected to AB17 of the S1D13A04
23 Not connected
24 Not connected
25 Ground
26 Ground
27 +5 volt supply
28 +5 volt supply
29 Connected to RD/WR# of the S1D13A04
30 Connected to BS# of the S1D13A04
31 Connected to BUSCLK of the S1D13A04
32 Connected to RD# of the S1D13A04
33 Not connected
34 Not connected

LCD Interface Pin Mapping
S5U13A04B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 15
Rev. 3.1
5 LCD Interface Pin Mapping
Note
1 These pin mappings use signal names commonly used for each panel type, however
signal names may differ between panel manufacturers. The values shown in brackets
represent the color components as mapped to the corresponding FPDATxx signals at
the first valid edge of FPSHIFT. For further FPDATxx to LCD interface mapping, see
S1D13A04 Hardware Functional Specification, document number X37A-A-001-xx.
2 DISPLAY can be disconnected from GPIO0 using JP5 (2-3 position) and can be
inverted on H1 setting JP4 to 2-3.
3 When the ’Direct’ HR-TFT interface is selected, DRDY becomes a general purpose
output (GPO) controllable using the ’Direct’ HR-TFT LCD Interface GPO Control bit
Table 5-1: LCD Signal Connector (H1)
Pin Name Connector
Pin No.
Monochrome
Passive Panel Color Passive Panel Color TFT Panel
Single Single Others Sharp
HR-TFT
Format 1 Format 2
4-bit 8-bit 4-bit 8-bit 8-bit 16-Bit 9-bit 12-bit 18-bit 18-bit
FPDAT0 1 driven 0 D0 driven 0 D0 (B5)1D0 (G3)1D0 (R6)1R2 R3 R5 R5
FPDAT1 3 driven 0 D1 driven 0 D1 (R5)1D1 (R3)1D1 (G5)1R1 R2 R4 R4
FPDAT2 5 driven 0 D2 driven 0 D2 (G4)1D2 (B2)1D2 (B4)1R0 R1 R3 R3
FPDAT3 7 driven 0 D3 driven 0 D3 (B3)1D3 (G2)1D3 (R4)1G2 G3 G5 G5
FPDAT4 9 D0 D4 D0 (R2)1D4 (R3)1D4 (R2)1D8 (B5)1G1 G2 G4 G4
FPDAT5 11 D1 D5 D1 (B1)1D5 (G2)1D5 (B1)1D9 (R5)1G0 G1 G3 G3
FPDAT6 13 D2 D6 D2 (G1)1D6 (B1)1D6 (G1)1D10 (G4)1B2 B3 B5 B5
FPDAT7 15 D3 D7 D3 (R1)1D7 (R1)1D7 (R1)1D11 (B3)1B1 B2 B4 B4
FPDAT8 17 driven 0 driven 0 driven 0 driven 0 driven 0 D4 (G3)1B0 B1 B3 B3
FPDAT9 19 driven 0 driven 0 driven 0 driven 0 driven 0 D5 (B2)1driven 0 R0 R2 R2
FPDAT10 21 driven 0 driven 0 driven 0 driven 0 driven 0 D6 (R2)1driven 0 driven 0 R1 R1
FPDAT11 23 driven 0 driven 0 driven 0 driven 0 driven 0 D7 (G1)1driven 0 driven 0 R0 R0
FPDAT12 25 driven 0 driven 0 driven 0 driven 0 driven 0 D12 (R3)1driven 0 G0 G2 G2
FPDAT13 27 driven 0 driven 0 driven 0 driven 0 driven 0 D13 (G2)1driven 0 driven 0 G1 G1
FPDAT14 29 driven 0 driven 0 driven 0 driven 0 driven 0 D14 (B1)1driven 0 driven 0 G0 G0
FPDAT15 31 driven 0 driven 0 driven 0 driven 0 driven 0 D15 (R1)1driven 0 B0 B2 B2
FPDAT16 4 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 B1 B1
FPDAT17 6 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 B0 B0
FPSHIFT 33 FPSHIFT CLK
DRDY 35 & 38 MOD FPSHIFT2 MOD DRDY GPO3
FPLINE 37 FPLINE LP
FPFRAME 39 FPFRAME SPS
GND 2, 8, 14, 20,
26 GND
PWMOUT 28 PWMOUT
VLCD 30 Adjustable -24V to -14V negative LCD bias
VCC 32 LCDVCC (3.3V or 5V)
+12V 34 +12V
VDDH 36 Adjustable +23V to +40V positive LCD bias
DISPLAY240 GPIO0 (for controlling on-board LCD bias power supply on/off) PS

LCD Interface Pin Mapping
16 Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board
Rev. 3.1
(REG[14h] bit 0). This GPO can be used to control the HR-TFT MOD signal if
required. For further information, see the S1D13A04 Hardware Functional
Specification, document number X37A-A-001-xx.

LCD Interface Pin Mapping
S5U13A04B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 17
Rev. 3.1
Note
1 When Switch SW1-4 is open (CNF3 = 0 at RESET#), GPIO[7:6] and GPIO[4:0] are
set as outputs at 0 (low state) and GPIO5 is set as an input at power-on/RESET#
(for use when USB is selected). If SW1-4 is closed then GPIO[7:0] are set as inputs
upon power-on/RESET#.
2 If the ’Direct’ HR-TFT interface is selected (REG[0Ch] bits 1:0 = 10), GPIO[3:0] are
used for the ’Direct’ HR-TFT interface. GPIO[7:4] remain available for USB support
or as GPIOs.
3 If USB support is enabled (REG[4000h] bit 7 = 1), GPIO[7:4] are used by the USB
interface. GPIO[3:0] remain available for ’Direct’ HR-TFT interface support or as
GPIOs.
Table 5-2: Extended LCD Signal Connector (H2)
Pin
Name
Connector
Pin No.
Monochrome
Passive Panel Color Passive Panel Color TFT Panel
USB3
Single Single Others HR-
TFT2
Format 1 Format 2
4-bit 8-bit 4-bit 8-bit 8-bit 16-Bit 9-bit 12-bit 18-bit 18-bit
GPIO011 GPIO0 PS GPIO0
GPIO113 GPIO1 CLS GPIO1
GPIO215 GPIO2 REV GPIO2
GPIO317 GPIO3 SPL GPIO3
GPIO419 GPIO4 USBPUP
GPIO5111 GPIO5 USBDET
ECT
GPIO6113 GPIO6 USBDM
GPIO7115 GPIO7 USBDP
GND 2, 4, 6, 8, 10,
12, 14, 16 GND

Technical Description
18 Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board
Rev. 3.1
6 Technical Description
6.1 PCI Bus Support
The S1D13A04 does not have on-chip PCI bus interface support. The S1D13A04B00C
uses the PCI Bridge FPGA to support the PCI bus.
6.2 Direct Host Bus Interface Support
The S5U13A04B00C is specifically designed to work using the PCI Bridge FPGA in a
standard PCI bus environment. However, the S1D13A04 directly supports many other host
bus interfaces. Connectors H3 and H4 provide the necessary IO pins to interface to these
host buses. For further information on the host bus interfaces supported, see “CPU
Interface” on page 12.
Note
The PCI Bridge FPGA must be disabled using SW1-8 in order for direct host bus inter-
face to operate properly.
6.3 S1D13A04 Embedded Memory
The S1D13A04 has 160K bytes of embedded SRAM. The 160K byte display buffer address
space is directly and contiguously available through the 18-bit address bus.
6.4 Adjustable LCD Panel Negative Power Supply
Most monochrome passive LCD panels require a negative power supply to provide
between -14V and -24V (Iout=45mA). Such a power supply (VLCD) has been provided on
the S5U13A04B00C board. VLCD can be adjusted using potentiometer R39 to provide an
output voltage from -14V to -24V, and is enabled/disabled using the S1D13A04 general
purpose signal, GPIO0 (active high).
Note
When manually adjusting the voltage, set the potentiometer according to the panel’s
specific power requirements before connecting the panel.

Technical Description
S5U13A04B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 19
Rev. 3.1
6.5 Adjustable LCD Panel Positive Power Supply
Most color passive LCD panels and most single monochrome 640x480 passive LCD panels
require a positive power supply to provide between +23V and +40V (Iout=45mA). Such a
power supply (VDDH) has been provided on the S5U13A04B00C board. VDDH can be
adjusted using R22 to provide an output voltage from +23V to +40V, and is
enabled/disabled using the S1D13A04 general purpose signal, GPIO0 (active high).
Note
When manually adjusting the voltage, set the potentiometer according to the panel’s
specific power requirements before connecting the panel.
6.6 Software Adjustable LCD Backlight Intensity Support Using PWM
The S1D13A04 provides Pulse Width Modulation output on PWMOUT. PWMOUT can be
used to control LCD panels which support PWM control of the backlight inverter. The
PWMOUT signal is provided on the LCD connector, H1.
6.7 LCD Panel Support
The S1D13A04 directly supports:
• Single-panel, single drive passive displays.
• 4/8-bit monochrome interface.
• 4/8/16-bit color interface.
• Active Matrix TFT interface.
• 9/12/18-bit interface.
• ’Direct’ support for 18-bit Sharp HR-TFT LCD or compatible interface.
All the necessary signals are provided on the 40-pin LCD connector H1 and the 16-pin LCD
connector H2. For connection information, refer to Table 5-1: “LCD Signal Connector
(H1)” on page 15 and Table 5-2: “Extended LCD Signal Connector (H2)” on page 17.
6.7.1 Direct LCD Connector
The direct LCD Connector (H1) provides all LCD panel signals required for Active Matrix
TFT and Passive LCD panels. These signals are buffered to either a 3.3V level or a 5.0V
level depending on the setting of JP3. See Table 3-2: “Jumper Summary” on page 9.

Technical Description
20 Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board
Rev. 3.1
6.7.2 Extended LCD Connector
The S1D13A04 directly supports Sharp 18-bit HR-TFT and compatible panels. The
extended LCD connector (H2) provides the extra signals required to support these panels.
The signals on this connector are provided directly from the S1D13A04 without any
buffering and are 3.3V signals.
6.8 USB Support
The S1D13A04 USB controller provides a Revision 1.1 compliant USB client. The
S1D13A04 acts as a USB device and connects to an upstream hub or USB host through
connector J1 on the S5U13A04B00C evaluation board. Clamping diodes have been added
to protect the USB bus from ESD and shorting.
6.8.1 USB IRQ Support
The S1D13A04 supports interrupts through output pin, IRQ. This interrupt can be used to
support interrupts from the USB client of the S1D13A04. The S5U13A04B00C evaluation
board supports this capability by connecting IRQ to the PCI interrupt INTA# of the PCI slot
that the S5U13A04B00C evaluation board is connected to.