FLY SP-770 User manual

SP-770 AS Manual
(GSM/GPRS Cellular Phone)
SKYSPRING & VITELCOM

CONTENTS
SECTION1. SP-770 PRODUCT OVERVIEW
1. RF Transceiver Part
1.1 Introduction
1.1.1 Features
1.1.2 Applications
1.1.3 General Description
1.1.4 MT6120 Function Block Diagram
1.2 Functional Description
1.2.1 Receiver
1.2.2 Transmitter
1.2.3 TX VCO
1.2.4 Frequency Synthesizer
1.2.4.1 Synthesizer System Description
1.2.4.2 Synthesizer Frequency Programming for RX Mode
1.2.4.3 Synthesizer Frequency Programming for TX Mode
1.2.4.4 Digital Calibration Loop
1.2.4.5 Fast-Acquisition System
1.2.4.5 Voltage Control Crystal Oscillator
1.2.4.6 Regulator
2. BASEBAND Part
2.1 Introduction
2.1.1 Platform
2.1.2 Memory
2.1.3 Multi-media
2.1.4 Connectivity and Storage
2.1.5 Audio
2.1.6 Radio
2.1.7 Debug function
2.1.8 Power Management
2.1.9 Package
2.2 Platform Features
2.2.1 General
2.2.2 MCU subsystem
2.2.3 External Memory Interface
2.2.4 User Interface
2.2.5 Security
2.2.6 Connectivity
2.2.7 Power management
2.2.8 Test and Debug
2.3 Modem Feature

2.3.1 Radio Interface and Baseband Front End
2.3.2 Voice and Modem Codec
2.3.3 Voice interface and Voice Front End
2.4 Multi-media Features
2.4.1 LCD/NAND Flash Interface
2.4.2 LCD Controller
2.4.3 Image serial Processor
2.4.4 Graphic Compression
2.4.5 JPEG Decoder
2.4.6 JPEG Encoder
2.4.7 Image Data Processing
2.4.8 MPEG-4/H.263. CODEC
2.4.9 TV-OUT
2.4.10 2D Accelerator
2.4.11 Audio Codec
2.4.12 Audio Interface and Audio Front End
2.5 General Description
3. Power Management System
3.1. Feature
3.2. Application
3.3. General Description
3.4. Detailed Description Overview
3.4.1 Low Dropout Regulator ( LDOs) and Reference
3.4.2 Digital Core LDO (Vcore)
3.4.3 Digital IO LDO (Vio)
3.4.4 Analog LDO ( Va )
3.4.5 TCXO LDO (Vtcxo)
3.4.6 RTC LDO (Vrtc)
3.4.7 Memory LDO (Vm)
3.4.8 SIM LDO (Vsim)
3.4.9 Reference Voltage Output (Vref)
3.4.10 SIM Card Interface
3.4.11 Vibrator, Alerter, LED Switches
3.5 Power Sequence and Protection Logic
3.5.1 Under voltage Lockout (UVLO)
3.5.2 Deep Discharge Lockout (DDLO)
3.5.3 Reset
3.5.4 Over temperature Protection
3.5.5 Battery Charger
4. POWER AMPLIFIER FOR GSM850 / DCS1800 / PCS1900
4.1 Block Diagram and Description

5. EXTERNAL DEVICE PART
5.1 External memory
5.1.1 Feature
5.1.2 Block Diagram & Description
5.2 Parallel memory
5.2.1 Feature
5.2.2 Block Diagram & Description
5.3 LCD Module
5.3.1 Feature
5.3.2 Block Diagram & Description
5.4 CAMERA IMAGE SENSOR
5.4.1 Block Diagram & Description
SECTION2. SCHEMATIC LAYOUT
1. MAIN PART SCHEMATIC LAYOUT
1.1 BASEBAND PART
1.2 MMI PART
1.3 RF PART
2. MAIN-KEY PART SCHEMATIC LAYOUT
3. LCD SCHEMATIC LAYOUT
SECTION3. PCB LAYOUT
1. MAIN PCB
1.1 Location Map of Main PCB Top
1.2 Location Map of Main PCB Bottom
2. MAIN-KEY PCB
2.1 Location Map of Main KEY PCB Top
2.2 Location Map of Main KEY PCB Bottom
3. LCD PCB
SECTION4. MECHANICAL ASSEMBLY

SECTION5. ALIGNMENT PROCEDURE
1. RECOMMENDED TEST EQUIPMENT
2. CONNECTION OF TEST EQUIPMENT
3. LOGIC PART TROUBLESHOOTING
4. RF PART TROUBLESHOOTING
SECTION6. EQUIPMENT REPARE PROCEDURE
1. No Power On with Battery Applied
2. LCD display and backlight error
3. Key pushing error and LED not in operation
4. Vibrator not in operation
5 MP3 Play not in operation
6. Camera Play not in operation.
7. FM Radio Play Error
8 Charging error
9. Bluetooth error
10. GSM RX/TX Power
SECTION7. How to use Flash Tool Manual
1. Introduction
2. Operating Environment
3. Installation
4. Setting.
5. Downloading
SECTION8. How to use Meta Tool Manual
1. Introduction
2. Operating Environment
3. Installation
4. Settings.
5. How to make the back up NVRAM data (system parameters)
6. How to restore the back up NVRAM data into target.

SECTION1. SP 770 PRODUCT OVERVIEW

1. RF Transceiver Part
1.1 Introduction
1.1.1 Feature
Receiver
- Very low IF architecture
- Tri- band differential input LNAs
- Quadrature RF mixers
- Fully integrated channel filter
- More than 100 dB gain
- More than 110 dB control range
- Image-reject down conversion to baseband
Transmitter
- Precision IQ modulator
- Translation loop architecture
- Fully integrated wideband TX VCO
- Fully integrated TX loop filter
Frequency Synthesizer
- Single integrated, fully programmable fractional-N synthesizer
- Fully integrated wideband RF VCO
- Fast settling time suitable for multi-slot GPRS application
Voltage Control Crystal Oscillator (VCXO)
- 26 MHz crystal oscillator capable of supporting 13MHz / 26 MHz output clock
- Programmable capacitor array for coarse tuning
- Internal varactor for fine tuning
Regulators
- Built-in low-noise, low-dropout (LDO) regulators
Low power consumption
QFN (Quad Flat Non-lead) Package 56-pin SMD
3-wire serial interface
MT6120 is fabricated using a 0.35 µm BiCMOS process
1.1.2 Applications
GSM 850 / PCS 1900 dual -band handsets
GSM 850 / DCS 1800 / PCS 1900 triple-band handsets
1.1.3 General Description
MT6120 is a highly integrated RF transceiver IC for multi-band Global Systems for
Mobile communication (GSM) and General Packet Radio Service (GPRS) cellular system
applications. The MT6120 includes four LNAs, two RF quadrature mixers, an integrated
channel filter, programmable gain amplifiers (PGA), an IQ demodulator for the receiver,
a precision IQ modulator with offset PLL for the transmitter, two internal TXVCOs, a
VCXO, on-chip regulators, and a fully programmable sigma-delta fractional-N
synthesizer with an on-chip RF VCO. The MT6120 also includes control circuits to
enable different operating modes. The device is housed in a 56-pin QFN SMD package

with a down set paddle for additional grounding .A functional block diagram of the
MT6120 and its pin assignment are shown in Figure 1.
1.1.4 MT6120 Function Block Diagram
Figure 1 MT6120 Function Block Diagram

1.2 Functional Description
1.2.1 Receiver
The receiver section of MT6120 includes Tri-band low noise amplifiers (LNAs), RF
quadrature mixers, an on-chip channel filter, Programmable Gain Amplifiers (PGAs),
quadrature second mixers, and a final low-pass filter. The very low-IF MT6120 uses
image-rejection mixers and filters to eliminate interference. With accurate RF
quadrature signal generation and mixer matching techniques, the image rejection of the
MT6120 can reach 35 dB for all bands. The fully integrated channel filters rejects
interference, blocking signals, and images without any external components Compared
to a direct conversion receiver (DCR), MT6120’s very low-IF architecture improves
the blocking rejection, AM suppression, as well as the adjacent channel interference
performance. Moreover, the very low-IF architecture eliminates the need for
complicated DC offset calibration that is necessary in a DCR architecture. In addition,
the common-mode balance requirement of the SAW filter input is relaxed. The
MT6120 provides the analog IQ baseband output without any extra frequency
conversion components.
The MT6120 includes Three differential LNAs for GSM 850 (869 MHz – 893 MHz),
DCS 1800 (1805 MHz-1880 MHz) and PCS 1900 (1930 MHz –1990 MHz). The
differential inputs are matched to 200 Ω SAW filters using LC networks. The gain of
the LNAs can be controlled either high or low for an additional 35 dB dynamic range
control. Following the LNAs are the image-rejection quadrature RF mixers that down-
convert the RF signal to the IF frequency. No external components are needed at the
output of the RF mixers.
The IF signal is then filtered and amplified through an image-rejection filter and a PGA.
The multi-stage PGA is implemented between filtering stages to control the gain of the
receiver. With 2 dB gain steps, a 78 dB dynamic range of the PGA ensures a proper
signal level for demodulation. The quadrature 2nd mixers are provided on-chip to
down convert IF signal to baseband in an analog differential IQ format.
1.2.2 Transmitter
The MT6120 transmitter section consists of two on-chip TX VCOs, buffer amplifiers, a
down-converting mixer, a quadrature modulator, an analog phase detector (PD) and a
digital phase frequency detector (PFD), each with a charge pump output and on chip
loop filter. The dividers and loop filters are used to achieve the desired IF frequency
from the down-conversion mixer and quadrature modulator. For a given transmission
channel, the transmitter will select one of the two different TX reference dividing
numbers. These built-in components, along with an internal voltage controlled
oscillator (TX VCO) and a loop filter, implement a translation loop modulator. The TX
VCO output is fed to the power amplifier (PA). A control loop, implemented externally,
is used to control the PA’s output power level.
1.2.3 TX VCO
Two power VCOs are integrated with OPLL to form a complete transmitter circuit. The
TX VCO output power is typically 9 dBm with +/- 2.5dB variation /
GSM850 bands and +8 dBm output power with +/- 2dB variation in DCS1800/

PCS1900 bands over extreme temperature conditions. Inside the chip, the VCO
differential output signals are fed into the output buffer, the OPLL input feedback
buffer, and the calibration circuit. The off chip signal is transformed into a single ended
output which needs impedance matching to 50Ωto drive the power amplifier. Like RF
VCO, the oscillation bandwidth is partitioned into 128 (or 64) sub-bands for DCS/ PCS
TX VCO to cover the process and temperature variation. Calibration process begins
after a period of programmable time when the on chip TX VCO regulator is turned on.
Total calibration time needs about 60us maximally and the frequency error after
calibration is within +/-5 MHz. For Vtune=1.2 V, the variation of kvco is about 14%
and 40% for GSM and DCS/PCS TX VCO, respectively, across the desired frequency
range.
1.2.4 Frequency Synthesizer
1.2.4.1 Synthesizer System Description
The MT6120 includes a frequency synthesizer with a fully integrated RF VCO to
generate RX and TX local oscillator frequencies. The PLL locks the RF VCO to a
precision reference frequency at 26 MHz. In order to reduce the inherent spur caused
by fractional-N synthesizers, a 3rd-order sigma-delta modulator with dithering
function is used to generate the prescaler divider number N. The prescaler is based
on a multi-modulus architecture with programmable divider numbers ranging from 64
to 127. A conventional digital-type PFD with a charge pump is used for phase
comparison in the PLL. By changing the output current of the charge pump, the phase
detector gain can be programmed from75/π µA/rad to 600/π µA/rad.
To reduce the acquisition time or to enable fast settling time for multi-slot data
services such as GPRS, a digital loop (calibration loop) along with a fast-acquisition
system are implemented in the synthesizer. Once the synthesizer is programmed, the
RF VCO is pre-set to the vicinity of the desired frequency by a digital calibration loop.
After the calibration, a fast-acquisition system is utilized for a period of time to
facilitate fast locking. Once the acquisition is done, the PLL reverts back to the normal
operation mode.
1.2.4.2 Synthesizer Frequency Programming for RX Mode
The frequency ranges of the synthesizer for RX mode are
RX mode GSM 850 1737 MHz ~ 1788 MHz
DCS 1800 1805 MHz ~ 1880 MHz
PCS 1900 1930 MHz ~ 1990 MHz.
And the divider number N can be decided by the following procedure.
1. Calculate LO frequency fVCO from RX channel frequency fCH
fVCO = 2 * fCH – 200k for GSM 850 and E-GSM 900
fVCO = fCH – 100k for DCS 1800 and PCS 1900
2. Calculate Nint and Nfrac
N = 64 + Nint + Nfrac/5200 = fVCO/26M Nint and Nfrac are integers
0 ≤ Nfrac < 5200
3. Use the binary equivalents of Nint and Nfrac to program registers CW1-N_INT
and CW1-N_FRA.

1.2.4.3 Synthesizer Frequency Programming for TX Mode
The frequency ranges of the synthesizer for TX mode are
TX mode GSM850 1813 MHz ~ 1868 MHz
DCS1800 1881 MHz ~ 2008 MHz
PCS1900 2035 MHz ~ 2149 MHz
And the divider number N can be decided by the following procedure.
1. Set the divider ratio D1 of TX reference divider = 11
2. Calculate LO frequency fVCO from TX channel frequency fCH
fVCO = 2 * D1 * fCH / (D1-1) for GSM850
fVCO = D1 * fCH / (D1-1) for DCS1800 and PCS1900
3. Calculate Nint and Nfrac
N = 64 + Nint + Nfrac/5200 = fVCO/26M Nint and Nfrac are integers
0 ≤ Nfrac < 5200
4. If Nfra < 400 or Nfra > 4800, re-set D1 = 9 and repeat Step 2 and 3 to get new
Nint and Nfrac.
5. Use the binary equivalents of Nint and Nfrac to program registers CW1-N_INT
and CW1-N_FRA.
1.2.4.4 Digital Calibration Loop
The MT6120 uses a digital calibration technique to reduce the PLL settling time.
Once the RF synthesizer is programmed through a 3-wire serial interface, the
calibration loop is activated. The main function of the calibration loop is to preset
the RF VCO to the vicinity of the desired frequency quickly and correctly, thus
aiding the PLL to settle faster.
On the other hand, since a large portion of initial frequency error is dealt with by
the integrated calibration loop, the overall locking time can be drastically reduced,
irrespective of the desired frequency.
1.2.4.5 Fast-Acquisition System
After the digital calibration loop presets the RFVCO, the RF synthesizer reverts to
the PLL operation and a fast-acquisition system is activated. For faster settling, the
charge pump current is set to a higher current than normal setting for a period of
time, typically, 20 µs or 60 µs.
1.2.4.5 Voltage Control Crystal Oscillator
Voltage Control Crystal Oscillator (VCXO) consists of an amplifier, a buffer, and a
programmable capacitor array. The VCXO provides the MT6120 with a selectable
reference frequency of either 13 MHz or 26 MHz.
The amplifier is designed to be in series resonance with a standard 26 MHz crystal.
The crystal is connected from the input pin XTAL of amplifier to ground through a
series load capacitance. The buffer provides a typical 600 mVpp voltage swing at
either 13 MHz or 26 MHz. It is designed to drive a tuned load to improve harmonic
contents and reduce the oscillator current consumption. The capacitor array, from
0.0625 pF to 4 pF in steps of 0.0625 pF, is used to shunt the series load capacitor
for coarse tuning and remove any fixed offsets due to crystal manufacturing
variations. An internal varactor that provides fine tuning combines with the

capacitor array. As an alternative, the reference frequency can be provided by an
external 26 MHz VCTCXO module. When pin VCXOCXR is tied to the VCCVCXO
supply, the XTAL pin will accept an external signal. Furthermore, the VCXO control
pin can be tied to VCCVCXO to prevent the current leakage during the sleep mode
operation.
1.2.4.6 Regulator
The MT6120 internal regulators provide low noise, stable, temperature and process
independent supply voltages to critical blocks in the transceiver. An internal P-
channel MOSFET pass transistor is used to achieve a low dropout (LDO) voltage of
less than 150 mV in all regulators.

2. BASEBAND Part
2.1 Introduction
MT6228 is a feature-rich extremely powerful single-chip solution for high–end
GSM/GPRS mobile phones. Based on 32 bit ARM7EJ-STM RISC processor, MT6228’s
superb processing power along with high bandwidth architecture and dedicated
hardware support provides an unprecedented platform for high performance GPRS
Class 12 MODEM and leading-edge multimedia applications. Overall, MT6228 presents
a revolutionary platform for multimedia-centric mobile devices.
Typical application diagram is shown in Figure 2
Figure2 Typical application of MT6228

2.1.1 Platform
MT6228 is capable of running the ARM7EJ-Stm RISC processor at up to 104Mhz, thus
providing fast data processing capabilities. In addition to high clock frequency,
separate CODE and DATA caches are also added to further improve the overall system
efficiency.
For large amount of data transfer, high performance DMA (Direct Memory Access) with
hardware flow control is implemented, which greatly enhances the data movement
speed while reducing MCU processing load.
Targeted as a media-rich platform for mobile applications, MT6228 also provides
hardware security digital rights management for copyright protection. For future
safeguarding, and to protect manufacture’s development investment, hardware flash
content protection is also provided to prevent unauthorized porting of software load.
2.1.2 Memory
To provide the greatest capacity for expansion and maximum bandwidth for data
intensive applications such as multimedia features. MT6228 supports up to 4 external
state-of-the art devices through its 8/16-bit host interface.
High performance devices such as Mobile RAM, and Cellular RAM are supported for
maximum bandwidth.
Traditional devices such as burst/page mode Flash, page mode SRAM, and Pseudo
SRAM are also supported. For greatest compatibility, the memory interface can also be
used to connect to legacy devices such as Color/Parallel LCD, and multi-media
companion chip are all supported through this interface. To minimize power
consumption and ensure low noise, this interface is designed for flexible I/O voltage
and allows lowering of supply voltage down to 1.8V. The driving strength is
configurable for signal integrity adjustment. The date bus also employs retention
technology to prevent the bus from floating during turn over.
2.1.3 Multi-media
The MT6228 multi-media subsystem provides connection to CMOS image sensor and
supports resolution up to 3M pixels. With its advanced image signal and data
processing technology, MT6228 allows efficient processing of image and data. It also
has built-in JPEG CODEC and MPEG-4 CODEC, thus enabling real-time recording and
playback of high-quality images and video. Hardware MPEG4 accelerator supports
playback in VGA mode at 15fps, and encoding in CIF at 15fps. Videophone functionality
is also provided. Moreover, high quality de-blocking filter is provided to remove
blocking artifacts in video playback. GIF decoder and PNG decoder are implemented as
well for fast image decoding. MT6228 supports TV-OUT capability, thus allowing the
mobile handset to connect to TV screen via NTSC/PAL connections.
In addition to advanced image and video features, MT6228 also utilizes high resolution
DAC, digital audio, and audio synthesis technology to provide superior audio features
for all future multi-media needs.

2.1.4 Connectivity and Storage
In order to take advantage of its incredible multimedia strengths, MT6228 incorporates
myriads of advanced connectivity and storage options for data storage and
communication. MT6228 supports UART, Fast IrDA. USB 1.1 Full speed OTG, SDIO,
Bluetooth and WIFI Interface, and MMC/SD/MS/MS Pro storage systems, All these
interfaces provide MT6228 users with the highest degree of flexibility in implementing
solutions suitable for the targeted application. To achieve a complete user interface,
MT6228 also brings together all the necessary peripheral blocks for multi-media
GSS/GPRS phone. The peripheral blocks includes the Keypad Scanner with the
capability to detect multiple key presses, SIM Controller, Alerter, Real Time Clock,
PWM, Serial LCD controller, and General Purpose Programmable I/Os.
Furthermore, to provide more configuration and bandwidth for multi-media products,
and additional 18-bit parallel interface is incorporated, This interface enables
connection to LCD panels as well as connection to NAND flash devices for additional
multi-media data storage.
2.1.5 Audio
Using a highly integrated mixed-signal Audio Front-End, the MT6228 architecture
allows for easy audio interfacing with direct connection to the audio transducers. The
audio interface integrates D/A and A/D Converters for Voice band, as well as high
resolution Stereo D/A Converters for Audio band. In addition, MT6228 also provides
Stereo Input and Analog Mux.
MT6228 supports AMR codec to adaptively optimize speech and audio quality.
Moreover, HE-AAC codec is implemented to deliver CD-quality audio at low bit rates.
On the whole, MT6228's audio features provide a right solution for multi-media
applications.
2.1.6 Radio
MT6228 integrates a mixed-signal Baseband front-end in order to provide a well-
organized radio interface with flexibility for efficient customization. It contains gain and
offset calibration mechanisms, and filters with programmable coefficients for
comprehensive compatibility control on RF modules. This approach also allows the
usage of a high resolution D/A Converter for controlling VCXO or crystal, thus
reducing the need for expensive TCVCXO. MT6228 achieves great MODEM
performance by utilizing 14-bit high resolution A/D Converter in the RF downlink path.
Furthermore, to reduce the need for extra external current-driving component, the
driving strength of some BPI outputs is designed to be configurable
2.1.7 Debug Function
The JTAC interface enables in-circuit debugging of software program with the
ARM7EJ-S core. With this standardized debugging interface, the MT6228 provides
developers with a wide set to options in choosing ARM development kits from different
third party vendors.

2.1.8 Power Management
The MT6228 offers various low-power features to help reduce system power
consumption. These features include Pause Mode of 32KHz clocking at Standby State,
Power Down Mode for individual peripherals, and Processor Sleep Mode. In addition,
Mt6228 is also fabricated in advanced low leakage CMOS process, hence providing an
overall ultra low leakage solution.
2.1.9 Package
The MT6228 device is offered in a 13mm x 13mm, 314-ball, 0.65mm pitch,
TFBGA package.
2.2 Platform Features
2.2.1 General
Integrated voice-band, audio-band and base-band analog front ends.
TFBGA 13mm X 13mm, 314-ball, 0.65 mm pitch package
2.2.2 MCU Subsystem
-ARM7EJ-s 32-bit RISC processor
-High performance multi-layer AMB bus
-Java hardware acceleration for fast Java-based games and applets
-Operating frequency: 26/52/104 Mhz
-Dedicated DMA bus
-14DMA channels
-1M bits on-chip SRAM
-256k bits CODE cache
-64K bits DATA cache
-On-chip boot ROM for Factory Flash programming
-Watchdog timer for system crash recovery
-3 sets of General Purpose Timer
-Circuit Switch Data coprocessor
-Division coprocessor
-PPP Framer coprocessor
2.2.3 External Memory Interface
-Supports up to 4 external devices
-Supports 8-bit or 16-bit memory components with maximum size of up to 64M byte
each
-Supports Mobile RAM, and Cellular RAM
-Supports Flash and SRAM/PSRAM with Page Mode or Burst Mode
-Industry standard Parallel LCD Interface
-Supports multi-media companion chips with 8/16 bits data width
-Flexible I/O voltage of 1.8V ~ 2.8V for memory interface
-Configurable driving strength for memory interface

2.2.4 User Interfaces
-6-row X 7-column keypad controller with hardware scanner
-Supports multiple key presses for gaming
-SIM/USIM Controller with hardware T=0/T=1 protocol control
-Real Time Clock (RTC) operating with a separate power supply
-General Purpose I/Os (GPIOs)
-2 sets of Pulse With Modulation (PWM) Output
-Alerter Output with Enhanced PWM or PDM
-8 external interrupt lines
2.2.5 Security
-Cipher : supports AES, DES/3DES
-Hash : supports MD5, SHA-1
-Supports security key and 20 bit chip unique ID
2.2.6 Connectivity
-3 UARTS with hardware flow control and speed up to 921600 bps
-IrDA modulator/demodulator with hardware framer. Supports SIR/MIR/FIR operating
speeds
-Full-speed USB 1.1 OTG capability. Supports device mode, Limited host mode, and
dual-role OTG mode.
-Multi Media card/secure Digital Memory Card/Memory stick Pro host controller with
flexible I/O voltage Power
-support SDIO interface for SDIO peripherals as well as WIFI connectivity
-DAI/PCM and 12S interface for Audio application
2.2.7 Power Management
-Power Down Mode for analog and digital circuits
-Processor Sleep Mode
-Pause Mode of 32KHZ clocking at standby state
-7 channel Auxiliary 10-bit A/D Converter for charger and battery monitoring and
photo sensing
2.2.8 Test and Debug
-Built –in digital and analog loop back modes for both Audio and Baseband Front-End
-DAI port complying with GSM Rec.11.10
-JTAG port for debugging embedded MCU
2.3 MODEM Features
2.3.1 Radio Interface and Baseband front End
-GSMK modulator with analog I and Q channel outputs
-10-bit D/A Converter for uplink baseband I and Q signal
-14-bit high resolution A/D converter for downlink baseband I and Q signal.
-Calibration mechanism of offset and gain mismatch for baseband A/D Converter and
D/A Converter

-10-bit D/A Converter for Automatic Power control.
-13-bit high resolution D/A Converter for Automatic Frequency Control
-Programmable Radio RX filter
-2 Channels Baseband Serial Interface(BSI)with 3-wire control
-Bi-directional BSI interface. RF chip resister read access with 3-wire or 4-wire
interface
-10-pin baseband Parallel Interface (BSI) with programmable driving strength
Multi-band support
2.3.2 Voice and Modem CODEC
-Dial tone generation
-Voice memo
-Noise Reduction
-Echo Suppression
-Advanced Sidetone Oscillation Reduction
-Digital sidetone generator with programmable gain
-Two programmable acoustic compensation filters
-GSM/GPRS quad vocoders for adaptive multi rate (AMR), enhanced full rate(EFR),full
rate(FR) and half rate(HR).
-GSM channel coding, equalization and A5/1 and A5/2 ciphering
-GPRS GEA1 and GEA2 ciphering
-Programmable GSM/GPRS Modem
-Packet Switched Data with CS1/CS2/CS3/CS4 coding schemes
-GSM Circuit Switch Data
-GPRS Class 12
2.3.3 Voice interface and Voice Front End
-Two microphone inputs sharing one low noise amplifier with programmable
- Gain control(AGC) mechanism.
-Voice power amplifier with programmable
-Second order Sigma-Delta A/D Converter for voice uplink path
-D/A Converter for voice downlink path
-Supports half-duplex hands-free operation
-Compliant with GSM 03.50
2.4 Multi-Media Feature
2.4.1 LCD/NAND flash Interface
-Dedicated Parallel Interface supports 3 external devices with 8/16 bit NAND flash
Interface 8/9/16/18 bit Parallel Interface, and Serial interface for LCM
-Built –in NAND Flash controller with 1-bit ECC for mass storages.
2.4.2 LCD Controller
-Supports simultaneous connection to up to 3 parallel LCD and 2 Serial LCD module
-Supports LCM format: RGB332, RGB444, RGB565, RGB666, RGB888.
-Supports LCD module with maximum resolution up to 800*600 at 24bpp.
-Per pixel alpha channel.
-True color engine

-Supports hardware display rotation.
-Capable combining display memories with up to 6 blending layers.
2.4.3 Image Signal Processor
- 8/10 bit Bayer format image input.
-Capable of processing image of size up to 3m pixels.
-Color Correction Matrix.
-Gamma Correction
-Automatic Exposure Control
-Automatic
2.4.4 Graphic Compression
-GIF Decoder
-PNG Decoder
2.4.5 JPEG Decoder
-ISO/IEC 10918-1 JPEG Baseline and Progressive modes
-Supports all possible YUV formats, including grayscale format
-Supports a;; DC/AC Huffuman table parsing
-Supports all quantization table parsing
-Supports restart interval
-supports SOS, DHT, DQT and DRI marker parsing
-IEEE Std 1180-1990 IDCT Standard Compliant
-Supports progressive image processing to minimize storage space requirement
-Supports reload-able DMA for VLD stream
2.4.6 JPEG Encoder
-ISO/IEC 10918-1 JPEG baseline mode
-ISO/IEC 10918-2 Compliance
-Supports YUV422 and YUV420 and grayscle formats
-Supports JFIF
-Standard DC and AC Huffman tables
-Provides 4 levels of encode quality
-Support continuous shooting
2.4.7 Image Data Processing
-Support Digital Zoom
-Support RGB888/565, YUV444 image processing
-High throughput hardware scaler, Capable of tailoring image to arbitrary size
-Horizontal scaling in averaging method
-Simultaneous scaling for MPEG-4 encode and LCD display
-YUV and RGB color space conversion
-Pixel format transform
-Boundary padding
-Pixel processing: hue/saturation/intensity/color adjustment, Gamma correction and
grayscale/invert/sepia-tone effects
-Hardware accelerated image editing

-Photo frame capability
-RGB thumbnail data output
2.4.8 MPEG-4/H.263 CODEC
-Hardware Video CODEC
-ISO/IEC 14496-2 simple profile:
decode @ level 0/1/2/3
encode @ level 0
-ITU-T H.263 profile 0 @ level 10
-Max decode speed is VGA @ 15fps
-Max encode speed is CIF @ 15fps
-Support VGA mode encoding
-Horizontal and Vertical De-blocking filter in video playback
-Encoder resync marker and HEC
-Supported visual tools for decoder: I-VOP, P-VOP, AC/DC prediction, 4-MV, Error
Resilience, Short Header
-Error Resilience for decoder: Slice
-Resynchronization, Data Partitioning, Reversible VLC
-Supported visual tools for encoder: I-VOP, P-VOP, Half-pel, DC prediction, -
Unrestricted MV, Reversible VLC, Short Header
-Supports encoding motion vector of range up to -64/+63.6 pixels
-HE-AAC decode support
-AAC/AMR/WB-AMR audio decode support
-AMR/WB-AMR audio encode support
2.4.9 TV-OUT
-Supports NTSC/PAL formats (interlaced mode)
-10 bit video DAC with 2x oversampling
-Support one composite video output
2.4.10 2D Accelerator
-Support 32-bpp ARGB8888 and 24bpp RGB888 and 16-bpp RGB565 and 8-bpp index
color modes
-Supports SVG Tiny
-Rectangle gradient fill
-BitBlt: muti-Bitblt with7 rotation
-Alpha blending wit 7 rotation
-Line drawing: normal line, dotted line, anti-aliasing
-Circle drawing
-Bezier curve drawing
-Triangle flat fill
-Font caching: normal font, Italic front
-Command queue with max depth of 2047
2.4.11 Audio CODEC
-Support HE-AAC codec decode