Freescale Semiconductor i.MX 6SoloLite Linux User manual

i.MX 6SoloLite Linux Reference
Manual
Document Number: IMXL6SLRM
Rev L3.0.35_4.1.0, 09/2013

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Contents
Section number Title Page
Chapter 1
About This Book
1.1 Audience.........................................................................................................................................................................17
1.1.1 Conventions.......................................................................................................................................................17
1.1.2 Definitions, Acronyms, and Abbreviations........................................................................................................17
Chapter 2
Introduction
2.1 Overview.........................................................................................................................................................................21
2.1.1 Software Base....................................................................................................................................................21
2.1.2 Features..............................................................................................................................................................22
Chapter 3
Machine Specific Layer (MSL)
3.1 Introduction.....................................................................................................................................................................27
3.2 Interrupts (Operation).....................................................................................................................................................28
3.2.1 Interrupt Hardware Operation............................................................................................................................28
3.2.2 Interrupt Software Operation.............................................................................................................................28
3.2.3 Interrupt Features...............................................................................................................................................29
3.2.4 Interrupt Source Code Structure........................................................................................................................29
3.2.5 Interrupt Programming Interface.......................................................................................................................29
3.3 Timer...............................................................................................................................................................................30
3.3.1 Timer Software Operation.................................................................................................................................30
3.3.2 Timer Features...................................................................................................................................................30
3.3.3 Timer Source Code Structure.............................................................................................................................31
3.3.4 Timer Programming Interface............................................................................................................................31
3.4 Memory Map..................................................................................................................................................................31
3.4.1 Memory Map Hardware Operation....................................................................................................................31
3.4.2 Memory Map Software Operation.....................................................................................................................31
3.4.3 Memory Map Features.......................................................................................................................................31
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3.4.4 Memory Map Source Code Structure................................................................................................................32
3.4.5 Memory Map Programming Interface...............................................................................................................32
3.5 IOMUX...........................................................................................................................................................................32
3.5.1 IOMUX Hardware Operation............................................................................................................................33
3.5.2 IOMUX Software Operation..............................................................................................................................33
3.5.3 IOMUX Features................................................................................................................................................34
3.5.4 IOMUX Source Code Structure.........................................................................................................................34
3.5.5 IOMUX Programming Interface........................................................................................................................34
3.5.6 IOMUX Control Through GPIO Module..........................................................................................................34
3.5.6.1 GPIO Hardware Operation.................................................................................................................35
3.5.6.1.1 Muxing Control.................................................................................................................35
3.5.6.1.2 PULLUP Control..............................................................................................................35
3.5.6.2 GPIO Software Operation (general)..................................................................................................35
3.5.6.3 GPIO Implementation........................................................................................................................35
3.5.6.4 GPIO Source Code Structure.............................................................................................................36
3.5.6.5 GPIO Programming Interface............................................................................................................36
3.6 General Purpose Input/Output(GPIO)............................................................................................................................36
3.6.1 GPIO Software Operation..................................................................................................................................36
3.6.1.1 API for GPIO.....................................................................................................................................37
3.6.2 GPIO Features....................................................................................................................................................37
3.6.3 GPIO Module Source Code Structure................................................................................................................37
3.6.4 GPIO Programming Interface 2.........................................................................................................................38
Chapter 4
Smart Direct Memory Access (SDMA) API
4.1 Overview.........................................................................................................................................................................39
4.1.1 Hardware Operation...........................................................................................................................................39
4.1.2 Software Operation............................................................................................................................................39
4.1.3 Source Code Structure.......................................................................................................................................40
4.1.4 Menu Configuration Options.............................................................................................................................41
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4.1.5 Programming Interface......................................................................................................................................41
4.1.6 Usage Example..................................................................................................................................................41
Chapter 5
Electrophoretic Display Controller (EPDC) Frame Buffer Driver
5.1 Introduction.....................................................................................................................................................................43
5.2 Hardware Operation........................................................................................................................................................44
5.3 Software Operation.........................................................................................................................................................44
5.3.1 EPDC Frame Buffer Driver Overview...............................................................................................................44
5.3.2 EPDC Frame Buffer Driver Extensions.............................................................................................................45
5.3.3 EPDC Panel Configuration................................................................................................................................45
5.3.3.1 Boot Command Line Parameters.......................................................................................................46
5.3.4 EPDC Waveform Loading.................................................................................................................................47
5.3.4.1 Using a Default Waveform File.........................................................................................................47
5.3.4.2 Using a Custom Waveform File.........................................................................................................48
5.3.5 EPDC Panel Initialization..................................................................................................................................48
5.3.6 Grayscale Framebuffer Selection.......................................................................................................................49
5.3.7 Enabling An EPDC Splash Screen.....................................................................................................................49
5.4 Source Code Structure ...................................................................................................................................................50
5.5 Menu Configuration Options..........................................................................................................................................51
5.6 Programming Interface...................................................................................................................................................51
5.6.1 IOCTLs/Functions.............................................................................................................................................52
5.6.2 Structures and Defines.......................................................................................................................................55
Chapter 6
Sipix Display Controller (SPDC) Frame Buffer Driver
6.1 Introduction.....................................................................................................................................................................57
6.2 Hardware Operation........................................................................................................................................................58
6.3 Software Operation.........................................................................................................................................................58
6.3.1 SPDC Frame Buffer Driver Overview...............................................................................................................58
6.3.2 SPDC Frame Buffer Driver Extensions.............................................................................................................59
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Section number Title Page
6.3.3 SPDC Panel Configuration................................................................................................................................59
6.3.3.1 Boot Command Line Parameters.......................................................................................................60
6.3.4 SPDC Waveform Loading.................................................................................................................................60
6.3.4.1 Using a Default Waveform File.........................................................................................................61
6.3.4.2 Using a Custom Waveform File.........................................................................................................61
6.3.5 SPDC Panel Initialization..................................................................................................................................62
6.3.6 Grayscale Framebuffer Selection.......................................................................................................................62
6.4 Source Code Structure ...................................................................................................................................................63
6.5 Menu Configuration Options..........................................................................................................................................64
6.6 Programming Interface...................................................................................................................................................64
6.6.1 IOCTLs/Functions.............................................................................................................................................65
6.6.2 Structures and Defines.......................................................................................................................................68
Chapter 7
Pixel Pipeline (PxP) DMA-ENGINE Driver
7.1 Introduction.....................................................................................................................................................................71
7.2 Hardware Operation........................................................................................................................................................71
7.3 Software Operation.........................................................................................................................................................71
7.3.1 Key Data Structs................................................................................................................................................71
7.3.2 Channel Management........................................................................................................................................72
7.3.3 Descriptor Management.....................................................................................................................................72
7.3.4 Completion Notification....................................................................................................................................72
7.3.5 Limitations.........................................................................................................................................................73
7.4 Menu Configuration Options..........................................................................................................................................73
7.5 Source Code Structure....................................................................................................................................................73
Chapter 8
ELCDIF Frame Buffer Driver
8.1 Introduction.....................................................................................................................................................................75
8.2 Hardware Operation........................................................................................................................................................75
8.3 Software Operation.........................................................................................................................................................75
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8.4 Menu Configuration Options..........................................................................................................................................76
8.5 Source Code Structure....................................................................................................................................................76
Chapter 9
Graphics Processing Unit (GPU)
9.1 Introduction.....................................................................................................................................................................77
9.1.1 Driver Features...................................................................................................................................................77
9.1.1.1 Hardware Operation...........................................................................................................................77
9.1.1.2 Software Operation............................................................................................................................78
9.1.1.3 Source Code Structure ......................................................................................................................78
9.1.1.4 Library Structure ...............................................................................................................................78
9.1.1.5 API References..................................................................................................................................80
9.1.1.6 Menu Configuration Options.............................................................................................................80
Chapter 10
High-Definition Multimedia Interface (HDMI)
10.1 Introduction.....................................................................................................................................................................81
10.2 Software Operation.........................................................................................................................................................81
10.2.1 Hotplug Handling and Video Mode Changes....................................................................................................81
10.3 Source Code Structure....................................................................................................................................................82
10.3.1 Linux Menu Configuration Options...................................................................................................................83
10.4 Unit Test..........................................................................................................................................................................83
10.4.1 Video..................................................................................................................................................................83
10.4.2 Audio..................................................................................................................................................................84
Chapter 11
X Windows Acceleration
11.1 Introduction.....................................................................................................................................................................85
11.2 Hardware Operation........................................................................................................................................................85
11.3 Software Operation.........................................................................................................................................................85
11.3.1 X Windows Acceleration Architecture..............................................................................................................86
11.3.2 i.MX 6 Driver for X-Windows System..............................................................................................................87
11.3.3 xorg.conf for i.MX 6..........................................................................................................................................89
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11.3.4 Setup X-Windows System Acceleration............................................................................................................90
Chapter 12
Camera Sensor Interface (CSI) Driver
12.1 Hardware Operation........................................................................................................................................................93
12.2 Software Operation.........................................................................................................................................................93
12.2.1 CSI Software Operation.....................................................................................................................................94
12.2.2 Video for Linux 2 (V4L2) APIs.........................................................................................................................94
12.2.2.1 V4L2 Capture Device........................................................................................................................94
12.2.2.2 Use of the V4L2 Capture APIs..........................................................................................................95
12.3 Source Code Structure....................................................................................................................................................95
12.4 Linux Menu Configuration Options................................................................................................................................96
12.5 Programming Interface...................................................................................................................................................96
Chapter 13
OV5640 Using parallel interface
13.1 Hardware Operation........................................................................................................................................................97
13.2 Software Operation.........................................................................................................................................................97
13.3 Source Code Structure....................................................................................................................................................98
13.4 Linux Menu Configuration Options................................................................................................................................98
Chapter 14
Low-level Power Management (PM) Driver
14.1 Hardware Operation........................................................................................................................................................99
14.1.1 Software Operation............................................................................................................................................99
14.1.2 Source Code Structure.......................................................................................................................................100
14.1.3 Menu Configuration Options.............................................................................................................................100
14.1.4 Programming Interface......................................................................................................................................101
14.1.5 Unit Test.............................................................................................................................................................101
Chapter 15
PF100 Regulator Driver
15.1 Introduction.....................................................................................................................................................................103
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15.2 Hardware Operation........................................................................................................................................................103
15.2.1 Driver Features...................................................................................................................................................104
15.3 Software Operation.........................................................................................................................................................104
15.3.1 Regulator APIs...................................................................................................................................................104
15.4 Driver Architecture.........................................................................................................................................................106
15.4.1 Driver Interface Details......................................................................................................................................107
15.4.2 Source Code Structure.......................................................................................................................................107
15.4.3 Menu Configuration Options.............................................................................................................................107
Chapter 16
CPU Frequency Scaling (CPUFREQ) Driver
16.1 Introduction.....................................................................................................................................................................109
16.1.1 Software Operation............................................................................................................................................109
16.1.2 Source Code Structure.......................................................................................................................................110
16.2 Menu Configuration Options..........................................................................................................................................110
16.2.1 Board Configuration Options.............................................................................................................................111
Chapter 17
Dynamic Voltage Frequency Scaling (DVFS) Driver
17.1 Introduction.....................................................................................................................................................................113
17.1.1 Operation............................................................................................................................................................113
17.1.2 Software Operation............................................................................................................................................113
17.1.3 Source Code Structure.......................................................................................................................................114
17.2 Menu Configuration Options..........................................................................................................................................114
17.2.1 Board Configuration Options.............................................................................................................................114
Chapter 18
Thermal Driver
18.1 Introduction.....................................................................................................................................................................115
18.1.1 Thermal Driver Overview..................................................................................................................................115
18.2 Hardware Operation........................................................................................................................................................115
18.2.1 Thermal Driver Software Operation..................................................................................................................116
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18.3 Driver Features................................................................................................................................................................116
18.3.1 Source Code Structure.......................................................................................................................................116
18.3.2 Menu Configuration Options.............................................................................................................................116
18.3.3 Programming Interface......................................................................................................................................116
18.3.4 Interrupt Requirements......................................................................................................................................117
18.4 Unit Test..........................................................................................................................................................................117
Chapter 19
Anatop Regulator Driver
19.1 Introduction.....................................................................................................................................................................119
19.1.1 Hardware Operation...........................................................................................................................................119
19.2 Driver Features................................................................................................................................................................120
19.2.1 Software Operation............................................................................................................................................120
19.2.2 Regulator APIs...................................................................................................................................................120
19.2.3 Driver Interface Details......................................................................................................................................121
19.2.4 Source Code Structure.......................................................................................................................................121
19.2.5 Menu Configuration Options.............................................................................................................................121
Chapter 20
SNVS Real Time Clock (SRTC) Driver
20.1 Introduction.....................................................................................................................................................................123
20.1.1 Hardware Operation...........................................................................................................................................123
20.2 Software Operation.........................................................................................................................................................123
20.2.1 IOCTL................................................................................................................................................................123
20.2.2 Keeping Alive in the Power Off State...............................................................................................................124
20.3 Driver Features................................................................................................................................................................124
20.3.1 Source Code Structure.......................................................................................................................................125
20.3.2 Menu Configuration Options.............................................................................................................................125
Chapter 21
Advanced Linux Sound Architecture (ALSA) System on a Chip (ASoC) Sound Driver
21.1 ALSA Sound Driver Introduction...................................................................................................................................127
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21.2 SoC Sound Card .............................................................................................................................................................130
21.2.1 Stereo CODEC Features....................................................................................................................................130
21.2.2 Sound Card Information.....................................................................................................................................130
21.3 Hardware Operation........................................................................................................................................................131
21.3.1 Stereo Audio CODEC........................................................................................................................................131
21.4 Software Operation.........................................................................................................................................................132
21.4.1 ASoC Driver Source Architecture.....................................................................................................................132
21.4.2 Sound Card Registration....................................................................................................................................132
21.4.3 Device Open.......................................................................................................................................................133
21.4.4 Platform Data.....................................................................................................................................................133
21.4.5 Menu Configuration Options.............................................................................................................................134
21.5 Unit Test..........................................................................................................................................................................134
21.5.1 Stereo CODEC Unit Test...................................................................................................................................134
Chapter 22
SPI NOR Flash Memory Technology Device (MTD) Driver
22.1 Introduction.....................................................................................................................................................................137
22.1.1 Hardware Operation...........................................................................................................................................137
22.1.2 Software Operation............................................................................................................................................138
22.1.3 Driver Features...................................................................................................................................................138
22.1.4 Source Code Structure.......................................................................................................................................138
22.1.5 Menu Configuration Options.............................................................................................................................139
Chapter 23
MMC/SD/SDIO Host Driver
23.1 Introduction.....................................................................................................................................................................141
23.1.1 Hardware Operation...........................................................................................................................................141
23.1.2 Software Operation............................................................................................................................................142
23.2 Driver Features................................................................................................................................................................144
23.2.1 Source Code Structure.......................................................................................................................................145
23.2.2 Menu Configuration Options.............................................................................................................................145
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23.2.3 Platform Data.....................................................................................................................................................146
23.2.4 Programming Interface......................................................................................................................................146
23.2.5 Loadable Module Operations.............................................................................................................................147
Chapter 24
Inter-IC (I2C) Driver
24.1 Introduction.....................................................................................................................................................................149
24.1.1 I2C Bus Driver Overview..................................................................................................................................149
24.1.2 I2C Device Driver Overview.............................................................................................................................150
24.1.3 Hardware Operation...........................................................................................................................................150
24.2 Software Operation.........................................................................................................................................................150
24.2.1 I2C Bus Driver Software Operation...................................................................................................................150
24.2.2 I2C Device Driver Software Operation.............................................................................................................151
24.3 Driver Features................................................................................................................................................................151
24.3.1 Source Code Structure.......................................................................................................................................152
24.3.2 Menu Configuration Options.............................................................................................................................152
24.3.3 Programming Interface......................................................................................................................................152
24.3.4 Interrupt Requirements......................................................................................................................................152
Chapter 25
Enhanced Configurable Serial Peripheral Interface (ECSPI) Driver
25.1 Introduction.....................................................................................................................................................................155
25.1.1 Hardware Operation...........................................................................................................................................155
25.2 Software Operation.........................................................................................................................................................156
25.2.1 SPI Sub-System in Linux...................................................................................................................................156
25.2.2 Software Limitations..........................................................................................................................................157
25.2.3 Standard Operations...........................................................................................................................................157
25.2.4 ECSPI Synchronous Operation..........................................................................................................................158
25.3 Driver Features................................................................................................................................................................160
25.3.1 Source Code Structure.......................................................................................................................................160
25.3.2 Menu Configuration Options.............................................................................................................................160
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25.3.3 Programming Interface......................................................................................................................................160
25.3.4 Interrupt Requirements......................................................................................................................................161
Chapter 26
ARC USB Driver
26.1 Introduction.....................................................................................................................................................................163
26.1.1 Architectural Overview......................................................................................................................................163
26.2 Hardware Operation........................................................................................................................................................164
26.2.1 Software Operation............................................................................................................................................164
26.2.2 Source Code Structure.......................................................................................................................................165
26.2.3 Menu Configuration Options.............................................................................................................................166
26.2.4 Programming Interface......................................................................................................................................169
26.3 System WakeUp..............................................................................................................................................................169
26.3.1 USB Wakeup usage...........................................................................................................................................169
26.3.2 How to Enable USB WakeUp System Ability...................................................................................................169
26.3.3 WakeUp Events Supported by USB..................................................................................................................170
26.3.4 How to Close the USB Child Device Power......................................................................................................171
Chapter 27
Fast Ethernet Controller (FEC) Driver
27.1 Introduction.....................................................................................................................................................................173
27.2 Hardware Operation........................................................................................................................................................173
27.2.1 Software Operation............................................................................................................................................176
27.2.2 Source Code Structure.......................................................................................................................................176
27.2.3 Menu Configuration Options.............................................................................................................................176
27.3 Programming Interface...................................................................................................................................................177
27.3.1 Device-Specific Defines....................................................................................................................................177
27.3.2 Getting a MAC Address.....................................................................................................................................178
Chapter 28
Universal Asynchronous Receiver/Transmitter (UART) Driver
28.1 Introduction.....................................................................................................................................................................179
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28.2 Hardware Operation........................................................................................................................................................180
28.2.1 Software Operation............................................................................................................................................180
28.2.2 Driver Features...................................................................................................................................................181
28.2.3 Source Code Structure.......................................................................................................................................181
28.3 Configuration..................................................................................................................................................................182
28.3.1 Menu Configuration Options.............................................................................................................................182
28.3.2 Source Code Configuration Options..................................................................................................................183
28.3.3 Chip Configuration Options...............................................................................................................................183
28.3.4 Board Configuration Options.............................................................................................................................183
28.4 Programming Interface...................................................................................................................................................183
28.4.1 Interrupt Requirements......................................................................................................................................183
Chapter 29
Pulse-Width Modulator (PWM) Driver
29.1 Introduction.....................................................................................................................................................................185
29.1.1 Hardware Operation...........................................................................................................................................185
29.1.2 Clocks.................................................................................................................................................................186
29.1.3 Software Operation............................................................................................................................................187
29.1.4 Driver Features...................................................................................................................................................187
29.1.5 Source Code Structure.......................................................................................................................................187
29.1.6 Menu Configuration Options.............................................................................................................................188
Chapter 30
Watchdog (WDOG) Driver
30.1 Introduction.....................................................................................................................................................................189
30.1.1 Hardware Operation...........................................................................................................................................189
30.1.2 Software Operation............................................................................................................................................189
30.2 Generic WDOG Driver...................................................................................................................................................190
30.2.1 Driver Features...................................................................................................................................................190
30.2.2 Menu Configuration Options.............................................................................................................................190
30.2.3 Source Code Structure.......................................................................................................................................190
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30.2.4 Programming Interface......................................................................................................................................191
Chapter 31
OProfile
31.1 Introduction.....................................................................................................................................................................193
31.1.1 Overview............................................................................................................................................................193
31.1.2 Features..............................................................................................................................................................193
31.1.3 Hardware Operation...........................................................................................................................................194
31.2 Software Operation.........................................................................................................................................................194
31.2.1 Architecture Specific Components....................................................................................................................194
31.2.2 oprofilefs Pseudo Filesystem.............................................................................................................................195
31.2.3 Generic Kernel Driver........................................................................................................................................195
31.2.4 OProfile Daemon...............................................................................................................................................195
31.2.5 Post Profiling Tools...........................................................................................................................................196
31.3 Requirements..................................................................................................................................................................196
31.3.1 Source Code Structure.......................................................................................................................................196
31.3.2 Menu Configuration Options.............................................................................................................................196
31.3.3 Programming Interface......................................................................................................................................197
31.3.4 Interrupt Requirements......................................................................................................................................197
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Chapter 1
About This Book
1.1 Audience
This document is targeted to individuals who will port the i.MX Linux BSP to customer-
specific products.
The audience is expected to have a working knowledge of the Linux 3.0 kernel internals,
driver models, and i.MX processors.
1.1.1 Conventions
This document uses the following notational conventions:
• Courier monospaced type indicate commands, command parameters, code examples,
and file and directory names.
•Italic type indicates replaceable command or function parameters.
•Bold type indicates function names.
1.1.2 Definitions, Acronyms, and Abbreviations
The following table defines the acronyms and abbreviations used in this document.
Definitions and Acronyms
Term Definition
ADC Asynchronous Display Controller
address
translation
Address conversion from virtual domain to physical domain
API Application Programming Interface
ARM® Advanced RISC Machines processor architecture
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Term Definition
AUDMUX Digital audio MUX-provides a programmable interconnection for voice, audio, and synchronous data routing
between host serial interfaces and peripheral serial interfaces
BCD Binary Coded Decimal
bus A path between several devices through data lines
bus load The percentage of time a bus is busy
CODEC Coder/decoder or compression/decompression algorithm-used to encode and decode (or compress and
decompress) various types of data
CPU Central Processing Unit-generic term used to describe a processing core
CRC Cyclic Redundancy Check-Bit error protection method for data communication
CSI Camera Sensor Interface
DFS Dynamic Frequency Scaling
DMA Direct Memory Access-an independent block that can initiate memory-to-memory data transfers
DPM Dynamic Power Management
DRAM Dynamic Random Access Memory
DVFS Dynamic Voltage Frequency Scaling
EMI External Memory Interface-controls all IC external memory accesses (read/write/erase/program) from all the
masters in the system
Endian Refers to byte ordering of data in memory. Little endian means that the least significant byte of the data is
stored in a lower address than the most significant byte. In big endian, the order of the bytes is reversed
EPIT Enhanced Periodic Interrupt Timer-a 32-bit set and forget timer capable of providing precise interrupts at
regular intervals with minimal processor intervention
FCS Frame Checker Sequence
FIFO First In First Out
FIPS Federal Information Processing Standards-United States Government technical standards published by the
National Institute of Standards and Technology (NIST). NIST develops FIPS when there are compelling
Federal government requirements such as for security and interoperability but no acceptable industry
standards
FIPS-140 Security requirements for cryptographic modules-Federal Information Processing Standard 140-2(FIPS 140-2)
is a standard that describes US Federal government requirements that IT products should meet for Sensitive,
but Unclassified (SBU) use
Flash A non-volatile storage device similar to EEPROM, where erasing can be done only in blocks or the entire chip.
Flash path Path within ROM bootstrap pointing to an executable Flash application
Flush Procedure to reach cache coherency. Refers to removing a data line from cache. This process includes
cleaning the line, invalidating its VBR and resetting the tag valid indicator. The flush is triggered by a software
command
GPIO General Purpose Input/Output
hash Hash values are produced to access secure data. A hash value (or simply hash), also called a message
digest, is a number generated from a string of text. The hash is substantially smaller than the text itself, and is
generated by a formula in such a way that it is extremely unlikely that some other text produces the same hash
value.
I/O Input/Output
ICE In-Circuit Emulation
IP Intellectual Property
ISR Interrupt Service Routine
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Audience
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Term Definition
JTAG JTAG (IEEE Standard 1149.1) A standard specifying how to control and monitor the pins of compliant devices
on a printed circuit board
Kill Abort a memory access
KPP KeyPad Port-16-bit peripheral used as a keypad matrix interface or as general purpose input/output (I/O)
line Refers to a unit of information in the cache that is associated with a tag
LRU Least Recently Used-a policy for line replacement in the cache
MMU Memory Management Unit-a component responsible for memory protection and address translation
MPEG Moving Picture Experts Group-an ISO committee that generates standards for digital video compression and
audio. It is also the name of the algorithms used to compress moving pictures and video
MPEG
standards
Several standards of compression for moving pictures and video:
• MPEG-1 is optimized for CD-ROM and is the basis for MP3
• MPEG-2 is defined for broadcast video in applications such as digital television set-top boxes and DVD
• MPEG-3 was merged into MPEG-2
• MPEG-4 is a standard for low-bandwidth video telephony and multimedia on the World-Wide Web
MQSPI Multiple Queue Serial Peripheral Interface-used to perform serial programming operations necessary to
configure radio subsystems and selected peripherals
NAND Flash Flash ROM technology-NAND Flash architecture is one of two flash technologies (the other being NOR) used
in memory cards such as the Compact Flash cards. NAND is best suited to flash devices requiring high
capacity data storage. NAND flash devices offer storage space up to 512-Mbyte and offers faster erase, write,
and read capabilities over NOR architecture
NOR Flash See NAND Flash
PCMCIA Personal Computer Memory Card International Association-a multi-company organization that has developed
a standard for small, credit card-sized devices, called PC Cards. There are three types of PCMCIA cards that
have the same rectangular size (85.6 by 54 millimeters), but different widths
physical
address
The address by which the memory in the system is physically accessed
PLL Phase Locked Loop-an electronic circuit controlling an oscillator so that it maintains a constant phase angle (a
lock) on the frequency of an input, or reference, signal
RAM Random Access Memory
RAM path Path within ROM bootstrap leading to the downloading and the execution of a RAM application
RGB The RGB color model is based on the additive model in which Red, Green, and Blue light are combined to
create other colors. The abbreviation RGB comes from the three primary colors in additive light models
RGBA RGBA color space stands for Red Green Blue Alpha. The alpha channel is the transparency channel, and is
unique to this color space. RGBA, like RGB, is an additive color space, so the more of a color placed, the
lighter the picture gets. PNG is the best known image format that uses the RGBA color space
RNGA Random Number Generator Accelerator-a security hardware module that produces 32-bit pseudo random
numbers as part of the security module
ROM Read Only Memory
ROM
bootstrap
Internal boot code encompassing the main boot flow as well as exception vectors
RTIC Real-Time Integrity Checker-a security hardware module
SCC SeCurity Controller-a security hardware module
SDMA Smart Direct Memory Access
SDRAM Synchronous Dynamic Random Access Memory
SoC System on a Chip
SPBA Shared Peripheral Bus Arbiter-a three-to-one IP-Bus arbiter, with a resource-locking mechanism
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Chapter 1 About This Book
i.MX 6SoloLite Linux Reference Manual, Rev. L3.0.35_4.1.0, 09/2013
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Term Definition
SPI Serial Peripheral Interface-a full-duplex synchronous serial interface for connecting low-/medium-bandwidth
external devices using four wires. SPI devices communicate using a master/slave relationship over two data
lines and two control lines: Also see SS, SCLK, MISO, and MOSI
SRAM Static Random Access Memory
SSI Synchronous-Serial Interface-standardized interface for serial data transfer
TBD To Be Determined
UART Universal Asynchronous Receiver/Transmitter-asynchronous serial communication to external devices
UID Unique ID-a field in the processor and CSF identifying a device or group of devices
USB Universal Serial Bus-an external bus standard that supports high speed data transfers. The USB 1.1
specification supports data transfer rates of up to 12 Mb/s and USB 2.0 has a maximum transfer rate of 480
Mbps. A single USB port can be used to connect up to 127 peripheral devices, such as mice, modems, and
keyboards. USB also supports Plug-and-Play installation and hot plugging
USBOTG USB On The Go-an extension of the USB 2.0 specification for connecting peripheral devices to each other.
USBOTG devices, also known as dual-role peripherals, can act as limited hosts or peripherals themselves
depending on how the cables are connected to the devices, and they also can connect to a host PC
word A group of bits comprising 32-bits
Audience
i.MX 6SoloLite Linux Reference Manual, Rev. L3.0.35_4.1.0, 09/2013
20 Freescale Semiconductor, Inc.