Fujitsu MB86R12 Instruction Manual

FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB86R12 Application Note
DDR3 Interface
PCB Design Guideline
November, 2011
The 1.0 edition

i
MB86R12 Application Note
DDR3 Interface PCB Design Guideline
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Preface
This guideline describes PCB design restrictions related to MB86R12 DDR3 interface signal wiring.
· The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
· The information, such as descriptions of function and application circuit examples, in this document are
presented solely for the purpose of reference to show examples of operations and uses of FUJITSU
SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR
does not warrant proper operation of the device
with respect to use based on such information. When you develop equipment incorporating the device based
on such information, you must assume any responsibility arising out of such use of the information. FUJITSU
SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the
information.
· Any information in this document, including descriptions of function and schematic diagrams, shall not be
construed as license of the use or exercise of any intellectual property right, such as patent right or copyright,
or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU
SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the
intellectual property rights or other rights of third parties which would result from the use of information
contained herein.
· The products described in this document are designed, developed and manufactured as contemplated for
general use, including without limitation, ordinary industrial use, general office use, personal use, and
household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying
fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public,
and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction
control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability
(i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any
claims or damages arising in connection with above-mentioned uses of the products.
· Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or
loss from such failures by incorporating safety design measures into your facility and equipment such as
redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.
· Exportation/release of any products described in this document may require necessary procedures in
accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US
export control laws.
· The company names and brand names herein are the trademarks or registered trademarks of their respective
owners.
All rights reserved, Copyright FUJITSU SEMICONDUCTOR LIMITED 2011

ii
MB86R12 Application Note
DDR3 Interface PCB Design Guideline
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Revision History
Date
Ver.
Contents
2011/11/29
1.0
Newly issued

iii
MB86R12 Application Note
DDR3 Interface PCB Design Guideline
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Contents
1. Floor plan............................................................................................................ 1
2. PCB laminating................................................................................................... 2
3. DDR3_SDRAM specifications............................................................................ 3
4. Signal design restrictions (DDR3 interface part)............................................. 4
4.1. Definition of signal line group ................................................................................................................ 4
4.2. General wiring restrictions...................................................................................................................... 5
4.3. Resistance................................................................................................................................................ 5
4.4. Terminal resistance/Damping resistance/Wire length ............................................................................. 6
4.5. Wiring gap/Crosstalk............................................................................................................................... 7
4.6. ZQ/ODT setting ...................................................................................................................................... 8
4.7. Wiring topology ...................................................................................................................................... 9
4.7.1. Wiring topology diagram of MCK_Group...................................................................................... 9
4.7.2. Wiring topology diagram of MDQSx_Group................................................................................ 10
4.7.3. Wiring topology diagram of MDQx_Group...................................................................................11
4.7.4. Wiring topology diagram of MCNTL_Group/MCMD_Group ..................................................... 12
5. Power system design restrictions .................................................................. 13
5.1. Number and capacity of bypass capacitor............................................................................................. 13
5.2.Pull-out wiring condition ...................................................................................................................... 14

1
FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB86R12 Application Note
DDR3 Interface PCB Design Guideline
1. Floor plan
Figure 1-1 shows the reference example of the floor plan of MB86R12 and connected DDR3 SDRAM
devices.
Figure 1-1 Reference example of the floor plan of MB86R12 and DDR3 SDRAM devices
27mm
9mm
27mm
32mm
6mm
9mm
MB86R12
10mm
15.5mm
SDRAM
SDRAM

2
FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB86R12 Application Note
DDR3 Interface PCB Design Guideline
2. PCB laminating
This chapter shows the recommended laminating conditions of the PCB.
Figure 2-1 PCB laminating
Specified condition of wiring layer
•L1 and L8 are used as wiring and pull-out wiring layer of CLK.
•L3 and L6 are used as wiring layer of DQS, DQ, and CMD/ADD.
•L2 and L5 are used as power layer.
•L4 and L7 are used as GND layer.
Conductor
thickness
Insulator thickness
L1 43μm SIG. (copper foil: 18mm, plating: 25mm)
L2 35μm Power
L3 35μm SIG.
L4 35μm GND
L5 35μm Power
L6 35μm SIG.
L7 35μm GND
L8 43μm SIG. (copper foil: 18mm, plating: 25mm)
Resist thickness
40μm
100μm
150μm
150μm
100μm
150μm
150μm
100μm
40μm
Insulation material: relative permittivity=4.3 (only the resist part is 3.9)
Classification
Resist thickness

3
FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB86R12 Application Note
DDR3 Interface PCB Design Guideline
3. DDR3_SDRAM specifications
This chapter shows DDR3_SDRAM that can be used for the DDR3 interface with MB86R12.
If an alternative device fulfills the same requirements, it can also used.
Please note however, that if you use an alternative device, there may be differences concerning I/O quality
which may require your attention. However, all I/O characteristics should be checked as could differ.
Even if you use the device(s) listed below, you must refer to the specifications provided by the DRAM
manufacturer for the confirmation of details (e.g. operating temperature conditions etc.).
Table 3-1 Recommended DDR3_SDRAM
Manufacturer
Product name
IBIS model name
Driver strength
Remarks
Micron
Technology, Inc.
MT41J128M16HA-15E
(2Gb 1333Mbps)
v69a_at.ibs
34Ω
It has already been verified by
the transmission line analysis.

4
FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB86R12 Application Note
DDR3 Interface PCB Design Guideline
4. Signal design restrictions (DDR3 interface part)
This chapter describes the signal wiring design restrictions for the DDR3 interface part.
4.1. Definition of signal line group
In order to make the requirements for wiring configurations described further on in this document easier to
understand, the DDR3 interface signals are classified into the groups listed below.
Table 4-1 DDR3 interface signal grouping
Wiring
preferential
order
Group name Pin name of MB86R12
1
MCK_Group
MCK, MXCK
2
MDQS0_Group
MDQS0, MXDQS0
MDQS1_Group
MDQS1, MXDQS1
MDQS2_Group
MDQS2, MXDQS2
MDQS3_Group
MDQS3, MXDQS3
3
MDQ0_Group
MDQ0~MDQ7, MDM0
MDQ1_Group
MDQ8~MDQ15, MDM1
MDQ2_Group
MDQ16~MDQ23, MDM2
MDQ3_Group
MDQ24~MDQ31, MDM3
4
MCNTL_Group
MCKE, MXCS, MODT
5
MCMD_Group
MA0~MA14, MBA0~MBA2, MXCAS, MXRAS, MXWE