Fujitsu MB90480 Series User manual

FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90480/485 Series
HARDWARE MANUAL
CM44-10121-5E

FUJITSU LIMITED
F2MC-16LX
16-BIT MICROCONTROLLER
MB90480/485 Series
HARDWARE MANUAL
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Be sure to refer to the “Check Sheet” for the latest cautions on development.

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PREFACE
■Purpose of This Manual and Intended Readers
Thank you very much for purchasing FUJITSU products.
MB90480/485 series is a 16-bit microcontroller designed for applications such as consumer
devices requiring high-speed real-time processing. MB90480/485 series functions are suitable
for controlling PHS, cellular phones, CD-ROMs, and VTRs.
This manual, intended for engineers developing products using the MB90480/485 series,
explains the MB90480/485 series functions and operations. Read this manual first, before using
the product.
For details on the instructions, refer to the "Instruction Manual".
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■Trademark
Embedded Algorithm is a registered trademark of Advanced Micro Devices, Inc.
Other company names and brand names are the trademarks or registered trademarks of their
respective owners.

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■Composition of This Manual
This manual consists of the following 27 chapters and an appendix.
CHAPTER 1 "OVERVIEW OF MB90480/485 SERIES"
This chapter explains the features, block diagram, and functions to give basic specifications
about the MB90480/485 series.
CHAPTER 2 "CPU"
This chapter provides basic information on the architecture, specifications, and instructions
to help the reader understand the functions of the MB90480/485 series CPU core.
CHAPTER 3 "INTERRUPT"
This chapter gives an overview of the interrupts and explains the interrupt vectors and
interrupt sources, the register configuration and functions, and the interrupt processing.
CHAPTER 4 "RESET"
This chapter gives an overview of the reset and explains the reset sources, oscillation
stabilization wait time, and reset operation.
CHAPTER 5 "CLOCKS"
This chapter gives an overview of the clock and explains the register configuration and
functions, the clock modes, and the oscillation stabilization wait time.
CHAPTER 6 "LOW-POWER CONSUMPTION MODE"
This chapter gives an overview of the low-power consumption mode and explains the
register configuration and functions and the operations of the low-power consumption mode.
CHAPTER 7 "MODE SETTING"
This chapter gives an overview of mode setting and explains the mode pins, mode data, and
operation of each mode for mode setting.
CHAPTER 8 "I/O PORT"
This chapter gives an overview of the I/O ports and explains the configuration and functions
of the registers used by the I/O ports.
CHAPTER 9 "TIMEBASE TIMER"
This chapter gives an overview of the timebase timer and explains the register configuration
and functions, the timebase timer interrupt, and the timebase timer operation.
CHAPTER 10 "WATCHDOG TIMER"
This chapter gives an overview of the watchdog timer and explains the register configuration
and functions and the watchdog timer operation.
CHAPTER 11 "WATCH TIMER"
This chapter gives an overview of the watch timer and explains the register configuration and
functions and the watch timer operation.
CHAPTER 12 "16-BIT INPUT/OUTPUT TIMER"
This chapter gives an overview of the 16-bit input/output timer and explains the register
configuration and functions and the 16-bit input/output timer operation.
CHAPTER 13 "8/16-BIT UP/DOWN COUNTER/TIMER"
This chapter gives an overview of the 8/16-bit up/down counter/timer and explains the
register configuration and functions and the operation of the 8/16-bit up/down counter/timer.

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CHAPTER 14 "16-BIT RELOAD TIMER"
This chapter gives an overview of the 16-bit reload timer and explains the register
configuration and functions and the 16-bit reload timer operation.
CHAPTER 15 "8/16-BIT PPG TIMER"
This chapter gives an overview of the 8/16-bit PPG timer and explains the register
configuration and functions and the 8/16-bit PPG timer operation.
CHAPTER 16 "DTP/EXTERNAL INTERRUPT UNIT"
This chapter gives an overview of the DTP/external interrupt unit and explains the register
configuration and functions and the operations of the DTP/external interrupt unit.
CHAPTER 17 "8/10-BIT A/D CONVERTER"
This chapter gives an overview of the 8/10-bit A/D converter and explains the register
configuration and functions and the operations of the 8/10-bit A/D converter.
CHAPTER 18 "EXPANDED I/O SERIAL INTERFACE"
This chapter gives an overview of the expanded I/O serial interface and explains the register
configuration and functions and the operation of the expanded I/O serial interface.
CHAPTER 19 "UART"
This chapter gives an overview of the UART and explains the register configuration and
functions and the UART operations. It also gives precautions on using the UART and a
UART program example.
CHAPTER 20 "CHIP SELECTION FACILITY"
This chapter gives an overview of the chip selection facility and explains the register
configuration and functions and the operation of the chip selection facility.
CHAPTER 21 "ADDRESS MATCH DETECTION FUNCTION"
This chapter explains the address match detection function and its operation.
CHAPTER 22 "ROM MIRROR FUNCTION SELECTION MODULE"
This chapter explains the functions of the ROM mirror function selection module and the
register configuration and functions.
CHAPTER 23 "2M/3M BIT FLASH MEMORY"
This chapter explains the functions and operation of the 2M/3M bit flash memory and the
operations for writing data to and erasing data from the flash memory.
CHAPTER 24 "EXAMPLES OF MB90F481B/MB90F482B SERIAL PROGRAMMING
CONNECTION"
This chapter shows an example of a serial programming connection using the AF220/AF210/
AF120/AF110 Flash Micro-computer Programmer by Yokogawa Digital Computer
Corporation.
CHAPTER 25 "PWC TIMER" (only for MB90485 series)
This chapter gives an overview of the PWC timer and explains the register configuration and
functions and the operation of the PWC timer.
CHAPTER 26 "μPG TIMER" (only for MB90485 series)
This chapter gives an overview of the μPG timer and explains the register configuration and
functions and the operation of the μPG timer.

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CHAPTER 27 "I2C INTERFACE" (only for MB90485 series)
This chapter gives an overview of the I2C interface and explains the register configuration
and functions and the operation of the I2C interface.
APPENDIX
The appendix gives information about the following parts: the I/O map, interrupt vectors, and
list of instructions. It gives detailed information that could not be included in the main text
and reference material for programming.

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Copyright ©2003-2006 FUJITSU LIMITED All rights reserved.
• The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU semiconductor device; FUJITSU does not warrant
proper operation of the device with respect to use based on such information. When you develop equipment incorporating the
device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU
assumes no liability for any damages whatsoever arising out of the use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU or any
third party or does FUJITSU warrant non-infringement of any third-party's intellectual property right or other right by using
such information. FUJITSU assumes no liability for any infringement of the intellectual property rights or other rights of third
parties which would result from the use of information contained herein.
• The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite). Please note that FUJITSU will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
• If any products described in this document represent goods or technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export
of those products from Japan.

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CONTENTS
CHAPTER 1 OVERVIEW OF MB90480/485 SERIES ........................................................ 1
1.1 Features of MB90480/485 Series .......................................................................................................... 2
1.2 Block Diagram of MB90480/485 Series ................................................................................................. 6
1.3 Package Dimensions ............................................................................................................................. 7
1.4 Pin Assignment ...................................................................................................................................... 9
1.5 Pin Functions ....................................................................................................................................... 11
1.6 I/O Circuit Type .................................................................................................................................... 18
1.7 Handling the Device ............................................................................................................................. 21
CHAPTER 2 CPU ............................................................................................................. 23
2.1 Overview of CPU Specifications .......................................................................................................... 24
2.2 Memory Space ..................................................................................................................................... 25
2.3 CPU Registers ..................................................................................................................................... 29
2.3.1 Accumulator (A) .............................................................................................................................. 31
2.3.2 User Stack Pointer (USP) and System Stack Pointer (SSP) .......................................................... 32
2.3.3 Processor Status (PS) .................................................................................................................... 33
2.3.4 Program Counter (PC) .................................................................................................................... 36
2.3.5 Program Counter Bank Register (PCB) .......................................................................................... 37
2.3.6 Direct Page Register (DPR) ........................................................................................................... 38
2.3.7 General-Purpose Register (Register Bank) .................................................................................... 39
2.4 Prefix Codes ........................................................................................................................................ 40
CHAPTER 3 INTERRUPT ................................................................................................ 43
3.1 Overview of Interrupt ........................................................................................................................... 44
3.2 Interrupt Factor and Interrupt Vector ................................................................................................... 46
3.3 Interrupt Control Register and Peripheral Function ............................................................................. 49
3.3.1 Interrupt Control Register (ICR00 to ICR15) .................................................................................. 50
3.4 Hardware Interrupt ............................................................................................................................... 53
3.4.1 Hardware Interrupt Operation ......................................................................................................... 56
3.4.2 Flow of Hardware Interrupt Operation ............................................................................................ 58
3.4.3 Procedure for Using Hardware Interrupt ......................................................................................... 59
3.4.4 Multiple Interrupts ........................................................................................................................... 61
3.4.5 Hardware Interrupt Processing Time .............................................................................................. 63
3.5 Software Interrupt ................................................................................................................................ 65
3.6 Interrupt by μDMAC ............................................................................................................................. 67
3.6.1 DMA Descriptor .............................................................................................................................. 70
3.6.2 Individual Registers of DMA Descriptor .......................................................................................... 72
3.6.3 μDMAC Processing Procedure ....................................................................................................... 75
3.6.4 μDMAC Processing Time ............................................................................................................... 76
3.7 Interrupt by Extended Intelligent I/O Service (EI2OS) .......................................................................... 78
3.7.1 EI2OS descriptor (ISD) ................................................................................................................... 80
3.7.2 Each Register of EI2OS Descriptor (ISD) ....................................................................................... 82
3.7.3 Operation of EI2OS ......................................................................................................................... 85
3.7.4 Procedure for Use of EI2OS ........................................................................................................... 86

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3.7.5 Processing Time of the Extended Intelligent I/O Service (EI2OS) ................................................. 87
3.8 Exception Processing Interrupt ........................................................................................................... 89
3.9 Stack Operation of Interrupt Processing ............................................................................................. 90
3.10 Sample Program of Interrupt Processing ............................................................................................ 92
3.11 Delay Interrupt Generation Module ..................................................................................................... 93
3.11.1 Operation of Delay Interrupt Generation Module ........................................................................... 94
CHAPTER 4 RESET ........................................................................................................ 95
4.1 Overview of Reset ............................................................................................................................... 96
4.2 Reset Factors and Oscillation Stabilization Wait Time ....................................................................... 98
4.3 External-Reset Pin ............................................................................................................................ 100
4.4 Resetting ........................................................................................................................................... 101
4.5 Reset-Factor Bits .............................................................................................................................. 103
4.6 Condition of Pins as Result of Reset ................................................................................................ 105
CHAPTER 5 CLOCKS ................................................................................................... 107
5.1 Overview of Clocks ........................................................................................................................... 108
5.2 Block Diagram of Clock Generator ................................................................................................... 110
5.3 Clock Selection Register (CKSCR) and PLL Output Selection Register (PLLOS) ........................... 112
5.4 Clock Modes ..................................................................................................................................... 117
5.5 Oscillation Stabilization Wait Time .................................................................................................... 121
5.6 Connecting Oscillator to External Clock ............................................................................................ 122
CHAPTER 6 LOW-POWER CONSUMPTION MODE .................................................... 123
6.1 Overview of Low-Power Consumption Mode .................................................................................... 124
6.2 Block Diagram of Low-Power Consumption Control Circuit .............................................................. 126
6.3 Low-Power Consumption Mode Control Register (LPMCR) ............................................................. 128
6.4 CPU Intermittent Operation Mode ..................................................................................................... 131
6.5 Standby Mode ................................................................................................................................... 132
6.5.1 Sleep Mode .................................................................................................................................. 133
6.5.2 Timebase Timer Mode ................................................................................................................. 135
6.5.3 Watch Mode ................................................................................................................................. 137
6.5.4 Stop Mode ................................................................................................................................... 139
6.6 State Transition Diagram .................................................................................................................. 141
6.7 Pin State in Standby Mode, Hold, and Reset .................................................................................... 143
6.8 Caution on Using Low-Power Consumption Mode ........................................................................... 148
CHAPTER 7 MODE SETTING ....................................................................................... 153
7.1 Mode Setting ..................................................................................................................................... 154
7.2 Mode Pins (MD2 to MD0) ................................................................................................................. 155
7.3 Mode Data ........................................................................................................................................ 156
7.4 External Memory Access .................................................................................................................. 160
7.4.1 Automatic ready function selection register (ARSR) .................................................................... 162
7.4.2 External address output control register (HACR) ......................................................................... 164
7.4.3 Bus control signal selection register (EPCR) ............................................................................... 165
7.5 Operation of Each Mode for Mode Setting ........................................................................................ 167
7.5.1 External memory access control signals ...................................................................................... 168
7.5.2 Ready function ............................................................................................................................. 171

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7.5.3 Hold function ................................................................................................................................. 174
CHAPTER 8 I/O PORT ................................................................................................... 177
8.1 Functions of I/O Port .......................................................................................................................... 178
8.2 Registers for I/O Port ......................................................................................................................... 179
8.2.1 Port registers (PDR0 to PDRA) .................................................................................................... 180
8.2.2 Port direction registers (DDR0 to DDRA) ..................................................................................... 181
8.2.3 Other registers .............................................................................................................................. 183
CHAPTER 9 TIMEBASE TIMER .................................................................................... 185
9.1 Overview of Timebase Timer ............................................................................................................. 186
9.2 Timebase Timer Configuration .......................................................................................................... 188
9.3 Timebase Timer Control Register (TBTC) ......................................................................................... 190
9.4 Timebase Timer Interrupt .................................................................................................................. 192
9.5 Timebase Timer Operation ................................................................................................................ 193
9.6 Notes on Using Timebase Timer ....................................................................................................... 196
9.7 Sample Programs of Timebase timer ................................................................................................ 197
CHAPTER 10 WATCHDOG TIMER ................................................................................. 199
10.1 Overview of Watchdog Timer ............................................................................................................ 200
10.2 Watchdog Timer Control Register (WDTC) ....................................................................................... 201
10.3 Watchdog Timer Configuration .......................................................................................................... 203
10.4 Watchdog Timer Operation ................................................................................................................ 205
10.5 Notes on Using Watchdog Timer ....................................................................................................... 207
10.6 Sample Programs of Watchdog Timer ............................................................................................... 208
CHAPTER 11 WATCH TIMER ......................................................................................... 209
11.1 Overview of Watch Timer .................................................................................................................. 210
11.2 Watch Timer Configuration ................................................................................................................ 211
11.3 Watch Timer Control Register (WTC) ................................................................................................ 212
11.4 Watch Timer Operation ...................................................................................................................... 214
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ................................................................ 217
12.1 Overview of 16-bit Input/Output Timer ............................................................................................... 218
12.2 Configuration of 16-bit Input/Output Timer ........................................................................................ 219
12.3 Configuration and Function of 16-bit Input/Output Timer Register .................................................... 223
12.3.1 Free-running timer ........................................................................................................................ 224
12.3.2 Output compare ............................................................................................................................ 229
12.3.3 Input capture ................................................................................................................................. 233
12.4 Interrupt of 16-bit Input/Output Timer ................................................................................................ 235
12.5 16-bit Input/Output Timer Operation .................................................................................................. 237
12.5.1 Operation of free-running timer .................................................................................................... 238
12.5.2 Operation of output compare ........................................................................................................ 240
12.5.3 Operation of input capture ............................................................................................................ 242
12.5.4 Free-running timer timing ............................................................................................................. 243
12.5.5 Output compare timing ................................................................................................................. 244
12.5.6 Timing of input capture ................................................................................................................. 245
12.6 Program Example of 16-bit Input/Output Timer ................................................................................. 246

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CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER ................................................... 259
13.1 Overview of 8/16-bit Up/Down Counter Timer .................................................................................. 260
13.2 Configuration of 8/16-bit Up/Down Counter/Timer ............................................................................ 261
13.3 Configuration and Functions of Registers for 8/16-bit Up/Down Counter/Timer ............................... 264
13.3.1 Counter control register (ch.0) upper (CCRH0) ........................................................................... 265
13.3.2 Counter control register (ch.1) upper (CCRH1) ........................................................................... 267
13.3.3 Counter control register (ch.0/ch.1) lower (CCRL0/CCRL1) ........................................................ 269
13.3.4 Counter status register 0/1 (CSR0/CSR1) ................................................................................... 271
13.3.5 Up/down count register (ch.0/ch.1) (UDCR0/UDCR1) ................................................................. 273
13.3.6 Reload/compare register (ch.0/ch.1) (RCR0/RCR1) .................................................................... 274
13.4 Interrupt of 8/16-bit Up/Down Counter/Timer .................................................................................... 275
13.5 8/16-bit Up/Down Counter/Timer Operation ..................................................................................... 277
13.5.1 Reload/compare function ............................................................................................................. 280
13.5.2 Writing data to up/down count register (UDCR) ........................................................................... 283
13.6 Program Example of 8/16-bit Up/Down Counter/Timer .................................................................... 285
CHAPTER 14 16-BIT RELOAD TIMER ........................................................................... 291
14.1 Overview of 16-Bit Reload Timer ...................................................................................................... 292
14.2 Configuration and Functions of 16-Bit Reload Timer Registers ........................................................ 296
14.2.1 Timer Control Status Register (TMCSR) ..................................................................................... 297
14.2.2 16-Bit Timer Register (TMR)/16-Bit Reload Register (TMRLR) ................................................... 301
14.3 Interrupt of 16-Bit Reload Timer ........................................................................................................ 303
14.4 Operations of the 16-Bit Reload Timer ............................................................................................. 304
14.4.1 State Transitions During Count Operation ................................................................................... 305
14.4.2 Operations of Internal Clock Mode (Reload Mode) ...................................................................... 306
14.4.3 Internal Clock Mode (One-Shot Mode) ........................................................................................ 308
14.4.4 Event Count Mode ....................................................................................................................... 310
14.5 Program Example of 16-Bit Reload Timer ........................................................................................ 312
CHAPTER 15 8/16-BIT PPG TIMER ................................................................................ 317
15.1 Overview of 8/16-Bit PPG Timer ....................................................................................................... 318
15.2 Configuration of 8/16-Bit PPG Timer ................................................................................................ 319
15.3 Configuration and Functions of 8/16-Bit PPG Timer Registers ......................................................... 322
15.3.1 PPG0/2/4 Operation Mode Control Register (PPGC0/PPGC2/PPGC4) ...................................... 323
15.3.2 PPG1/3/5 Operation Mode Control Register (PPGC1/PPGC3/PPGC5) ...................................... 325
15.3.3 PPG0 to PPG5 Output Control Registers (PPG01, PPG23, PPG45) .......................................... 328
15.3.4 Reload Registers (PRLL0 to PRLL5, PRLH0 to PRLH5) ............................................................. 330
15.4 Interrupt of 8/16-Bit PPG Timer ........................................................................................................ 331
15.5 Operations of 8/16-Bit PPG Timer .................................................................................................... 333
15.6 Program Example of 8/16-Bit PPG Timer ......................................................................................... 338
CHAPTER 16 DTP/EXTERNAL INTERRUPTS ............................................................... 341
16.1 Overview of DTP/External Interrupt Unit ........................................................................................... 342
16.2 Configuration and Functions of DTP/External Interrupt Unit Registers ............................................. 344
16.3 DTP/External Interrupt ...................................................................................................................... 346
16.4 Operations of DTP/External Interrupt Unit ........................................................................................ 348
16.5 Precautions on Use of DTP/External Interrupt Unit .......................................................................... 350
16.6 Program Example of DTP/External Interrupt .................................................................................... 352

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CHAPTER 17 8/10-BIT A/D CONVERTER ...................................................................... 355
17.1 Overview of 8/10-Bit A/D Converter ................................................................................................... 356
17.2 Configuration of 8/10-Bit A/D Converter ............................................................................................ 357
17.3 Configuration and Functions of 8/10-Bit A/D Converter Registers .................................................... 359
17.3.1 Control Status Register 1 (ADCS1) .............................................................................................. 360
17.3.2 Control Status Register 2 (ADCS2) .............................................................................................. 363
17.3.3 Data Registers (ADCR2 and ADCR1) .......................................................................................... 366
17.4 Interrupt of 8/10-Bit A/D Converter .................................................................................................... 367
17.5 Operations of 8/10-Bit A/D Converter ................................................................................................ 368
17.5.1 Example of μDMAC Start in Single Mode ..................................................................................... 370
17.5.2 Example of μDMAC Start in Continuous Mode ............................................................................ 372
17.5.3 Example of μDMAC Start in Stop Mode ....................................................................................... 374
17.6 Conversion Data Protection Function of 8/10-Bit A/D Converter ....................................................... 376
17.7 Precautions on use of the 8/10-Bit A/D Converter ............................................................................. 378
17.8 Program Example of 8/10-Bit A/D Converter ..................................................................................... 379
CHAPTER 18 EXPANDED I/O SERIAL INTERFACE ..................................................... 385
18.1 Overview of Expanded I/O Serial Interface ........................................................................................ 386
18.2 Configuration of Expanded I/O Serial Interface ................................................................................. 387
18.3 Configuration and Functions of Expanded I/O Serial Interface Registers ......................................... 389
18.3.1 Serial Mode Control Status Register 0/1 (SMCS0/SMCS1) ......................................................... 390
18.3.2 Serial Data Register 0/1 (SDR0/SDR1) ........................................................................................ 394
18.3.3 Communication Prescaler Control Register0/1 (SDCR0/SDCR1) ................................................ 395
18.4 Interrupt of Expanded I/O Serial Interface ......................................................................................... 396
18.5 Operation of Expanded I/O Serial Interface ....................................................................................... 397
18.5.1 Shift Clock Modes ......................................................................................................................... 398
18.5.2 Operational States of Serial I/O Units ........................................................................................... 399
18.5.3 Start/Stop Timing and Input/Output Timing of Shift Operation ..................................................... 401
18.5.4 Interrupt Function ......................................................................................................................... 403
18.6 Program Example of Expanded I/O Serial Interface .......................................................................... 404
CHAPTER 19 UART ......................................................................................................... 407
19.1 Overview of the UART ....................................................................................................................... 408
19.2 Configuration of UART ....................................................................................................................... 409
19.3 Configuration and Functions of UART Registers ............................................................................... 411
19.3.1 Serial Mode Register (SMR) ......................................................................................................... 412
19.3.2 Serial Control Register (SCR) ...................................................................................................... 414
19.3.3 Serial Input/Output Register (SIDR/SODR) .................................................................................. 416
19.3.4 Serial Status Register (SSR) ........................................................................................................ 417
19.3.5 Communication Prescaler Control Register (CDCR) .................................................................... 419
19.4 Interrupt of UART ............................................................................................................................... 421
19.5 UART Operations .............................................................................................................................. 423
19.5.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) .................................................... 427
19.5.2 Operation in Synchronous Mode (Operation Mode 2) .................................................................. 430
19.5.3 Two-Way Communication Function (Normal Mode) ..................................................................... 432
19.5.4 Master/Slave Communication Function (Multiprocessor Mode) ................................................... 434
19.6 Precautions on use of the UART ....................................................................................................... 437
19.7 Program Example of UART ............................................................................................................... 438

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CHAPTER 20 CHIP SELECTION FACILITY ................................................................... 445
20.1 Overview of Chip Selection Facility ................................................................................................... 446
20.2 Configuration of Chip Selection Facility ............................................................................................ 447
20.3 Configuration and Functions of Chip Selection Facility Registers .................................................... 449
20.3.1 Chip Select Area MASK Register (CMRx) ................................................................................... 450
20.3.2 Chip Selection Area Register (CARx) .......................................................................................... 451
20.3.3 Chip Selection Control Register (CSCR) ..................................................................................... 452
20.3.4 Chip Selection Active Level Register (CALR) .............................................................................. 453
20.4 Operation of the Chip Selection Facility ............................................................................................ 454
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION .......................................... 457
21.1 Overview of Address Match Detection Function ............................................................................... 458
21.2 Block Diagram of Address Match Detection Function ....................................................................... 459
21.3 Configuration of Registers for Address Match Detection Function ................................................... 460
21.3.1 Program Address Detection Control Status Register (PACSR) ................................................... 461
21.3.2 Program Address Detection Registers (PADR0, PADR1) ........................................................... 463
21.4 Explanation of Operation of Address Match Detection Function ...................................................... 465
21.4.1 Example of using Address Match Detection Function ................................................................. 466
21.5 Program Example of Address Match Detection Function ................................................................. 471
CHAPTER 22 ROM MIRROR FUNCTION SELECTION MODULE ................................. 473
22.1 Overview of ROM Mirror Function Selection Module ........................................................................ 474
22.2 ROM Mirror Function Selection Register (ROMM) ........................................................................... 475
CHAPTER 23 2M/3M BIT FLASH MEMORY ................................................................... 477
23.1 Overview of 2M/3M Bit Flash Memory .............................................................................................. 478
23.2 Sector Configuration of 2M/3M Bit Flash Memory ............................................................................ 479
23.3 Flash memory Control Status Register (FMCS) ............................................................................... 480
23.4 Method for Starting the Flash Memory's Automatic Algorithm .......................................................... 486
23.5 Verifying the Execution State of the Automatic Algorithm ................................................................. 487
23.5.1 Data Polling Flag (DQ7) ............................................................................................................... 489
23.5.2 Toggle Bit Flag (DQ6) .................................................................................................................. 491
23.5.3 Timing Limit Excess Flag (DQ5) .................................................................................................. 492
23.5.4 Sector Erase Timer Flag (DQ3) ................................................................................................... 493
23.6 Flash Memory Write/Erase Operations ............................................................................................. 494
23.6.1 Setting the Flash Memory to Read/Reset State ........................................................................... 495
23.6.2 Writing Data to Flash Memory ..................................................................................................... 496
23.6.3 Erasing All Data in the Flash Memory (Chip Erase) .................................................................... 498
23.6.4 Erasing Arbitrary Data in Flash Memory (Sector Erase) .............................................................. 499
23.6.5 Suspending Sector Erasure for the Flash Memory ...................................................................... 501
23.6.6 Resuming the Sector Erasure of Flash Memory .......................................................................... 502
23.7 Flash Security Function .................................................................................................................... 503

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CHAPTER 24 EXAMPLES OF MB90F481B/MB90F482B/MB90F488B/MB90F489B
SERIAL PROGRAMMING CONNECTION............................................... 505
24.1 Basic Configuration of Serial Programming Connection with MB90F481B/MB90F482B/MB90F488B/
MB90F489B....................................................................................................................................... 506
24.2 Example of Connection in Single-Chip Mode (When Using the User Power Supply) ....................... 510
24.3 Example of Minimum Connection with Flash Microcontroller Programmer
(When Using the User Power Supply)............................................................................................... 512
CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) .................................................. 515
25.1 Overview of PWC Timer .................................................................................................................... 516
25.2 Configuration of PWC Timer .............................................................................................................. 517
25.3 Configuration and Functions of PWC Timer Registers ...................................................................... 519
25.3.1 PWC Control/Status Register (PWCSR0 to PWCSR2) ................................................................ 520
25.3.2 PWC Data Buffer Register (PWCR0 to PWCR2) ......................................................................... 525
25.3.3 Divide Ratio Control Register (DIVR0 to DIVR2) .......................................................................... 526
25.4 Interrupt of PWC Timer ...................................................................................................................... 527
25.5 Operations of PWC Timer .................................................................................................................. 529
25.5.1 Operations of the Timer Function ................................................................................................. 530
25.5.2 Operations of the Pulse Width Measurement Function ................................................................ 531
25.5.3 Selection of Count Clock and Operation Mode ............................................................................ 533
25.5.4 Start and Stop of Timer/Pulse Width Measurement ..................................................................... 535
25.5.5 Timer Mode Operation .................................................................................................................. 537
25.5.6 Operation in Pulse Width Measurement Mode ............................................................................. 540
25.6 Notes on PWC Timer Usage ............................................................................................................. 546
CHAPTER 26 µPG TIMER (ONLY MB90485 SERIES) ................................................... 549
26.1 Overview and Configuration of µPG Timer ........................................................................................ 550
26.2 Configuration and Functions of µPG Timer Registers ....................................................................... 552
26.3 Timing Chart of µPG Timer ................................................................................................................ 554
CHAPTER 27 I2C INTERFACE (ONLY MB90485 SERIES) ............................................ 555
27.1 Overview of I2C Interface ................................................................................................................... 556
27.2 Configuration of I2C Interface ............................................................................................................ 557
27.3 Configuration and Functions of I2C Interface Registers .................................................................... 559
27.3.1 Bus Status Register (IBSR) .......................................................................................................... 560
27.3.2 Bus Control Register (IBCR) ........................................................................................................ 562
27.3.3 Clock Control Register (ICCR) ..................................................................................................... 568
27.3.4 Address Register (IADR) .............................................................................................................. 570
27.3.5 Data Register (IDAR) .................................................................................................................... 571
27.4 Interrupt of I2C Interface .................................................................................................................... 572
27.5 I2C Interface Operation ...................................................................................................................... 574

xiv
APPENDIX .......................................................................................................................... 577
APPENDIX A Memory Map ........................................................................................................................ 578
APPENDIX B I/O Map ................................................................................................................................ 581
APPENDIX C Interrupt Source, Interrupt Vector, and Interrupt Control Register ....................................... 589
APPENDIX D Instructions ........................................................................................................................... 591
D.1 Instruction Types ............................................................................................................................ 592
D.2 Addressing ..................................................................................................................................... 593
D.3 Direct Addressing ........................................................................................................................... 595
D.4 Indirect Addressing ......................................................................................................................... 600
D.5 Execution Cycle Count ................................................................................................................... 606
D.6 Effective Address Field ................................................................................................................... 609
D.7 How to Read the Instruction List .................................................................................................... 610
D.8 F2MC-16LX Instruction List ............................................................................................................ 613
D.9 Instruction Map ............................................................................................................................... 627
INDEX ................................................................................................................................. 649

xv
Main changes in this edition
Page Changes (For details, refer to main body.)
-
All of the following descriptions are changed.
(μDMA → μDMAC)
(2M BIT FLASH MEMORY → 2M/3M BIT FLASH MEMORY)
(MB90F481/MB90F482 → MB90F481B/MB90F482B/MB90F488B/MB90F489B)
4 Table 1.1-2 MB90485 series product configuration is changed.
5■Package of corresponding products is added.
6 Figure 1.2-1 Block diagram of MB90480/485 Series is changed.
9Figure 1.4-1 Pin assignment diagram of MB90480/485 series (QFP-100) is changed.
(Text in the figure is changed.)
10 Figure 1.4-2 Pin assignment diagram of MB90480/485 series (LQFP-100) is changed.
(Text in the figure is changed.)
21
❍Crystal oscillation circuit is changed.
(Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. is
added.)
22
❍Notes on using external clock is changed.
(Use of the external clock requires a connection with an external pin, as shown in Figure 1.7-1 "Use of exter-
nal clock". → To use external clock, drive only pin XO. Be sure to set up pin X1 to be open.)
❍Note on operations during PLL clock mode is changed.
(If the PLL clock mode is selected, the microcontroller attempt to be working with the selfoscillating circuit
even when there is no external oscillator or external clock input is stopped.Performance of this operation,
however, cannot be guaranteed. → On this microcontroller, if in case the crystal oscillator breaks off or an
external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained
in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee
results of operations if such failure occurs.)
48
Table 3.2-2 Interrupt factors, interrupt vectors, and interrupt control registers is changed.
(*2: Please write "0" in the INTE bit, after prohibiting interrupt by setting the IL2 bit to IL0 bit of the inter-
rupt control register to "111B", if the reload timer underflow interrupt setting is changed from enable (INTE
bit of TMCSR registers =1) to prohibit (INTE bit of TMCSR registers =0). is added.)
75 Figure 3.6-7 μDMAC processing procedure is changed.
78 to 88 3.7 Interrupt by Extended Intelligent I/O Service (EI2OS) is added.
96 ■Reset factors ❍Power-on reset of 4.1 Overview of Reset is changed.
(MB90F488B → MB90F488B/F489B)
115
Figure 5.3-2 Configuration of PLL output selection register (PLLOS) is changed.
(------X0B→ ------00B)
(PLL output selection bit → PLL output frequency doubling selection bit)
(Reserved bit → PLL input divided selection bit)
116 Table 5.3-2 Functions of bits for PLL output selection register (PLLOS) is changed.
(•The readout value is always 1. → •Read value is undefined.)

xvi
143
Table 6.7-1 Pin states in single chip mode is changed.
(*3: "Input cutoff" means that operations of input gates located very close to the pins are disabled. "Output
Hi-Z" means that the pin-drive transistors are disabled and the pins are set to the high-impedance state. →
*2: In the state of "Input cutoff", input A is masked and "L" level is transmitted internally. "Output Hi-Z"
means that the pin-drive transistors are disabled and the pins are set to the high-impedance state.)
144
Table 6.7-2 Pin states in external bus 16-bit data bus mode and multiplex 16-bit external bus mode is
changed.
(*6: "Input cutoff" means that operations of input gates located very close to the pins are disabled. "Output
Hi-Z"means that the pin-drive transistors are disabled and the pins are set to the high-impedance state. →
*5: In the state of "Input cutoff", input A is masked and "L" level is transmitted internally. "Output Hi-Z"
means that the pin-drive transistors are disabled and the pins are set to the high-impedance state.)
145
Table 6.7-3 Pin states in external bus 8-bit data bus mode and multiplex 8-bit external bus mode is changed.
(*6: "Input cutoff" means that operations of input gates located very close to the pins are disabled. "Output
Hi-Z"means that the pin-drive transistors are disabled and the pins are set to the high-impedance state. →
*5: In the state of "Input cutoff", input A is masked and "L" level is transmitted internally. "Output Hi-Z"
means that the pin-drive transistors are disabled and the pins are set to the high-impedance state.)
146
Table 6.7-4 Pin states in external bus 16-bit data bus mode and non-multiplex 16-bit external bus mode is
changed.
(*6: "Input cutoff" means that operations of input gates located very close to the pins are disabled. "Output
Hi-Z"means that the pin-drive transistors are disabled and the pins are set to the high-impedance state. →
*5: In the state of "Input cutoff", input A is masked and "L" level is transmitted internally. "Output Hi-Z"
means that the pin-drive transistors are disabled and the pins are set to the high-impedance state.)
205 ❍Clearing of the watchdog timer is changed.
(Note: is changed.)
224
■Compare clear register (CPCLR) is changed.
(When this register value matches the value of the 16-bit free-running timer, the 16-bit free-running timer
value is initialized to 0000Hand a compare clear interrupt flag is set. When interrupt operation is allowed, an
interrupt request is issued to the CPU. → When the MODE bit of the timer counter control status register
(TCCS) is set to "1", the freerunning timer value is initialized to "0000H" at matching this register value and
the value of the free-running timer. When this register value matches the value of the free-running timer, a
compare clear interrupt flag is set. When the compare interrupt flag is set to "1", an interrupt request issues to
the CPU at allowing the interrupt operation.)
227 [bit3] SCLR is changed.
(Note: is added.)
229 Figure 12.3-8 Registers of output compare is changed.
(ICP1C → ICP1)
235 12.4 Interrupt of 16-bit Input/Output Timer is added.
246 12.6 Program Example of 16-bit Input/Output Timer is added.
275, 276 13.4 Interrupt of 8/16-bit Up/Down Counter/Timer is added.
285 to 290 13.6 Program Example of 8/16-bit Up/Down Counter/Timer is added.
299
[bit3] INTE (Timer interrupt request enable) is changed.
(Note: is added.)
[bit2] UF (Timer interrupt request flag) is changed.
(Note: is added.)
312 to 316 14.5 Program Example of 16-Bit Reload Timer is added.
Page Changes (For details, refer to main body.)