Fujitsu F2MC-16LX Series User manual

FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90550A/B Series
HARDWARE MANUAL
CM44-10103-5E

FUJITSU LIMITED
F2MC-16LX
16-BIT MICROCONTROLLER
MB90550A/B Series
HARDWARE MANUAL
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Be sure to refer to the “Check Sheet” for the latest cautions on development.

i
PREFACE
■Objective and Intended Readership
Thank you for your continued preference for Fujitsu semiconductor products.
The MB90550A/B Series was developed as general-purpose version of the F2MC-16LX Series,
which is a proprietary 16-bit single-chip microcontroller that supports application-specific ICs
(ASICs).
This manual is intended for engineers who design products using this semiconductor. Consult
this manual for information on the functions and operations of the MB90550A/B Series.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■Trademark
Embedded AlgorithmTM is a trademark of Advanced Micro Devices, Inc.
The company names and brand names herein are the trademarks or registered trademarks of
their respective owners.
■Licence
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to
use, these components in an I2C system provided that the system conforms to the I2C Standard
Specification as defined by Philips.
■Structure of This Manual
This manual consists of the following 24 chapters:
Chapter 1 Overview
This chapter gives an overview of the features and basic specification of the MB90550A/B
Series.
Chapter 2 CPU
This chapter describes the internal configuration of the CPU of the F2MC-16LX Series and
provides a specification of the hardware incorporated in the MB90550A/B Series.
Chapter 3 Interrupts
This chapter describes the functions and operation of interrupts.
Chapter 4 Generating and Resetting Clocks
This chapter describes the functions and operation for generating clock signals and resetting
clocks.
Chapter 5 Low-Power Consumption Control Circuit
This chapter describes the functions and operation of the low-power consumption control
circuit.
Chapter 6 Memory Access Modes
This chapter describes the internal and the external memory access mode of the F2MC-
16LX Series.

ii
Chapter 7 I/O Ports
This chapter describes the functions and operation of the I/O port.
Chapter 8 Time-Based Timer
This chapter describes the functions and operation of the time-base timer.
Chapter 9 Watchdog Timer
This chapter describes the functions and operation of the watchdog timer.
Chapter 10 16-Bit I/O Timer
This chapter describes the functions and operations of the 16-bit I/O timer.
Chapter 11 16-Bit Reload Timer (with the Event Count Function)
This chapter describes the functions and operation of the 16-bit reload timer containing the
event count function.
Chapter 12 8/16-Bit PPG
This chapter describes the functions and operation of the 8/16-bit PPG.
Chapter 13 DTP/External Interrupt
This chapter describes the functions and operation of the DTP/external interrupt circuit and
lists cautions in connection with its use.
Chapter 14 Delayed Interrupt Generating Module
This chapter describes the functions and operation of the delayed interrupt generation
module and lists cautions in connection with its use.
Chapter 15 A/D Converter
This chapter describes the functions and operation of the A/D converter and lists cautions in
connection with its use.
Chapter 16 Communication Prescaler Register
This chapter describes the functions and operations of the communication prescaler register.
Chapter 17 UART
This chapter describes the functions and operation of the UART, its application, and lists
cautions in connection with its use.
Chapter 18 I/O Extended Serial Interface
This chapter describes the functions and operation of the I/O extended serial interface.
Chapter 19 I2C Interface
This chapter describes the functions and operation of the I2C interface.
Chapter 20 Clock Monitor Function
This chapter describes the clock monitor function.
Chapter 21 Address Match Detection Function
This chapter describes the address match detection function and its operation.
Chapter 22 ROM Mirror Function Selection Module
This chapter describes the functions and operation of the ROM mirror function selection
module.
Chapter 23 1M-Bit Flash Memory
This chapter describes the functions and operation of the 1 Mb flash memory.

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Chapter 24 Example of MB90F553A Serial Programming Connection
This chapter provides examples of MB90F553A serial programming connections.
Appendix
The appendix lists the I/O map, instructions, OTPROM programming, and cautions in
connection with reset.

iv
Copyright © 1999-2007 FUJITSU LIMITED All rights reserved
• The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU semiconductor device; FUJITSU does not warrant
proper operation of the device with respect to use based on such information. When you develop equipment incorporating the
device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU
assumes no liability for any damages whatsoever arising out of the use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU or any
third party or does FUJITSU warrant non-infringement of any third-party's intellectual property right or other right by using such
information. FUJITSU assumes no liability for any infringement of the intellectual property rights or other rights of third parties
which would result from the use of information contained herein.
• The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in connection
with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
• Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
• The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

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CONTENTS
CHAPTER 1 OVERVIEW ................................................................................................... 1
1.1 Features .............................................................................................................................................. 2
1.2 Available Models ................................................................................................................................. 5
1.3 Block Diagram .................................................................................................................................... 6
1.4 External Dimensions of the Package .................................................................................................. 7
1.5 Pin Assignment ................................................................................................................................... 9
1.6 Description of the Pin Functions ....................................................................................................... 11
1.7 I/O Circuit Types ............................................................................................................................... 17
1.8 Cautions on Handling Devices .......................................................................................................... 21
CHAPTER 2 CPU ............................................................................................................ 25
2.1 Memory Space .................................................................................................................................. 26
2.2 Addressing ........................................................................................................................................ 27
2.3 Allocating Multiple-byte Data in a Memory Space ............................................................................ 30
2.4 Dedicated Registers ......................................................................................................................... 31
2.4.1 Accumulator (A) ........................................................................................................................... 33
2.4.2 User Stack Pointer (USP) and System Stack Pointer (SSP) ....................................................... 35
2.4.3 Processor Status (PS) ................................................................................................................. 36
2.4.4 Program Counter (PC) ................................................................................................................. 39
2.4.5 Direct Page Register (DPR) ........................................................................................................ 40
2.4.6 Bank registers (PCB, DTB, USB, SSB, ADB) .............................................................................. 41
2.5 General-purpose Registers ............................................................................................................... 42
2.6 Prefix Codes ..................................................................................................................................... 44
2.7 Interrupt Suppression Instructions and Prefix Codes ....................................................................... 46
2.8 Notes on Using the "DIV A, Ri" and "DIVW A, RWi" Instructions ..................................................... 47
CHAPTER 3 INTERRUPTS ............................................................................................. 51
3.1 Overview of Interrupts ....................................................................................................................... 52
3.2 Interrupt Causes ............................................................................................................................... 53
3.3 Interrupt Vectors ............................................................................................................................... 56
3.4 Hardware Interrupts .......................................................................................................................... 58
3.4.1 Operation of Hardware Interrupts ................................................................................................ 61
3.4.2 Operating Flow for Hardware Interrupts ...................................................................................... 64
3.4.3 Example of Procedure for Using Hardware Interrupts ................................................................. 65
3.5 Software Interrupts ........................................................................................................................... 66
3.6 Expanded Intelligent I/O Service (EI2OS) ......................................................................................... 68
3.6.1 Interrupt Control Register (ICR) ................................................................................................... 70
3.6.2 Expanded Intelligent I/O Service Descriptor (ISD) ...................................................................... 73
3.6.3 Operation of the Expanded Intelligent I/O Service (EI2OS) ......................................................... 77
3.6.4 Execution Time of the Expanded Intelligent I/O Service (EI2OS) ................................................ 79
3.7 Exceptions because of Executing Undefined Instructions ................................................................ 80

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CHAPTER 4 GENERATING AND RESETTING CLOCKS ............................................. 81
4.1 Clock Generator ................................................................................................................................ 82
4.2 Clock Supply Map ............................................................................................................................. 83
4.3 Reset Causes ................................................................................................................................... 84
4.4 Operation after a Reset is Released ................................................................................................. 86
4.5 Registers not Initialized by Reset Input ............................................................................................ 87
CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT .............................. 89
5.1 Overview of the Low-power Consumption Control Circuit ................................................................ 90
5.2 Low-power Consumption Mode Control Register (LPMCR) ............................................................. 93
5.3 Clock Selection Register (CKSCR) ................................................................................................... 95
5.4 Operation of the Low-power Consumption Control Circuit ............................................................... 98
5.4.1 Sleep Mode ............................................................................................................................... 100
5.4.2 Watch Mode .............................................................................................................................. 101
5.4.3 Stop Mode ................................................................................................................................. 103
5.4.4 Hardware Standby Mode ........................................................................................................... 104
5.4.5 Pin status in the Sleep, Stop, Hold, Reset, and Hardware Standby Modes .............................. 105
5.5 Intermittent CPU Operation Function .............................................................................................. 108
5.6 Setting the Oscillation Stabilization Time ........................................................................................ 109
5.7 Machine Clock ................................................................................................................................ 110
CHAPTER 6 MEMORY ACCESS MODES .................................................................... 113
6.1 Memory Access Mode Overview .................................................................................................... 114
6.1.1 Mode Pins .................................................................................................................................. 115
6.1.2 Mode Data ................................................................................................................................. 116
6.1.3 Memory Space for Each Bus Mode ........................................................................................... 117
6.2 External Memory Access (External Bus Pin Control Circuit) .......................................................... 120
6.2.1 Registers for External Memory Access (External Bus Pin Control Circuit) ................................ 121
6.2.2 Automatic Ready Function Selection Register (ARSR) ............................................................. 122
6.2.3 External Address Output Control Register (HACR) ................................................................... 124
6.2.4 Bus Control Signal Selection Register (ECSR) ......................................................................... 125
6.3 Operation of the External Memory Access Control Signals ............................................................ 128
6.3.1 Ready Function ......................................................................................................................... 130
6.3.2 Hold Function ............................................................................................................................ 132
CHAPTER 7 I/O PORTS ................................................................................................ 133
7.1 I/O Port Overview ........................................................................................................................... 134
7.2 I/O Port Block Diagram ................................................................................................................... 135
7.3 I/O Port Registers ........................................................................................................................... 138
7.3.1 Port Data Registers (PDRx) ...................................................................................................... 140
7.3.2 Port Data Direction Registers (DDRx) ....................................................................................... 142
7.3.3 Output Pin Register (ODR4) ...................................................................................................... 143
7.3.4 Input Resistor Registers (RDR0 and RDR1) ............................................................................. 144
7.3.5 Analog Input Enable Register (ADER) ...................................................................................... 145

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CHAPTER 8 TIME-BASED TIMER ............................................................................... 147
8.1 Overview of the Time-Based Timer ................................................................................................ 148
8.2 Time-Based Timer Control Register (TBTC) .................................................................................. 149
8.3 Time-Based Timer Operations ........................................................................................................ 151
CHAPTER 9 WATCHDOG TIMER ............................................................................... 153
9.1 Overview of the Watchdog Timer ................................................................................................... 154
9.2 Watchdog Timer Control Register (WDTC) .................................................................................... 155
9.3 Watchdog Timer Operations ........................................................................................................... 157
CHAPTER 10 16-BIT I/O TIMER ..................................................................................... 159
10.1 Overview of the 16-Bit I/O Timer .................................................................................................... 160
10.2 16-Bit I/O Timer Block Diagram ...................................................................................................... 162
10.3 16-Bit I/O Timer Registers .............................................................................................................. 163
10.3.1 16-bit Free-run Timer ................................................................................................................. 165
10.3.2 Output Compare ........................................................................................................................ 168
10.3.3 Input Capture ............................................................................................................................. 172
10.4 16-Bit Free-Run Timer Operations ................................................................................................. 174
10.5 16-Bit Output Compare Operations ................................................................................................ 176
10.6 16-Bit Input Capture Operations ..................................................................................................... 179
CHAPTER 11 16-BIT RELOAD TIMER (WITH THE EVENT COUNT FUNCTION)
................................................................................................................... 181
11.1 Overview of the 16-Bit Reload Timer (with the Event Count Function) .......................................... 182
11.2 Registers of the 16-Bit Reload Timer (with the Event Count Function) .......................................... 183
11.2.1 Timer Control Status Register (TMCSR) ................................................................................... 184
11.2.2 16-Bit Timer Register (TMR) and 16-Bit Reload Register (TMRLR) .......................................... 187
11.3 Clock Operations ............................................................................................................................ 188
11.4 Underflow Operation ....................................................................................................................... 189
11.5 I/O Pin Functions ............................................................................................................................ 190
11.6 Counter Operation Statuses ........................................................................................................... 192
CHAPTER 12 8/16-BIT PPG ........................................................................................... 193
12.1 Overview of the 8/16-Bit PPG ......................................................................................................... 194
12.2 Block Diagrams of the 8-Bit PPG .................................................................................................... 195
12.3 Registers in the 8/16-Bit PPG ......................................................................................................... 197
12.3.1 PPG0 Operation Mode Control Register (PPGC0) .................................................................... 198
12.3.2 PPG1 Operation Mode Control Register (PPGC1) .................................................................... 200
12.3.3 PPG0/1 Output Pin Control Register (PPGE) ............................................................................ 203
12.3.4 Reload Registers (PRLL/PRLH) ................................................................................................ 205
12.4 8/16-Bit PPG Operation .................................................................................................................. 206
12.4.1 8/16-bit PPG Operation Modes ................................................................................................. 208
12.4.2 PPG Output Operation .............................................................................................................. 209
12.4.3 Selecting a Count Clock ............................................................................................................ 211
12.4.4 Controlling Pulse Output on Pins ............................................................................................... 212
12.4.5 Write Timing for the Reload Registers ....................................................................................... 213

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CHAPTER 13 DTP/EXTERNAL INTERRUPT ................................................................. 215
13.1 Overview of the DTP/External Interrupt Circuit ............................................................................... 216
13.2 Registers in the DTP/External Interrupt Circuit ............................................................................... 218
13.3 Operation of DTP/External Interrupt Circuit .................................................................................... 221
13.4 Notes on Using the DTP/External Interrupt Circuit ......................................................................... 224
CHAPTER 14 DELAYED INTERRUPT GENERATING MODULE .................................. 227
14.1 Outline of the Delayed Interrupt Generating Module ...................................................................... 228
14.2 Operation of the Delayed Interrupt Generating Module .................................................................. 229
CHAPTER 15 A/D CONVERTER .................................................................................... 231
15.1 Overview of the A/D Converter ....................................................................................................... 232
15.2 Resisters of the A/D Converter ....................................................................................................... 235
15.2.1 Control Status Registers (ADCS0 and ADCS1) ........................................................................ 236
15.2.2 Data Register (ADCR1 and ADCR0) ......................................................................................... 240
15.3 Operation of A/D Converter ............................................................................................................ 242
15.3.1 Example of EI2OS Activation in Single Mode ............................................................................ 244
15.3.2 Example of EI2OS Activation in Successive Mode .................................................................... 246
15.3.3 Example of EI2OS Activation in Pause Mode ............................................................................ 248
15.4 Conversion Data Protection Function ............................................................................................. 250
CHAPTER 16 COMMUNICATION PRESCALER REGISTER ........................................ 253
16.1 Overview of Communication Prescaler Register ............................................................................ 254
16.2 Operation of Communication Prescaler Register ........................................................................... 256
CHAPTER 17 UART ........................................................................................................ 257
17.1 Overview of UART .......................................................................................................................... 258
17.2 UART Block Diagram ...................................................................................................................... 259
17.3 UART Registers .............................................................................................................................. 260
17.3.1 Serial Mode Register (SMR) ...................................................................................................... 261
17.3.2 Serial Control Register (SCR) ................................................................................................... 263
17.3.3 Serial Input Data Register (SIDR) and Serial Output Data Register (SODR) ............................ 266
17.3.4 Serial Status Register (SSR) ..................................................................................................... 267
17.4 UART Operations ........................................................................................................................... 270
17.4.1 UART Clock Selection ............................................................................................................... 271
17.4.2 Asynchronous (Start-stop Synchronous) Mode ......................................................................... 273
17.4.3 CLK-synchronous Mode ............................................................................................................ 275
17.4.4 Occurrence of Interrupt and Flag Setting Timing ....................................................................... 277
17.5 Application of UART (During Operation in Mode 1) ........................................................................ 280
CHAPTER 18 I/O EXTENDED SERIAL INTERFACE ..................................................... 283
18.1 Overview of the I/O Extended Serial Interface ................................................................................ 284
18.2 Registers of the I/O Extended Serial Interface ............................................................................... 286
18.2.1 Serial Mode Control Status Register (SMCS) ........................................................................... 287
18.2.2 Serial Shift Data Register (SDR) ............................................................................................... 291
18.3 Operation of I/O Extended Serial Interface ..................................................................................... 292
18.3.1 Shift Clock ................................................................................................................................. 293

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18.3.2 Operation States of the Serial I/O .............................................................................................. 295
18.3.3 Start/Stop Timing Of Shift Operation and Input/Output Timing ................................................. 297
18.3.4 Interrupt Function of the I/O Extended Serial Interface ............................................................. 300
CHAPTER 19 I2C INTERFACE ....................................................................................... 301
19.1 Overview of the I2C Interface .......................................................................................................... 302
19.2 Block Diagram and Structure of the I2C Interface ........................................................................... 303
19.3 Registers of the I2C Interface ......................................................................................................... 305
19.3.1 Bus Status Register (IBSR) ....................................................................................................... 306
19.3.2 Bus Control Register (IBCR) ..................................................................................................... 309
19.3.3 Clock Control Register (ICCR) .................................................................................................. 312
19.3.4 Address Register (IADR) ........................................................................................................... 314
19.3.5 Data Register (IDAR) ................................................................................................................. 315
19.3.6 Port Selection Register (ISEL) ................................................................................................... 316
19.4 Operation of the I2C Interface ......................................................................................................... 317
19.4.1 Flow of the I2C Interface Transmission ..................................................................................... 319
19.4.2 Flow of the I2C Interface Modes ................................................................................................ 321
CHAPTER 20 CLOCK MONITOR FUNCTION ................................................................ 323
20.1 Overview of the Clock Monitor Functions ....................................................................................... 324
20.2 Clock Output Permission Register (CLKR) ..................................................................................... 325
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION ......................................... 327
21.1 Overview of the Address Match Detection Function ....................................................................... 328
21.2 Registers of the Address Match Detection Function ....................................................................... 329
21.3 Operation of the Address Match Detection Function ...................................................................... 331
21.4 Example of the Address Match Detection Function ........................................................................ 332
21.5 Program Example of the Address Match Detection Function ......................................................... 334
CHAPTER 22 ROM MIRROR FUNCTION SELECTION MODULE ................................ 337
22.1 Overview of the ROM Mirror Function Selection Module ................................................................ 338
22.2 ROM Mirror Function Selection Register (ROMM) ......................................................................... 339
CHAPTER 23 1M-BIT FLASH MEMORY ........................................................................ 341
23.1 Overview of the 1M-Bit Flash Memory ............................................................................................ 342
23.2 Block Diagram and Sector Configuration of the Entire Flash Memory ........................................... 343
23.3 Writing and Deletion Modes ............................................................................................................ 345
23.4 Flash Memory Control Status Register (FMCS) ............................................................................. 347
23.5 Activating the Automatic Algorithm of the Flash Memory ............................................................... 349
23.6 Confirming the Automatic Algorithm Execution Status ................................................................... 350
23.6.1 Data Polling Flag (DQ7) ............................................................................................................ 352
23.6.2 Toggle Bit Flag (DQ6) ................................................................................................................ 354
23.6.3 Timing Limit Excess Flag (DQ5) ................................................................................................ 355
23.6.4 Sector Deletion Timer Flag (DQ3) ............................................................................................. 356
23.7 Detailed Explanations of Flash Memory Writing and Deletion ........................................................ 357
23.7.1 Setting the Flash Memory in the Read or Reset Status ............................................................ 358
23.7.2 Writing Data in the Flash Memory ............................................................................................. 359

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23.7.3 Deleting all Data Items from the Flash Memory (Chip Deletion) ................................................ 361
23.7.4 Deleting any Data Item from the Flash Memory (Sector Deletion) ............................................ 362
23.7.5 Temporarily Stopping the Sector Deletion from the Flash Memory .......................................... 364
23.7.6 Restarting the Flash Memory Sector Deletion ........................................................................... 365
23.8 Example of the 1M-Bit Flash Memory Program .............................................................................. 366
CHAPTER 24 EXAMPLE OF MB90F553A SERIAL PROGRAMMING CONNECTION
................................................................................................................... 371
24.1 Basic Configuration of MB90F553A Serial Programming Connection ............................................ 372
24.2 Example of Serial Programming Connection (When User Power Supply Is Used) ........................ 375
24.3 Example of Serial Programming Connection (When Power Is Supplied from a Writer) ................. 377
24.4 Example of Minimal Connection with the Flash Microcontroller Programmer
(When User Power Supply Is Used) ............................................................................................. 379
24.5 Example of Minimal Connection with the Flash Microcontroller Programmer
(When Power Is Supplied from a Writer) ......................................................................................... 381
APPENDIX ......................................................................................................................... 383
APPENDIX A I/O MAP ............................................................................................................................... 384
APPENDIX B Instructions ........................................................................................................................... 392
B.1 Instruction Types ............................................................................................................................ 393
B.2 Addressing ..................................................................................................................................... 394
B.3 Direct Addressing ........................................................................................................................... 396
B.4 Indirect Addressing ........................................................................................................................ 402
B.5 Execution Cycle Count ................................................................................................................... 410
B.6 Effective address field .................................................................................................................... 413
B.7 How to Read the Instruction List .................................................................................................... 414
B.8 F2MC-16LX Instruction List ............................................................................................................ 417
B.9 Instruction Map ............................................................................................................................... 431
APPENDIX C Programming the OTPROM ................................................................................................. 453
INDEX................................................................................................................................... 455

xi
Main changes in this edition
The vertical lines marked in the left side of the page show the changes.
Page Changes (For details, refer to main body.)
--Pin names were changed.
(TOUT→TOT)
24 CHAPTER 1 OVERVIEW
1.8 Cautions on Handling Devices
"❍Notes on operation in PLL clock mode" was
changed.
105 CHAPTER 5 LOW-POWER CONSUMPTION CON-
TROL CIRCUIT
5.4.5 Pin status in the Sleep, Stop, Hold, Reset, and
Hardware Standby Modes
"Table 5.4-2 Status of Each Pin in the Single Chip
Mode" was changed.
162 CHAPTER 10 16-BIT I/O TIMER
10.2 16-Bit I/O Timer Block Diagram
"Figure 10.2-1 16-bit I/O Timer Block Diagram" was
changed.
167 CHAPTER 10 16-BIT I/O TIMER
10.3.1 16-bit Free-run Timer
"[Bit 2] CLR" was changed.
218
CHAPTER 13 DTP/EXTERNAL INTERRUPT
13.2 Registers in the DTP/External Interrupt Circuit
"Note:" of "■Interrupt/DTP Enable Register
(ENIR)" was added.
219 "Notes:" of "■Interrupt/DTP Source Register
(EIRR)" was changed.
236 CHAPTER 15 A/D CONVERTER
15.2.1 Control Status Registers (ADCS0 and ADCS1)
"Note:" was changed.
"[Bit 14] INT (Interrupt)" was changed.
243 CHAPTER 15 A/D CONVERTER
15.3 Operation of A/D Converter
"Figure 15.3-1 Example of Flow from Activation of
A/D Conversion to Conversion Data Transfer
(Successive Mode)" was changed.
264 CHAPTER 17 UART
17.3.2 Serial Control Register (SCR)
"[Bit 10] REC (Receiver error clear)" was changed.
287 CHAPTER 18 I/O EXTENDED SERIAL INTERFACE
18.2.1 Serial Mode Control Status Register (SMCS)
"Figure 18.2-2 Serial Mode Control Status Register
(SMCS)" was changed.
306 CHAPTER 19 I2C INTERFACE
19.3.1 Bus Status Register (IBSR)
"[Bit 6] RSC (Repeated start condition)" was
changed.
342 CHAPTER 23 1M-BIT FLASH MEMORY
23.1 Overview of the 1M-Bit Flash Memory
"■Features of the 1M-bit Flash Memory" was
changed.
429 APPENDIX B Instructions
B.8 F2MC-16LX Instruction List
"Table B.8-17 6 Accumulator Operation Instructions
(Byte, Word)" was changed.

xii

1
CHAPTER 1 OVERVIEW
This chapter provides an overview of the MB90550A/B Series.
1.1 Features
1.2 Available Models
1.3 Block Diagram
1.4 External Dimensions of the Package
1.5 Pin Assignment
1.6 Description of the Pin Functions
1.7 I/O Circuit Types
1.8 Cautions on Handling Devices

2
CHAPTER 1 OVERVIEW
1.1 Features
The MB90550A/B Series is a general-purpose high-performance 16-bit microcontroller
that was designed for devices used in various industries, OA devices, and devices for
process control requiring high-speed real-time processing. In addition to inheriting
the F2MC-8 Series AT architecture, the MB90550A/B Series instruction system adds
support of high-level language instructions, expanded addressing modes, enhanced
multiplication and division instructions, and provides substantial bit processing
capabilities. By employing a 32-bit accumulator, this system also enables long-word
data processing.
■Features
The features of the MB90550A/B Series are shown below.
❍Minimum time for instruction execution
62.5 ns / 4 MHz, oscillation frequency multiplied by four (PLL clock multiplication system)
❍Maximum memory space
16 MB
❍Instruction system optimized for the controller
Data types that can be handled: bit/bytes/read/long word
Standard addressing modes: 23 types
Enhanced high-precision arithmetic operations by using a 32-bit accumulator
Enhanced signed multiplication and division instructions as well as an enhancement of the
functions for the reti command.
❍Instruction system supporting a high-level language (C) and multitasking
• Use of the system stack pointer
• Symmetrical instruction set and barrel shift instructions
❍Incorporation of an address match detection function (for two address pointers)
❍Improved execution speed
4-byte queue
❍Powerful interrupt functions
• Programmable setting of eight priority levels
• External interrupt input: 8 channels

3
1.1 Features
❍Data transfer function
• Intelligent I/O services: Up to 16 channels
• DTP request input: 8 channels
❍Internal ROM
• EPROM version, Flash version: 128 KB
• Mask ROM version: 64 KB/128 KB
❍Internal RAM
• EPROM version, Flash version: 4 KB
• Mask ROM version: 2 KB/4 KB
❍General-purpose ports
Up to 83 ports (allowing input pull-up register setting: 16 ports, allowing open-drain setting: 8
ports, I/O open-drain: 6 ports)
❍A/D converter
• RC sequential approximation type): 8 channels
• Resolution: 8 or 10 bits selectable, Conversion time 26.3 µs [minimum]
❍UART: 1 channel
❍Extended I/O serial interface: 2 channels
❍I2C interface: 2 channels
One of the two channels can be switched between terminal input/output. [For two systems]
❍16 bit reload timer: 2 channels
❍8/16-bit PPG: 3 channels
With function for switching between 8 bits ×2 channels and 16 bits ×1 channel mode
❍16-bit I/O timer configuration
• Input capture ×4 channels
• Output compare ×4 channels
• Free-run timer ×1 channel
❍Incorporation of a clock monitor function
Outputs a clock signal with segments of 21to 28
❍Time-base and watchdog timer: 18 bits

4
CHAPTER 1 OVERVIEW
❍Low-power consumption mode
• Sleep
•Stop
• Hardware standby mode
• CPU intermittent operation mode function
❍Package
• QFP-100
• LQFP-100
❍CMOS technology
❍Reduction in radiation noise (MB90550B Series)