GigaDevice Semiconductor GD32L23 Series User manual

GigaDevice Semiconductor Inc.
GD32L23x
Arm®Cortex®-M23 32-bit MCU
User Manual
Revision 1.0
( Oct 2021 )

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Table of Contents
Table of Contents...........................................................................................................2
List of Figures ..............................................................................................................18
List of Tables................................................................................................................24
1. System and memory architecture ........................................................................26
1.1. Arm®Cortex®-M23 processor ................................................................................... 26
1.2. System architecture .................................................................................................. 27
1.3. Memory map .............................................................................................................. 29
1.3.1. On-chip SRAM memory........................................................................................................ 32
1.3.2. On-chip Flash memory ......................................................................................................... 32
1.4. Boot configuration..................................................................................................... 33
1.5. System configuration controller (SYSCFG)............................................................. 33
1.6. System configuration registers................................................................................ 34
1.6.1. System configuration register 0 (SYSCFG_CFG0) .............................................................. 34
1.6.2. EXTI sources selection register 0 (SYSCFG_EXTISS0)...................................................... 35
1.6.3. EXTI sources selection register 1 (SYSCFG_EXTISS1)...................................................... 36
1.6.4. EXTI sources selection register 2 (SYSCFG_EXTISS2)...................................................... 38
1.6.5. EXTI sources selection register 3 (SYSCFG_EXTISS3)...................................................... 39
1.6.6. IRQ Latency register (SYSCFG_CPU_IRQ_LAT)................................................................ 40
1.7. Device electronic signature...................................................................................... 41
1.7.1. Memory density information.................................................................................................. 41
1.7.2. Unique device ID (96 bits) .................................................................................................... 41
2. Flash memory controller (FMC)............................................................................43
2.1. Overview .................................................................................................................... 43
2.2. Characteristics........................................................................................................... 43
2.3. Function overview..................................................................................................... 43
2.3.1. Flash memory architecture ................................................................................................... 43
2.3.2. Read operations ................................................................................................................... 45
2.3.3. Unlock the FMC_CTL register .............................................................................................. 46
2.3.4. Page erase............................................................................................................................ 47
2.3.5. Mass erase ........................................................................................................................... 48
2.3.6. Main flash programming ....................................................................................................... 49
2.3.7. Main flash fast programming ................................................................................................ 51
2.3.8. OTP programming ................................................................................................................ 53
2.3.9. Option bytes erase................................................................................................................ 53
2.3.10. Option bytes modify.............................................................................................................. 54

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2.3.11. Option bytes description ....................................................................................................... 54
2.3.12. Page erase / program protection.......................................................................................... 55
2.3.13. Security protection................................................................................................................ 56
2.3.14. LVE sequence....................................................................................................................... 56
2.4. Register definition..................................................................................................... 57
2.4.1. Wait state register (FMC_WS).............................................................................................. 57
2.4.2. Unlock key register (FMC_KEY)........................................................................................... 58
2.4.3. Option byte unlock key register (FMC_OBKEY)................................................................... 58
2.4.4. Status register (FMC_STAT)................................................................................................. 59
2.4.5. Control register (FMC_CTL)................................................................................................. 60
2.4.6. Address register (FMC_ADDR) ............................................................................................ 61
2.4.7. Option byte status register (FMC_OBSTAT)......................................................................... 61
2.4.8. Erase/Program protection register (FMC_WP)..................................................................... 62
2.4.9. Unlock flash sleep/power-down mode key register (FMC_SLPKEY)................................... 62
2.4.10. Product ID register (FMC_PID)............................................................................................. 63
3. Power management unit (PMU)............................................................................64
3.1. Overview .................................................................................................................... 64
3.2. Characteristics........................................................................................................... 64
3.3. Function overview..................................................................................................... 65
3.3.1. Battery backup domain......................................................................................................... 65
3.3.2. VDD/VDDA power domain........................................................................................................ 66
3.3.3. 1.1V power domain............................................................................................................... 69
3.3.4. Power saving modes ............................................................................................................ 70
3.4. Register definition..................................................................................................... 75
3.4.1. Control register 0 (PMU_CTL0)............................................................................................ 75
3.4.2. Control and status register (PMU_CS)................................................................................. 76
3.4.3. Control register 1 (PMU_CTL1)............................................................................................ 78
3.4.4. Status register (PMU_STAT)................................................................................................. 79
3.4.5. Parameter register (PMU_PAR) ........................................................................................... 80
4. Reset and clock unit (RCU)...................................................................................82
4.1. Reset control unit (RCTL) ......................................................................................... 82
4.1.1. Overview............................................................................................................................... 82
4.1.2. Function overview................................................................................................................. 82
4.2. Clock control unit (CCTL) ......................................................................................... 83
4.2.1. Overview............................................................................................................................... 83
4.2.2. Characteristics...................................................................................................................... 85
4.2.3. Function overview................................................................................................................. 85
4.3. Register definition..................................................................................................... 90
4.3.1. Control register (RCU_CTL)................................................................................................. 90
4.3.2. Configuration register 0 (RCU_CFG0) ................................................................................. 92

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4.3.3. Interrupt register (RCU_INT) ................................................................................................ 95
4.3.4. APB2 reset register (RCU_APB2RST)................................................................................. 98
4.3.5. APB1 reset register (RCU_APB1RST)................................................................................. 99
4.3.6. AHB enable register (RCU_AHBEN).................................................................................. 101
4.3.7. APB2 enable register (RCU_APB2EN) .............................................................................. 103
4.3.8. APB1 enable register (RCU_APB1EN) .............................................................................. 104
4.3.9. Backup domain control register (RCU_BDCTL)................................................................. 107
4.3.10. Reset source /clock register (RCU_RSTSCK) ................................................................... 108
4.3.11. AHB reset register (RCU_AHBRST)....................................................................................110
4.3.12. Configuration register 1 (RCU_CFG1) ................................................................................111
4.3.13. Configuration register 2 (RCU_CFG2) ................................................................................112
4.3.14. AHB2 enable register (RCU_AHB2EN)...............................................................................114
4.3.15. AHB2 reset register (RCU_AHB2RST) ...............................................................................114
4.3.16. Voltage key register (RCU_VKEY) ......................................................................................115
4.3.17. Low power mode LDO voltage register (RCU_LPLDO) ......................................................115
4.3.18. Low power bandgap mode register (RCU_LPB) .................................................................116
5. Clock trim controller (CTC)................................................................................. 117
5.1. Overview ...................................................................................................................117
5.2. Characteristics..........................................................................................................117
5.3. Function overview....................................................................................................117
5.3.1. REF sync pulse generator ...................................................................................................118
5.3.2. CTC trim counter..................................................................................................................118
5.3.3. Frequency evaluation and automatically trim process.........................................................119
5.3.4. Software program guide ..................................................................................................... 120
5.4. Register definition................................................................................................... 122
5.4.1. Control register 0 (CTC_CTL0)........................................................................................... 122
5.4.2. Control register 1 (CTC_CTL1)........................................................................................... 123
5.4.3. Status register (CTC_STAT)............................................................................................... 124
5.4.4. Interrupt clear register (CTC_INTC) ................................................................................... 126
6. Interrupt/event controller (EXTI).........................................................................128
6.1. Overview .................................................................................................................. 128
6.2. Characteristics......................................................................................................... 128
6.3. Interrupts function overview................................................................................... 128
6.4. External interrupt and event (EXTI) block diagram............................................... 131
6.5. External interrupt and Event function overview.................................................... 131
6.6. Register definition................................................................................................... 133
6.6.1. Interrupt enable register (EXTI_INTEN) ............................................................................. 133
6.6.2. Event enable register (EXTI_EVEN) .................................................................................. 133
6.6.3. Rising edge trigger enable register (EXTI_RTEN) ............................................................. 134

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6.6.4. Falling edge trigger enable register (EXTI_FTEN)............................................................. 134
6.6.5. Software interrupt event register (EXTI_SWIEV) ............................................................... 135
6.6.6. Pending register (EXTI_PD) ............................................................................................... 135
7. General-purpose and alternate-function I/Os (GPIO and AFIO).......................136
7.1. Overview .................................................................................................................. 136
7.2. Characteristics......................................................................................................... 136
7.3. Function overview................................................................................................... 136
7.3.1. GPIO pin configuration ....................................................................................................... 138
7.3.2. External interrupt/event lines.............................................................................................. 138
7.3.3. Alternate functions (AF)...................................................................................................... 139
7.3.4. Additional functions............................................................................................................. 139
7.3.5. Input configuration .............................................................................................................. 139
7.3.6. Output configuration ........................................................................................................... 139
7.3.7. Analog configuration........................................................................................................... 140
7.3.8. Alternate function (AF) configuration.................................................................................. 141
7.3.9. GPIO locking function......................................................................................................... 141
7.3.10. GPIO single cycle toggle function....................................................................................... 142
7.4. Register definition................................................................................................... 143
7.4.1. Port control register (GPIOx_CTL, x=A..D,F)..................................................................... 143
7.4.2. Port output mode register (GPIOx_OMODE, x=A..D,F)..................................................... 144
7.4.3. Port output speed register (GPIOx_OSPD, x=A..D,F)........................................................ 146
7.4.4. Port pull-up/down register (GPIOx_PUD, x=A..D,F)........................................................... 148
7.4.5. Port input status register (GPIOx_ISTAT, x=A..D,F)........................................................... 150
7.4.6. Port output control register (GPIOx_OCTL, x=A..D,F) ....................................................... 150
7.4.7. Port bit operate register (GPIOx_BOP, x=A..D,F)............................................................... 151
7.4.8. Port configuration lock register (GPIOx_LOCK, x=A..D,F)................................................. 151
7.4.9. Alternate function selected register 0 (GPIOx_AFSEL0, x=A..D,F) ................................... 152
7.4.10. Alternate function selected register 1 (GPIOx_AFSEL1, x=A..D,F) ................................... 153
7.4.11. Bit clear register (GPIOx_BC, x=A..D,F) ............................................................................ 154
7.4.12. Port bit toggle register (GPIOx_TG, x=A..D,F)................................................................... 155
8. CRC calculation unit (CRC).................................................................................156
8.1. Overview .................................................................................................................. 156
8.2. Characteristics......................................................................................................... 156
8.3. Function overview................................................................................................... 157
8.4. Register definition................................................................................................... 158
8.4.1. Data register (CRC_DATA)................................................................................................. 158
8.4.2. Free data register (CRC_FDATA)....................................................................................... 158
8.4.3. Control register (CRC_CTL)............................................................................................... 159
8.4.4. Initialization data register (CRC_IDATA)............................................................................. 159
8.4.5. Polynomial register (CRC_POLY)....................................................................................... 160

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9. True random number generator (TRNG)............................................................161
9.1. Overview .................................................................................................................. 161
9.2. Characteristics......................................................................................................... 161
9.3. Function overview................................................................................................... 161
9.3.1. Operation flow..................................................................................................................... 162
9.3.2. Error flags ........................................................................................................................... 162
9.4. Register definition................................................................................................... 163
9.4.1. Control register (TRNG_CTL)............................................................................................. 163
9.4.2. Status register (TRNG_STAT) ............................................................................................ 163
9.4.3. Data register (TRNG_DATA)............................................................................................... 164
10. Direct memory access controller (DMA).........................................................166
10.1. Overview............................................................................................................... 166
10.2. Characteristics..................................................................................................... 166
10.3. Block diagram ...................................................................................................... 167
10.4. Function overview................................................................................................ 167
10.4.1. DMA operation.................................................................................................................... 167
10.4.2. Peripheral handshake......................................................................................................... 169
10.4.3. Arbitration............................................................................................................................ 169
10.4.4. Address generation............................................................................................................. 170
10.4.5. Circular mode...................................................................................................................... 170
10.4.6. Memory to memory mode................................................................................................... 170
10.4.7. Channel configuration......................................................................................................... 170
10.4.8. Interrupt............................................................................................................................... 171
10.4.9. DMA request mapping ........................................................................................................ 171
10.5. Register definition................................................................................................ 172
10.5.1. Interrupt flag register (DMA_INTF)..................................................................................... 172
10.5.2. Interrupt flag clear register (DMA_INTC)............................................................................ 172
10.5.3. Channel x control register (DMA_CHxCTL) ....................................................................... 173
10.5.4. Channel x counter register (DMA_CHxCNT)...................................................................... 175
10.5.5. Channel x peripheral base address register (DMA_CHxPADDR)...................................... 176
10.5.6. Channel x memory base address register (DMA_CHxMADDR)........................................ 176
11. DMA request multiplexer (DMAMUX)..............................................................178
11.1. Overview............................................................................................................... 178
11.2. Characteristics..................................................................................................... 178
11.3. Block diagram ...................................................................................................... 179
11.4. Signal description................................................................................................ 179
11.5. Function overview................................................................................................ 180
11.5.1. DMAMUX request multiplexer ............................................................................................ 180

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11.5.2. DMAMUX request generator .............................................................................................. 183
11.5.3. Channel configurations....................................................................................................... 183
11.5.4. Interrupt............................................................................................................................... 184
11.5.5. DMAMUX mapping............................................................................................................. 184
11.6. Register definition................................................................................................ 189
11.6.1. Request multiplexer channel x configuration register (DMAMUX_RM_CHxCFG)............. 189
11.6.2. Request multiplexer channel interrupt flag register (DMAMUX_RM_INTF)....................... 190
11.6.3. Request multiplexer channel interrupt flag clear register (DMAMUX_RM_INTC).............. 191
11.6.4. Request generator channel x configuration register (DMAMUX_RG_CHxCFG) ............... 191
11.6.5. Request generator channel interrupt flag register (DMAMUX_RG_INTF)......................... 192
11.6.6. Rquest generator channel interrupt flag clear register (DMAMUX_RG_INTC).................. 193
12. Debug (DBG).....................................................................................................195
12.1. Overview............................................................................................................... 195
12.2. JTAG/SW function overview................................................................................ 195
12.2.1. Switch JTAG or SW interface ............................................................................................. 195
12.2.2. Pin assignment ................................................................................................................... 195
12.2.3. JTAG daisy chained structure............................................................................................. 196
12.2.4. Debug reset ........................................................................................................................ 196
12.2.5. JEDEC-106 ID code ........................................................................................................... 196
12.3. Debug hold function overview ............................................................................ 197
12.3.1. Debug support for power saving mode............................................................................... 197
12.3.2. Debug support for TIMER, LPTIMER, I2C, RTC, WWDGT and FWDGT .......................... 197
12.4. Register definition................................................................................................ 198
12.4.1. ID code register (DBG_ID).................................................................................................. 198
12.4.2. Control register 0 (DBG_CTL0).......................................................................................... 198
12.4.3. Control register 1 (DBG_CTL1).......................................................................................... 200
13. Analog to digital converter (ADC) ...................................................................202
13.1. Overview............................................................................................................... 202
13.2. Characteristics..................................................................................................... 202
13.3. Pins and internal signals..................................................................................... 203
13.4. Function overview................................................................................................ 204
13.4.1. Calibration (CLB) ................................................................................................................ 204
13.4.2. Dual clock domain architecture........................................................................................... 205
13.4.3. ADCON switch.................................................................................................................... 205
13.4.4. Regular and inserted channel groups................................................................................. 205
13.4.5. Conversion modes.............................................................................................................. 205
13.4.6. Inserted channel management........................................................................................... 210
13.4.7. Analog watchdog .................................................................................................................211
13.4.8. Data alignment.....................................................................................................................211
13.4.9. Programmable sampling time............................................................................................. 212

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13.4.10. External trigger.................................................................................................................... 213
13.4.11. DMA request ....................................................................................................................... 213
13.4.12. Temperature sensor and internal reference voltage VREFINT............................................... 214
13.4.13. Battery voltage monitoring.................................................................................................. 215
13.4.14. SLCD voltage monitoring.................................................................................................... 215
13.4.15. ADC interrupts .................................................................................................................... 215
13.4.16. Programmable resolution (DRES) - fast conversion mode ................................................ 215
13.4.17. On-chip hardware oversampling......................................................................................... 216
13.5. Register definition................................................................................................ 219
13.5.1. Status register (ADC_STAT)............................................................................................... 219
13.5.2. Control register 0 (ADC_CTL0) .......................................................................................... 220
13.5.3. Control register 1 (ADC_CTL1) .......................................................................................... 221
13.5.4. Sample time register 0 (ADC_SAMPT0) ............................................................................ 224
13.5.5. Sample time register 1 (ADC_SAMPT1) ............................................................................ 224
13.5.6. Inserted channel data offset register x (ADC_IOFFx) (x=0..3)........................................... 225
13.5.7. Watchdog high threshold register (ADC_WDHT)............................................................... 226
13.5.8. Watchdog low threshold register (ADC_WDLT) ................................................................. 226
13.5.9. Regular sequence register 0 (ADC_RSQ0)........................................................................ 227
13.5.10. Regular sequence register 1 (ADC_RSQ1)........................................................................ 227
13.5.11. Regular sequence register 2 (ADC_RSQ2)........................................................................ 228
13.5.12. Inserted sequence register (ADC_ISQ).............................................................................. 228
13.5.13. Inserted data register x (ADC_IDATAx) (x= 0..3)................................................................ 229
13.5.14. Regular data register (ADC_RDATA) ................................................................................. 229
13.5.15. Oversampling control register (ADC_OVSAMPCTL) ......................................................... 230
13.5.16. Charge control register (ADC_CCTL)................................................................................. 231
14. Digital-to-analog converter (DAC)...................................................................233
14.1. Introduction.......................................................................................................... 233
14.2. Main featuress...................................................................................................... 233
14.3. Function description............................................................................................ 234
14.3.1. DAC enable......................................................................................................................... 234
14.3.2. DAC output buffer............................................................................................................... 234
14.3.3. DAC data configuration....................................................................................................... 235
14.3.4. DAC trigger......................................................................................................................... 235
14.3.5. DAC conversion.................................................................................................................. 235
14.3.6. DAC noise wave ................................................................................................................. 235
14.3.7. DAC output voltage............................................................................................................. 236
14.3.8. DMA request ....................................................................................................................... 237
14.4. DAC registers....................................................................................................... 238
14.4.1. Control register 0 (DAC_CTL0) .......................................................................................... 238
14.4.2. Software trigger register (DAC_SWT) ................................................................................ 239
14.4.3. DAC_OUT 12-bit right-aligned data holding register (OUT_R12DH)................................. 240

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14.4.4. DAC_OUT 12-bit left-aligned data holding register (OUT_L12DH).................................... 240
14.4.5. DAC_OUT 8-bit right-aligned data holding register (OUT_R8DH)..................................... 241
14.4.6. DAC_OUT data output register (OUT_DO)........................................................................ 241
14.4.7. DAC Status register 0 (DAC_STAT0)................................................................................. 242
15. Watchdog timer (WDGT) ..................................................................................243
15.1. Free watchdog timer (FWDGT)............................................................................ 243
15.1.1. Overview............................................................................................................................. 243
15.1.2. Characteristics.................................................................................................................... 243
15.1.3. Function overview............................................................................................................... 243
15.1.4. Register definition............................................................................................................... 246
15.2. Window watchdog timer (WWDGT)..................................................................... 250
15.2.1. Overview............................................................................................................................. 250
15.2.2. Characteristics.................................................................................................................... 250
15.2.3. Function overview............................................................................................................... 250
15.2.4. Register definition............................................................................................................... 254
16. Real time clock (RTC).......................................................................................257
16.1. Overview............................................................................................................... 257
16.2. Characteristics..................................................................................................... 257
16.3. Function overview................................................................................................ 258
16.3.1. Block diagram..................................................................................................................... 258
16.3.2. Clock source and prescalers .............................................................................................. 259
16.3.3. Shadow registers introduction ............................................................................................ 259
16.3.4. Configurable and field maskable alarm .............................................................................. 259
16.3.5. Configurable periodic auto-wakeup counter....................................................................... 260
16.3.6. RTC initialization and configuration .................................................................................... 260
16.3.7. Calendar reading ................................................................................................................ 261
16.3.8. Resetting the RTC .............................................................................................................. 263
16.3.9. RTC shift function ............................................................................................................... 263
16.3.10. RTC reference clock detection ........................................................................................... 264
16.3.11. RTC smooth digital calibration............................................................................................ 264
16.3.12. Time-stamp function ........................................................................................................... 266
16.3.13. Tamper detection ................................................................................................................ 266
16.3.14. Calibration clock output ...................................................................................................... 269
16.3.15. Alarm output........................................................................................................................ 269
16.3.16. RTC pin configuration......................................................................................................... 269
16.3.17. RTC power saving mode management.............................................................................. 270
16.3.18. RTC interrupts..................................................................................................................... 271
16.4. Register definition................................................................................................ 272
16.4.1. Time register (RTC_TIME).................................................................................................. 272
16.4.2. Date register (RTC_DATE)................................................................................................. 272
16.4.3. Control register (RTC_CTL)................................................................................................ 273

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16.4.4. Status register (RTC_STAT) ............................................................................................... 276
16.4.5. Prescaler register (RTC_PSC) ........................................................................................... 278
16.4.6. Wakeup timer register (RTC_WUT).................................................................................... 278
16.4.7. Alarm 0 time and date register (RTC_ALRM0TD).............................................................. 279
16.4.8. Alarm 1 time and date register (RTC_ALRM1TD).............................................................. 280
16.4.9. Write protection key register (RTC_WPK).......................................................................... 281
16.4.10. Sub second register (RTC_SS) .......................................................................................... 282
16.4.11. Shift function control register (RTC_SHIFTCTL)................................................................ 282
16.4.12. Time of time stamp register (RTC_TTS)............................................................................. 283
16.4.13. Date of time stamp register (RTC_DTS)............................................................................. 284
16.4.14. Sub second of time stamp register (RTC_SSTS)............................................................... 284
16.4.15. High resolution frequency compensation register (RTC_HRFC) ....................................... 285
16.4.16. Tamper register (RTC_TAMP) ............................................................................................ 286
16.4.17. Alarm 0 sub second register (RTC_ALRM0SS) ................................................................. 289
16.4.18. Alarm 1 sub second register (RTC_ALRM1SS) ................................................................. 290
16.4.19. Backup registers (RTC_BKPx) (x=0..4).............................................................................. 291
17. Timer (TIMERx) .................................................................................................292
17.1. General level0 timer (TIMERx, x=1, 2)................................................................. 293
17.1.1. Overview............................................................................................................................. 293
17.1.2. Characteristics.................................................................................................................... 293
17.1.3. Block diagram..................................................................................................................... 293
17.1.4. Function overview............................................................................................................... 294
17.1.5. TIMERx registers(x=1, 2).................................................................................................... 317
17.2. General level1 timer (TIMERx, x=8, 11) ............................................................... 340
17.2.1. Overview............................................................................................................................. 340
17.2.2. Characteristics.................................................................................................................... 340
17.2.3. Block diagram..................................................................................................................... 341
17.2.4. Function overview............................................................................................................... 341
17.2.5. TIMERx registers(x=8, 11).................................................................................................. 353
17.3. Basic timer (TIMERx, x=5, 6)................................................................................ 367
17.3.1. Overview............................................................................................................................. 367
17.3.2. Characteristics.................................................................................................................... 367
17.3.3. Block diagram..................................................................................................................... 367
17.3.4. Function overview............................................................................................................... 367
17.3.5. TIMERx registers(x=5,6)..................................................................................................... 372
18. Low power timer (LPTIMER)............................................................................377
18.1. Overview............................................................................................................... 377
18.2. Characteristics..................................................................................................... 377
18.3. Block diagram ...................................................................................................... 378
18.4. Function overview................................................................................................ 378

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18.4.1. Clock selection.................................................................................................................... 378
18.4.2. LPTIMER enable ................................................................................................................ 380
18.4.3. Prescaler............................................................................................................................. 380
18.4.4. Input filter............................................................................................................................ 381
18.4.5. External inputs high level counter....................................................................................... 381
18.4.6. Start counting mode............................................................................................................ 382
18.4.7. External trigger mapping..................................................................................................... 383
18.4.8. Operating mode.................................................................................................................. 383
18.4.9. Output Mode....................................................................................................................... 385
18.4.10. Timeout function ................................................................................................................. 386
18.4.11. Decoder mode .................................................................................................................... 387
18.4.12. Register update................................................................................................................... 392
18.4.13. Low-power modes .............................................................................................................. 392
18.4.14. Interrupts............................................................................................................................. 393
18.4.15. LPTIMER debug mode ....................................................................................................... 394
18.5. LPTIMER registers ............................................................................................... 395
18.5.1. Interrupt flag register (LPTIMER_INTF) ............................................................................. 395
18.5.2. Interrupt flag clear register (LPTIMER_INTC) .................................................................... 397
18.5.3. Interrupt enable register (LPTIMER_INTEN)...................................................................... 398
18.5.4. Control register 0 (LPTIMER_CTL0) .................................................................................. 400
18.5.5. Control register 1 (LPTIMER_CTL1) .................................................................................. 404
18.5.6. Compare value register (LPTIMER_CMPV)....................................................................... 405
18.5.7. Counter auto reload register (LPTIMER_CAR) .................................................................. 405
18.5.8. Counter register (LPTIMER_CNT)...................................................................................... 406
18.5.9. External input remap register (LPTIMER_EIRMP)............................................................. 406
18.5.10. Input high level counter max value register (LPTIMER_INHLCMV)................................... 407
19. Universal synchronous/asynchronous receiver /transmitter (USART)........408
19.1. Overview............................................................................................................... 408
19.2. Characteristics..................................................................................................... 408
19.3. Function overview................................................................................................ 410
19.3.1. USART frame format .......................................................................................................... 410
19.3.2. Baud rate generation ...........................................................................................................411
19.3.3. USART transmitter.............................................................................................................. 412
19.3.4. USART receiver.................................................................................................................. 413
19.3.5. Use DMA for data buffer access......................................................................................... 415
19.3.6. Hardware flow control......................................................................................................... 416
19.3.7. Multi-processor communication.......................................................................................... 417
19.3.8. LIN mode ............................................................................................................................ 418
19.3.9. Synchronous mode............................................................................................................. 419
19.3.10. IrDA SIR ENDEC mode ...................................................................................................... 420
19.3.11. Half-duplex communication mode ...................................................................................... 421
19.3.12. Smartcard (ISO7816-3) mode ............................................................................................ 421

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19.3.13. Auto baudrate detection...................................................................................................... 423
19.3.14. ModBus communication ..................................................................................................... 424
19.3.15. Receive FIFO...................................................................................................................... 424
19.3.16. Wakeup from Deep-sleep mode......................................................................................... 425
19.3.17. USART interrupts................................................................................................................ 425
19.4. Register definition................................................................................................ 427
19.4.1. Control register 0 (USART_CTL0)...................................................................................... 427
19.4.2. Control register 1 (USART_CTL1)...................................................................................... 429
19.4.3. Control register 2 (USART_CTL2)...................................................................................... 432
19.4.4. Baud rate generator register (USART_BAUD)................................................................... 435
19.4.5. Prescaler and guard time configuration register (USART_GP).......................................... 435
19.4.6. Receiver timeout register (USART_RT) ............................................................................. 436
19.4.7. Command register (USART_CMD) .................................................................................... 437
19.4.8. Status register (USART_STAT) .......................................................................................... 438
19.4.9. Interrupt status clear register (USART_INTC).................................................................... 442
19.4.10. Receive data register (USART_RDATA) ............................................................................ 443
19.4.11. Transmit data register (USART_TDATA)............................................................................ 444
19.4.12. USART coherence control register (USART_CHC)............................................................ 444
19.4.13. USART receive FIFO control and status register (USART_RFCS).................................... 445
20. Low-power universal asynchronous receiver /transmitter (LPUART) .........447
20.1. Overview............................................................................................................... 447
20.2. Characteristics..................................................................................................... 447
20.3. Function overview................................................................................................ 448
20.3.1. LPUART frame format ........................................................................................................ 449
20.3.2. Baud rate generation .......................................................................................................... 450
20.3.3. LPUART transmitter............................................................................................................ 451
20.3.4. LPUART receiver................................................................................................................ 452
20.3.5. Use DMA for data buffer access......................................................................................... 453
20.3.6. Hardware flow control......................................................................................................... 455
20.3.7. Multi-processor communication.......................................................................................... 457
20.3.8. Half-duplex communication mode ...................................................................................... 457
20.3.9. Wakeup from Deep-sleep mode......................................................................................... 457
20.3.10. LPUART interrupts.............................................................................................................. 458
20.4. Register definition................................................................................................ 460
20.4.1. Control register 0 (LPUART_CTL0).................................................................................... 460
20.4.2. Control register 1 (LPUART_CTL1).................................................................................... 462
20.4.3. Control register 2 (LPUART_CTL2).................................................................................... 464
20.4.4. Baud rate generator register (LPUART_BAUD)................................................................. 466
20.4.5. Command register (LPUART_CMD) .................................................................................. 466
20.4.6. Status register (LPUART_STAT) ........................................................................................ 467
20.4.7. Interrupt status clear register (LPUART_INTC).................................................................. 470

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20.4.8. Receive data register (LPUART_RDATA) .......................................................................... 471
20.4.9. Transmit data register (LPUART_TDATA).......................................................................... 471
20.4.10. Coherence control register (LPUART_CHC)...................................................................... 472
21. Inter-integrated circuit interface (I2C).............................................................473
21.1. Overview............................................................................................................... 473
21.2. Characteristics..................................................................................................... 473
21.3. Function overview................................................................................................ 473
21.3.1. Clock requirements............................................................................................................. 474
21.3.2. I2C communication flow...................................................................................................... 475
21.3.3. Noise filter........................................................................................................................... 478
21.3.4. I2C timings.......................................................................................................................... 478
21.3.5. Software reset..................................................................................................................... 480
21.3.6. Data transfer....................................................................................................................... 480
21.3.7. I2C slave mode................................................................................................................... 483
21.3.8. I2C master mode ................................................................................................................ 488
21.3.9. SMBus support ................................................................................................................... 493
21.3.10. SMBus mode ...................................................................................................................... 496
21.3.11. Wakeup from Deep-sleep mode......................................................................................... 498
21.3.12. Use DMA for data transfer .................................................................................................. 498
21.3.13. I2C error and interrupts....................................................................................................... 499
21.3.14. I2C debug mode ................................................................................................................. 499
21.4. Register definition................................................................................................ 500
21.4.1. Control register 0 (I2C_CTL0) ............................................................................................ 500
21.4.2. Control register 1 (I2C_CTL1) ............................................................................................ 502
21.4.3. Slave address register 0 (I2C_SADDR0) ........................................................................... 504
21.4.4. Slave address register 1 (I2C_SADDR1) ........................................................................... 505
21.4.5. Timing register (I2C_TIMING) ............................................................................................ 506
21.4.6. Timeout register (I2C_TIMEOUT)....................................................................................... 507
21.4.7. Status register (I2C_STAT)................................................................................................. 508
21.4.8. Status clear register (I2C_STATC) ......................................................................................511
21.4.9. PEC register (I2C_PEC)..................................................................................................... 512
21.4.10. Receive data register (I2C_RDATA)................................................................................... 512
21.4.11. Transmit data register (I2C_TDATA)................................................................................... 513
21.4.12. Control register 2 (I2C_CTL2) ............................................................................................ 513
22. Serial peripheral interface/Inter-IC sound (SPI/I2S).......................................514
22.1. Overview............................................................................................................... 514
22.2. Characteristics..................................................................................................... 514
22.2.1. SPI characteristics.............................................................................................................. 514
22.2.2. I2S characteristics .............................................................................................................. 514
22.3. SPI block diagram................................................................................................ 515

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22.4. SPI signal description.......................................................................................... 515
22.4.1. Normal configuration (Not Quad-SPI Mode)....................................................................... 515
22.4.2. Quad-SPI configuration ...................................................................................................... 516
22.5. SPI function overview.......................................................................................... 516
22.5.1. SPI clock timing and data format........................................................................................ 516
22.5.2. RXFIFO and TXFIFO.......................................................................................................... 518
22.5.3. NSS function....................................................................................................................... 519
22.5.4. SPI operation modes .......................................................................................................... 520
22.5.5. DMA function....................................................................................................................... 529
22.5.6. CRC function....................................................................................................................... 530
22.6. SPI interrupts........................................................................................................ 530
22.6.1. Status flags......................................................................................................................... 530
22.6.2. Error conditions................................................................................................................... 531
22.7. I2S block diagram ................................................................................................ 532
22.8. I2S signal description.......................................................................................... 533
22.9. I2S function overview .......................................................................................... 533
22.9.1. I2S audio standards............................................................................................................ 533
22.9.2. I2S clock ............................................................................................................................. 541
22.9.3. Operation............................................................................................................................ 542
22.9.4. DMA function....................................................................................................................... 545
22.10. I2S interrupts........................................................................................................ 545
22.10.1. Status flags......................................................................................................................... 545
22.10.2. Error conditions................................................................................................................... 545
22.11. Register definition................................................................................................ 547
22.11.1. Control register 0 (SPI_CTL0)............................................................................................ 547
22.11.2. Control register 1 (SPI_CTL1)............................................................................................ 549
22.11.3. Status register (SPI_STAT)................................................................................................. 551
22.11.4. Data register (SPI_DATA)................................................................................................... 552
22.11.5. CRC polynomial register (SPI_CRCPOLY) ........................................................................ 553
22.11.6. Receive CRC register (SPI_RCRC) ................................................................................... 553
22.11.7. Transmit CRC register (SPI_TCRC)................................................................................... 554
22.11.8. I2S control register (SPI_I2SCTL)...................................................................................... 555
22.11.9. I2S clock prescaler register (SPI_I2SPSC) ........................................................................ 556
22.11.10.Quad-SPI mode control register (SPI_QCTL) of SPI0 ....................................................... 557
23. Cryptographic Acceleration Unit (CAU)..........................................................559
23.1. Overview............................................................................................................... 559
23.2. Characteristics..................................................................................................... 559
23.3. CAU data type and initialization vectors ............................................................ 560
23.3.1. Data type............................................................................................................................. 560
23.3.2. Initialization vectors ............................................................................................................ 561

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23.4. Cryptographic acceleration processor............................................................... 561
23.4.1. DES/TDES cryptographic acceleration processor.............................................................. 562
23.4.2. AES cryptographic acceleration processor......................................................................... 566
23.5. Operating modes.................................................................................................. 574
23.6. CAU DMA interface .............................................................................................. 575
23.7. CAU interrupts...................................................................................................... 576
23.8. CAU suspended mode......................................................................................... 576
23.9. Register definition................................................................................................ 578
23.9.1. Control register (CAU_CTL) ............................................................................................... 578
23.9.2. Status register 0 (CAU_STAT0).......................................................................................... 580
23.9.3. Data input register (CAU_DI).............................................................................................. 580
23.9.4. Data output register (CAU_DO).......................................................................................... 581
23.9.5. DMA enable register (CAU_DMAEN)................................................................................. 582
23.9.6. Interrupt enable register (CAU_INTEN).............................................................................. 582
23.9.7. Status register 1 (CAU_STAT1).......................................................................................... 583
23.9.8. Interrupt flag register (CAU_INTF)...................................................................................... 583
23.9.9. Key registers (CAU_KEY0..3(H/L))..................................................................................... 584
23.9.10. Initial vector registers (CAU_IV0..1(H/L)) ........................................................................... 586
23.9.11. GCM or CCM mode context switch register x (CAU_GCMCCMCTXSx) (x=0..7).............. 588
23.9.12. GCM mode context switch register x (CAU_GCMCTXSx) (x=0..7) ................................... 588
24. VREF..................................................................................................................590
24.1. Overview............................................................................................................... 590
24.2. Characteristics..................................................................................................... 590
24.3. Function overview................................................................................................ 590
24.4. Register definition................................................................................................ 591
24.4.1. Control and status register (VREF_CS) ............................................................................. 591
24.4.2. Calibration register (VREF_CALIB).................................................................................... 592
25. Segment LCD controller (SLCD)......................................................................593
25.1. Overview............................................................................................................... 593
25.2. Characteristics..................................................................................................... 593
25.3. Function overview................................................................................................ 593
25.3.1. SLCD Architecture .............................................................................................................. 593
25.3.2. Clock generator................................................................................................................... 594
25.3.3. Blink control ........................................................................................................................ 595
25.3.4. SEG/COM Driver ................................................................................................................ 595
25.3.5. Double buffer memory ........................................................................................................ 598
25.3.6. ANALOG matrix.................................................................................................................. 598
25.3.7. VSLCD voltage monitoring..................................................................................................... 599

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25.4. Register definition................................................................................................ 600
25.4.1. Control register (SLCD_CTL) ............................................................................................. 600
25.4.2. Configuration register (SLCD_CFG)................................................................................... 601
25.4.3. Status flag register (SLCD_STAT)...................................................................................... 603
25.4.4. Status flag clear register (SLCD_STATC)........................................................................... 604
25.4.5. Display data registers (SLCD_DATAx) (x=0…7) ................................................................ 605
26. Comparator (CMP)............................................................................................606
26.1. Overview............................................................................................................... 606
26.2. Characteristic....................................................................................................... 606
26.3. Function overview................................................................................................ 606
26.3.1. CMP clock and reset........................................................................................................... 607
26.3.2. CMP inputs and outputs ..................................................................................................... 607
26.3.3. CMP power and speed mode ............................................................................................. 608
26.3.4. CMP windows mode........................................................................................................... 608
26.3.5. CMP hysteresis................................................................................................................... 608
26.3.6. CMP output blanking........................................................................................................... 609
26.3.7. CMP register write protection ............................................................................................. 610
26.4. CMP registers........................................................................................................611
26.4.1. Comparator 0 Control / Status register (CMP0_CS) ...........................................................611
26.4.2. Comparator 1 Control / Status register (CMP1_CS) .......................................................... 613
27. Universal Serial Bus full-speed device interface (USBD)..............................616
27.1. Overview............................................................................................................... 616
27.2. Main features........................................................................................................ 616
27.3. Block diagram ...................................................................................................... 616
27.4. Signal description................................................................................................ 617
27.5. Clock configuration.............................................................................................. 617
27.6. Function overview................................................................................................ 617
27.6.1. USB endpoints.................................................................................................................... 617
27.6.2. Operation procedure........................................................................................................... 620
27.6.3. USB events and interrupts.................................................................................................. 623
27.6.4. Operation guide .................................................................................................................. 625
27.7. Registers definition.............................................................................................. 627
27.7.1. USBD control register (USBD_CTL)................................................................................... 627
27.7.2. USBD interrupt flag register (USBD_INTF) ........................................................................ 628
27.7.3. USBD status register (USBD_STAT).................................................................................. 630
27.7.4. USBD device address register (USBD_DADDR) ............................................................... 630
27.7.5. USBD buffer address register (USBD_BADDR)................................................................. 631
27.7.6. USBD endpoint x control and status register (USBD_EPxCS), x=[0..7] ............................ 631
27.7.7. USBD endpoint x transmission buffer address register (USBD_EPxTBADDR), x can be in

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[0..7] 633
27.7.8. USBD endpoint x transmission buffer byte count register (USBD_EPxTBCNT), x can be in
[0..7] 633
27.7.9. USBD endpoint x reception buffer address register (USBD_EPxRBADDR), x can be in [0..7]
634
27.7.10. USBD endpoint x reception buffer byte count register (USBD_EPxRBCNT), x can be in
[0..7] 634
27.7.11. USBD LPM control and status register (USBD_LPMCS)................................................... 635
27.7.12. USBD DP pull-up control register (USBD_DPC)................................................................ 635
28. Document appendix .........................................................................................637
28.1. List of abbreviations used in registers............................................................... 637
28.2. List of terms.......................................................................................................... 637
28.3. Available peripherals ........................................................................................... 637
29. Revision history................................................................................................638

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List of Figures
Figure 1-1. The structure of the Arm®Cortex®-M23 processor ............................................. 27
Figure 1-2. Series system architecture of GD32L23x series.................................................. 29
Figure 2-1. Process of page erase operation........................................................................... 48
Figure 2-2. Process of mass erase operation.......................................................................... 49
Figure 2-3. Process of word program operation ..................................................................... 51
Figure 2-4. Process of fast program operation........................................................................ 52
Figure 3-1. Power supply overview........................................................................................... 65
Figure 3-2. Waveform of the POR/PDR..................................................................................... 67
Figure 3-3. Waveform of the BOR ............................................................................................. 68
Figure 3-4. Waveform of the LVD threshold............................................................................. 69
Figure 4-1. The system reset circuit ......................................................................................... 83
Figure 4-2. Clock tree ................................................................................................................. 84
Figure 4-3. HXTAL clock source................................................................................................ 85
Figure 5-1. CTC overview..........................................................................................................118
Figure 5-2. CTC trim counter ....................................................................................................119
Figure 6-1. Block diagram of EXTI .......................................................................................... 131
Figure 7-1. Basic structure of a standard I/O port bit........................................................... 138
Figure 7-2. Input configuration................................................................................................ 139
Figure 7-3. Output configuration............................................................................................. 140
Figure 7-4. Analog configuration ............................................................................................ 140
Figure 7-5. Alternate function configuration.......................................................................... 141
Figure 8-1. Block diagram of CRC calculation unit............................................................... 156
Figure 9-1. TRNG block diagram............................................................................................. 161
Figure 10-1. Block diagram of DMA........................................................................................ 167
Figure 10-2. Handshake mechanism....................................................................................... 169
Figure 10-3. DMA interrupt logic ............................................................................................. 171
Figure 11-1. Block diagram of DMAMUX................................................................................ 179
Figure 11-2. Synchronization mode........................................................................................ 181
Figure 11-3. Event generation.................................................................................................. 182
Figure 13-1. ADC module block diagram................................................................................ 204
Figure 13-2. Single conversion mode..................................................................................... 206
Figure 13-3. Continuous conversion mode............................................................................ 207
Figure 13-4. Scan conversion mode, continuous disable.................................................... 208
Figure 13-5. Scan conversion mode, continuous enable..................................................... 208
Figure 13-6. Discontinuous conversion mode....................................................................... 209
Figure 13-7. Auto-insertion, CTN = 1 ...................................................................................... 210
Figure 13-8. Triggered insertion.............................................................................................. 210
Figure 13-9. Data alignment of 12-bit resolution....................................................................211
Figure 13-10. Data alignment of 10-bit resolution................................................................. 212
Figure 13-11. Data alignment of 8-bit resolution ................................................................... 212

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Figure 13-12. Data alignment of 6-bit resolution................................................................... 212
Figure 13-13. 20-bit to 16-bit result truncation ...................................................................... 216
Figure 13-14. A numerical example with 5-bit shifting and rounding................................. 217
Figure 14-1. DAC block diagram ............................................................................................. 234
Figure 14-2. DAC LFSR algorithm........................................................................................... 236
Figure 14-3. DAC triangle noise wave..................................................................................... 236
Figure 15-1. Free watchdog block diagram............................................................................ 244
Figure 15-2. Window watchdog timer block diagram ........................................................... 251
Figure 15-3. Window watchdog timing diagram.................................................................... 252
Figure 16-1. Block diagram of RTC......................................................................................... 258
Figure 17-1. General Level 0 timer block diagram ................................................................ 294
Figure 17-2. Normal mode, internal clock divided by 1........................................................ 295
Figure 17-3. Counter timing diagram with prescaler division change from 1 to 2 ............ 296
Figure 17-4. Timing chart of up counting mode, PSC=0/1 ................................................... 297
Figure 17-5. Timing chart of up counting, change TIMERx_CAR ongoing ........................ 298
Figure 17-6. Timing chart of down counting mode, PSC=0/1 .............................................. 299
Figure 17-7. Timing chart of down counting mode, change TIMERx_CAR ongoing......... 300
Figure 17-8. Timing chart of center-aligned counting mode................................................ 301
Figure 17-9. Input capture logic .............................................................................................. 302
Figure 17-10. Output compare logic (x=0,1,2,3)..................................................................... 303
Figure 17-11. Output-compare under three modes............................................................... 304
Figure 17-12. Timing chart of EAPWM.................................................................................... 305
Figure 17-13. Timing chart of CAPWM.................................................................................... 306
Figure 17-14. Example of counter operation in encoder interface mode........................... 308
Figure 17-15. Example of encoder interface mode with CI0FE0 polarity inverted ............ 308
Figure 17-16. Restart mode...................................................................................................... 309
Figure 17-17. Pause mode........................................................................................................ 310
Figure 17-18. Event mode ........................................................................................................ 310
Figure 17-19. Single pulse mode TIMERx_CHxCV = 0x04, TIMERx_CAR=0x60 .................311
Figure 17-20. TIMER1 Master/Slave mode timer example.................................................... 312
Figure 17-21. Triggering TIMER1 with Enable of TIMER2..................................................... 313
Figure 17-22. Triggering TIMER1 with update signal of TIMER2......................................... 313
Figure 17-23. Pause TIMER1 with enable of TIMER2............................................................ 314
Figure 17-24. Pause TIMER1 with O0CPREof TIMER2.......................................................... 315
Figure 17-25. Triggering TIMER0 and TIMER2 with TIMER2’s CI0 input............................. 316
Figure 17-26. General level1 timer block diagram................................................................. 341
Figure 17-27. Normal mode, internal clock divided by 1...................................................... 342
Figure 17-28. Counter timing diagram with prescaler division change from 1 to 2 .......... 343
Figure 17-29. Up-counter timechart, PSC=0/1 ....................................................................... 344
Figure 17-30. Up-counter timechart, change TIMERx_CAR on the go................................ 344
Figure 17-31. Input capture logic ............................................................................................ 345
Figure 17-32. Output-compare under three modes............................................................... 347
Figure 17-33. EAPWM timechart.............................................................................................. 348
Figure 17-34. CAPWM timechart ............................................................................................. 348

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Figure 17-35. Restart mode...................................................................................................... 350
Figure 17-36. Pause mode........................................................................................................ 350
Figure 17-37. Event mode ........................................................................................................ 351
Figure 17-38. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60 ................. 352
Figure 17-39. Basic timer block diagram................................................................................ 367
Figure 17-40. Normal mode, internal clock divided by 1...................................................... 368
Figure 17-41. Counter timing diagram with prescaler division change from 1 to 2 .......... 369
Figure 17-42. Timing chart of up counting mode, PSC=0/1 ................................................. 370
Figure 17-43. Timing chart of up counting mode, change TIMERx_CAR ongoing............ 371
Figure 18-1. LPTIMER block diagram ..................................................................................... 378
Figure 18-2. LPTIMER clock source selection....................................................................... 379
Figure 18-3. Internal clock mode1 (CKSSEL = 0 and CNTMEN = 1 and PSC[2:0] = 000).. 380
Figure 18-4. Input filter timing diagram (ECKFLT=2’b01)..................................................... 381
Figure 18-5. External inputs high level counter..................................................................... 382
Figure 18-6. LPTIMER output with SMST = 1......................................................................... 384
Figure 18-7. LPTIMER output with OMSEL = 1 ...................................................................... 384
Figure 18-8. LPTIMER output with CTNMST = 1.................................................................... 385
Figure 18-9. LPTIMER_O output mode with OPSEL bit........................................................ 386
Figure 18-10. LPTIMER timeout mode.................................................................................... 387
Figure 18-11. Counter operation in decoder mode 0 with rising-edge-mode..................... 388
Figure 18-12. Counter operation in decoder mode 0 with falling-edge-mode.................... 389
Figure 18-13. Counter operation in decoder mode 1 with non-inverted............................. 390
Figure 18-14. Counter operation in decoder mode 1 with non-inverted(IN1EIF)............... 390
Figure 18-15. Counter operation in decoder mode 1 with non-inverted(IN0EIF)............... 391
Figure 18-16. Counter operation in decoder mode 1 with non-inverted(INRFOEIF) ......... 391
Figure 18-17. Counter operation in decoder mode 1 with non-inverted(INHLOEIF) ......... 391
Figure 19-1. USART module block diagram........................................................................... 410
Figure 19-2. USART character frame (8 bits data and 1 stop bit).........................................411
Figure 19-3. USART transmit procedure ................................................................................ 413
Figure 19-4. Oversampling method of a receive frame bit (OSB=0).................................... 414
Figure 19-5. Configuration step when using DMA for USART transmission..................... 415
Figure 19-6. Configuration step when using DMA for USART reception............................ 416
Figure 19-7. Hardware flow control between two USARTs................................................... 416
Figure 19-8. Hardware flow control......................................................................................... 417
Figure 19-9. Break frame occurs during idle state................................................................ 419
Figure 19-10. Break frame occurs during a frame................................................................. 419
Figure 19-11. Example of USART in synchronous mode ..................................................... 419
Figure 19-12. 8-bit format USART synchronous waveform (CLEN=1)................................ 420
Figure 19-13. IrDA SIR ENDEC module................................................................................... 420
Figure 19-14. IrDA data modulation........................................................................................ 421
Figure 19-15. ISO7816-3 frame format.................................................................................... 422
Figure 19-16. USART Receive FIFO structure........................................................................ 424
Figure 19-17. USART interrupt mapping diagram................................................................. 426
Figure 20-1. LPUART module block diagram......................................................................... 449