GigaDevice Semiconductor GD32H737 User manual

GigaDevice Semiconductor Inc.
GD32H737/757/759
Arm® Cortex®-M7 32-bit MCU
User Manual
Revision 1.0
(May. 2023)

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Table of Contents
Table of Contents ...........................................................................................................2
List of Figures ..............................................................................................................38
List of Tables ................................................................................................................52
1. System and memory architecture ........................................................................59
1.1. Arm®Cortex®-M7 processor ..................................................................................... 59
1.2. System architecture .................................................................................................. 60
1.2.1. Bus matrix Region 0 ............................................................................................................. 63
1.2.2. Bus matrix Region 1 ............................................................................................................. 63
1.2.3. Bus matrix Region 2 ............................................................................................................. 64
1.3. Memory map .............................................................................................................. 65
1.3.1. On-chip SRAM memory........................................................................................................ 73
1.3.2. On-chip flash memory overview ........................................................................................... 75
1.4. Boot configuration..................................................................................................... 75
1.5. System configuration controller (SYSCFG)............................................................. 76
1.6. Timer break input lock .............................................................................................. 77
1.7. AXI interconnect matrix (AXIIM) ............................................................................... 77
1.7.1. Characteristics ...................................................................................................................... 77
1.7.2. Function overview ................................................................................................................. 77
1.8. System configuration registers................................................................................ 79
1.8.1. Peripheral mode configuration register (SYSCFG_PMCFG) ............................................... 79
1.8.2. EXTI sources selection register 0 (SYSCFG_EXTISS0)...................................................... 81
1.8.3. EXTI sources selection register 1 (SYSCFG_EXTISS1)...................................................... 82
1.8.4. EXTI sources selection register 2 (SYSCFG_EXTISS2)...................................................... 83
1.8.5. EXTI sources selection register 3 (SYSCFG_EXTISS3)...................................................... 84
1.8.6. Lockup control register (SYSCFG_LKCTL).......................................................................... 86
1.8.7. I/O compensation control register (SYSCFG_CPSCTL) ...................................................... 87
1.8.8. I/O compensation cell code configuration register (SYSCFG_CPSCCCFG) ....................... 88
1.8.9. Timer input selection register 0 (SYSCFG_TIMERCISEL0)................................................. 89
1.8.10. Timer input selection register 1 (SYSCFG_TIMERCISEL1)................................................. 90
1.8.11. Timer input selection register 2 (SYSCFG_TIMERCISEL2)................................................. 91
1.8.12. Timer input selection register 3 (SYSCFG_TIMERCISEL3)................................................. 92
1.8.13. Timer input selection register 4 (SYSCFG_TIMERCISEL4)................................................. 94
1.8.14. Timer input selection register 5 (SYSCFG_TIMERCISEL5)................................................. 95
1.8.15. Timer input selection register 6 (SYSCFG_TIMERCISEL6)................................................. 97
1.8.16. CPU ICACHE error status register(SYSCFG_CPUICAC).................................................... 98
1.8.17. CPU DCACHE error status register (SYSCFG_CPUDCAC) ............................................... 99

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1.8.18. FPU interrupt enable register (SYSCFG_FPUINTEN) ......................................................... 99
1.8.19. SRAM configuration register 0 (SYSCFG_SRAMCFG0) ................................................... 100
1.8.20. SRAM configuration register 1 (SYSCFG_SRAMCFG1) ................................................... 101
1.8.21. TIMERx configuration register 0 (SYSCFG_TIMERxCFG0, x=0, 7) .................................. 101
1.8.22. TIMERx configuration register 1 (SYSCFG_TIMERxCFG1, x=0, 7) .................................. 104
1.8.23. TIMERx configuration register 2 (SYSCFG_TIMERxCFG2, x=0, 7) .................................. 106
1.8.24. TIMERx configuration register 0 (SYSCFG_TIMERxCFG0, x=1, 2, 3, 4, 22, 23, 30, 31) .. 107
1.8.25. TIMERx configuration register 1 (SYSCFG_TIMERxCFG1, x=1, 2, 3, 4, 22, 23, 30, 31) .. 109
1.8.26. TIMERx configuration register 2 (SYSCFG_TIMERxCFG2, x=1, 2, 3, 4, 22, 23, 30, 31) ...112
1.8.27. TIMERx configuration register 0 (SYSCFG_TIMERxCFG0, x=14, 40, 41, 42, 43, 44) .......113
1.8.28. TIMERx configuration register 1 (SYSCFG_TIMERxCFG1, x=14, 40, 41, 42, 43, 44).......115
1.8.29. TIMERx configuration register 2 (SYSCFG_TIMERxCFG2, x=14, 40, 41, 42, 43, 44) .......116
1.8.30. User configuration register (SYSCFG_USERCFG).............................................................117
1.9. AXI interconnect registers.......................................................................................118
1.9.1. AXI peripheral ID4 register (AXI_PERIPH_ID4) ..................................................................118
1.9.2. AXI peripheral ID0 register (AXI_PERIPH_ID0) ..................................................................118
1.9.3. AXI peripheral ID1 register (AXI_PERIPH_ID1) ..................................................................119
1.9.4. AXI peripheral ID2 register (AXI_PERIPH_ID2) ..................................................................119
1.9.5. AXI peripheral ID3 register (AXI_PERIPH_ID3) ................................................................. 120
1.9.6. AXI componet ID0 register (AXI_COMP_ID0).................................................................... 120
1.9.7. AXI componet ID1 register (AXI_COMP_ID1).................................................................... 120
1.9.8. AXI componet ID2 register (AXI_COMP_ID2).................................................................... 121
1.9.9. AXI componet ID3 register (AXI_COMP_ID3).................................................................... 121
1.9.10. AXI Master Port x bus matrix issuing functionality control register (AXI_MPxBM_ISS_CTL)
122
1.9.11. AXI Master Port x bus matrix functionality control register (AXI_MPxBM_CTL) ................ 122
1.9.12. AXI Master Port x long burst functionality control register (AXI_MPx_LB_CTL) ................ 123
1.9.13. AXI Master Port x issuing functionality control register (AXI_MPx_ISS_CTL) ................... 123
1.9.14. AXI Slave Port x functionality control register (AXI_SPx_CTL) .......................................... 124
1.9.15. AXI Slave Port x AHB issuing functionality control register (AXI_SPx_AHBISS_CTL) ...... 124
1.9.16. AXI Slave Port x read QOS control register (AXI_SPx_RDQOS_CTL) ............................. 125
1.9.17. AXI Slave Port x write QOS control register (AXI_SPx_WRQOS_CTL) ............................ 125
1.9.18. AXI Slave Port x issuing functionality control register (AXI_SPx_ISS_CTL)...................... 126
1.10. Device electronic signature................................................................................. 126
1.10.1. Memory density information................................................................................................ 127
1.10.2. Unique device ID (96 bits) .................................................................................................. 127
2. RAM ECC monitor unit (RAMECCMU)................................................................129
2.1. Characteristics......................................................................................................... 129
2.2. Function overview................................................................................................... 129
2.3. Register definition................................................................................................... 131
2.3.1. RAMECCMU global interruput register (RAMECCMU_INT) .............................................. 131

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2.3.2. RAMECCMU monitor x control register (RAMECCMU_MxCTL) ....................................... 131
2.3.3. RAMECCMU monitor x status register (RAMECCMU_MxSTAT)....................................... 132
2.3.4. RAMECCMU monitor x failing address register (RAMECCMU_MxFADDR) ..................... 133
2.3.5. RAMECCMU monitor x failing data low register (RAMECCMU_MxFDL) .......................... 134
2.3.6. RAMECCMU monitor x failing data high register (RAMECCMU_MxFDH) ........................ 134
2.3.7. RAMECCMU monitor x failing ECC error code register (RAMECCMU_MxFECODE) ...... 134
3. Flash memory controller (FMC)..........................................................................136
3.1. Overview .................................................................................................................. 136
3.2. Characteristics......................................................................................................... 136
3.3. Function overview................................................................................................... 136
3.3.1. Flash memory architecture ................................................................................................. 136
3.3.2. Read operations ................................................................................................................. 137
3.3.3. Unlock the FMC_CTL and FMC_OBCTL register .............................................................. 138
3.3.4. Sector erase........................................................................................................................ 139
3.3.5. Mass erase ......................................................................................................................... 140
3.3.6. Main flash Programming..................................................................................................... 144
3.3.7. Option bytes........................................................................................................................ 145
3.3.8. Sector erase/program protection ........................................................................................ 148
3.3.9. Security protection .............................................................................................................. 149
3.3.10. Dedicated code read protection area ................................................................................. 151
3.3.11. Secure user area ................................................................................................................ 153
3.3.12. Secure mode....................................................................................................................... 154
3.3.13. Basic security service ......................................................................................................... 156
3.3.14. Error description.................................................................................................................. 157
3.3.15. FMC interrupts .................................................................................................................... 159
3.4. Register definition................................................................................................... 160
3.4.1.Unlock key register (FMC_KEY)......................................................................................... 160
3.4.2. Option byte unlock key register (FMC_OBKEY)................................................................. 160
3.4.3. Control register (FMC_CTL) ............................................................................................... 160
3.4.4. Status register (FMC_STAT)............................................................................................... 162
3.4.5. Address register (FMC_ADDR) .......................................................................................... 163
3.4.6. Option byte control register (FMC_OBCTL) ....................................................................... 164
3.4.7. Option byte status register 0 (FMC_OBSTAT0_EFT)......................................................... 165
3.4.8. Option byte status register 0 (FMC_OBSTAT0_MDF)........................................................ 166
3.4.9. DCRP address register (FMC_DCRPADDR_EFT) ............................................................ 168
3.4.10. DCRP address register (FMC_DCRPADDR_MDF) ........................................................... 169
3.4.11. Secure address register (FMC_SCRADDR_EFT).............................................................. 170
3.4.12. Secure address register (FMC_SCRADDR_MDF)............................................................. 170
3.4.13. Erase/program protection register (FMC_WP_EFT) .......................................................... 171
3.4.14. Erase/program protection register (FMC_WP_MDF) ......................................................... 172
3.4.15. Boot address register (FMC_BTADDR_EFT) ..................................................................... 173
3.4.16. Boot address register (FMC_BTADDR_MDF) .................................................................... 173

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3.4.17. Option byte status register 1 (FMC_OBSTAT1_EFT)......................................................... 174
3.4.18. Option byte status register 1 (FMC_OBSTAT1_MDF)........................................................ 175
3.4.19. NO-RTDEC area register (FMC_NODEC) ......................................................................... 176
3.4.20. AES IV register (FMC_AESIVx_EFT) (x = 0…2)................................................................ 176
3.4.21. AES IV register (FMC_AESIVx_MDF) (x = 0…2)............................................................... 177
3.4.22. Product ID register x (FMC_PIDx) (x = 0,1)........................................................................ 177
4. Electronic fuse (EFUSE)......................................................................................179
4.1. Overview .................................................................................................................. 179
4.2. Characteristics......................................................................................................... 179
4.3. Function overview................................................................................................... 179
4.3.1. Block diagram ..................................................................................................................... 179
4.3.2. Efuse macro description ..................................................................................................... 180
4.3.3. Read operation ................................................................................................................... 183
4.3.4. Program operation .............................................................................................................. 184
4.3.5. AES key CRC function........................................................................................................ 184
4.3.6. EFUSE interrupts ................................................................................................................ 185
4.4. Register definition................................................................................................... 187
4.4.1. Control register (EFUSE_CTL) ........................................................................................... 187
4.4.2. Address register (EFUSE_ADDR) ...................................................................................... 188
4.4.3. Status register (EFUSE_STAT) .......................................................................................... 189
4.4.4. Status flag clear register (EFUSE_STATC) ........................................................................ 189
4.4.5. User control register (EFUSE_USER_CTL) ....................................................................... 190
4.4.6. MCU reserved register (EFUSE_MCU_RSV) .................................................................... 192
4.4.7. Debug password register x (EFUSE_DPx) (x = 0,1) .......................................................... 194
4.4.8. Firmware AES key register x (EFUSE_AES_KEYx) (x = 0…3) ......................................... 195
4.4.9. User data register x (EFUSE_USER_DATAx) (x = 0…3) ................................................... 195
5. Power management unit (PMU) ..........................................................................196
5.1. Overview .................................................................................................................. 196
5.2. Characteristics......................................................................................................... 196
5.3. Function overview................................................................................................... 197
5.3.1. Backup domain ................................................................................................................... 197
5.3.2. VDD / VDDA power domain .................................................................................................... 199
5.3.3. 0.9V power domain............................................................................................................. 203
5.3.4. Power saving modes .......................................................................................................... 208
5.4. Register definition................................................................................................... 210
5.4.1. Control register 0 (PMU_CTL0) .......................................................................................... 210
5.4.2. Control and status register (PMU_CS) ................................................................................211
5.4.3. Control register 1 (PMU_CTL1) .......................................................................................... 213
5.4.4. Control register 2 (PMU_CTL2) .......................................................................................... 215
5.4.5. Control register 3 (PMU_CTL3) .......................................................................................... 216

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5.4.6. Parameter register (PMU_PAR) ......................................................................................... 217
6. Reset and clock unit (RCU).................................................................................219
6.1. Reset control unit (RCTL) ....................................................................................... 219
6.1.1. Overview ............................................................................................................................. 219
6.1.2. Function overview ............................................................................................................... 219
6.2. Clock control unit (CCTL) ....................................................................................... 220
6.2.1. Overview ............................................................................................................................. 220
6.2.2. Characteristics .................................................................................................................... 224
6.2.3. Function overview ............................................................................................................... 224
6.3. Register definition................................................................................................... 230
6.3.1. Control register (RCU_CTL) ............................................................................................... 230
6.3.2. PLL0 register (RCU_PLL0)................................................................................................. 232
6.3.3. Clock configuration register 0 (RCU_CFG0) ...................................................................... 234
6.3.4. Clock interrupt register (RCU_INT) .................................................................................... 236
6.3.5. AHB1 reset register (RCU_AHB1RST) .............................................................................. 239
6.3.6. AHB2 reset register (RCU_AHB2RST) .............................................................................. 241
6.3.7. AHB3 reset register (RCU_AHB3RST) .............................................................................. 242
6.3.8. AHB4 reset register (RCU_AHB4RST) .............................................................................. 243
6.3.9. APB1 reset register (RCU_APB1RST) ............................................................................... 245
6.3.10. APB2 reset register (RCU_APB2RST) ............................................................................... 248
6.3.11. APB3 reset register (RCU_APB3RST) ............................................................................... 251
6.3.12. APB4 reset register (RCU_APB4RST) ............................................................................... 252
6.3.13. AHB1 enable register (RCU_AHB1EN) .............................................................................. 253
6.3.14. AHB2 enable register (RCU_AHB2EN) .............................................................................. 255
6.3.15. AHB3 enable register (RCU_AHB3EN) .............................................................................. 256
6.3.16. AHB4 enable register (RCU_AHB4EN) .............................................................................. 258
6.3.17. APB1 enable register (RCU_APB1EN) .............................................................................. 259
6.3.18. APB2 enable register (RCU_APB2EN) .............................................................................. 263
6.3.19. APB3 enable register (RCU_APB3EN) .............................................................................. 266
6.3.20. APB4 enable register (RCU_APB4EN) .............................................................................. 266
6.3.21. AHB1 sleep mode enable register (RCU_AHB1SPEN) ..................................................... 267
6.3.22. AHB2 sleep mode enable register (RCU_AHB2SPEN) ..................................................... 270
6.3.23. AHB3 sleep mode enable register (RCU_AHB3SPEN) ..................................................... 271
6.3.24. AHB4 sleep mode enable register (RCU_AHB4SPEN) ..................................................... 273
6.3.25. APB1 sleep mode enable register (RCU_APB1SPEN)...................................................... 274
6.3.26. APB2 sleep mode enable register (RCU_APB2SPEN)...................................................... 278
6.3.27. APB3 sleep mode enable register (RCU_APB3SPEN)...................................................... 281
6.3.28. APB4 sleep mode enable register (RCU_APB4SPEN)...................................................... 281
6.3.29. Backup domain control register (RCU_BDCTL) ................................................................. 282
6.3.30. Reset source/clock register (RCU_RSTSCK) .................................................................... 284
6.3.31. PLL clock additional control register (RCU_PLLADDCTL) ................................................. 286
6.3.32. PLL1 register (RCU_PLL1)................................................................................................. 288

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6.3.33. PLL2 register (RCU_PLL2)................................................................................................. 290
6.3.34. Clock configuration register 1 (RCU_CFG1) ...................................................................... 292
6.3.35. Clock configuration register 2 (RCU_CFG2) ...................................................................... 294
6.3.36. Clock configuration register 3 (RCU_CFG3) ...................................................................... 296
6.3.37. PLL all configuration register (RCU_PLLALL) .................................................................... 298
6.3.38. PLL0 fraction configuration register (RCU_PLL0FRA) ....................................................... 300
6.3.39. PLL1 fraction configuration register (RCU_PLL1FRA) ....................................................... 300
6.3.40. PLL2 fraction configuration register (RCU_PLL2FRA) ....................................................... 301
6.3.41. Additional clock control register 0 (RCU_ADDCTL0) ......................................................... 302
6.3.42. Additional clock control register 1(RCU_ADDCTL1) .......................................................... 303
6.3.43. Additional clock interrupt register (RCU_ADDINT)............................................................. 304
6.3.44. Clock configuration register 4 (RCU_CFG4) ...................................................................... 306
6.3.45. USB clock control register (RCU_USBCLKCTL)................................................................ 307
6.3.46. PLLUSB configuration register (RCU_PLLUSBCFG)......................................................... 309
6.3.47. APB2 additional reset register (RCU_ADDAPB2RST)....................................................... 310
6.3.48. APB2 additional enable register (RCU_ADDAPB2EN) .......................................................311
6.3.49. APB2 additional sleep enable register (RCU_ADDAPB2SPEN)........................................ 312
6.3.50. Clock configuration register 5 (RCU_CFG5) ...................................................................... 312
7. Clock trim controller (CTC) .................................................................................315
7.1. Overview .................................................................................................................. 315
7.2. Characteristics......................................................................................................... 315
7.3. Function overview ................................................................................................... 315
7.3.1. REF sync pulse generator .................................................................................................. 316
7.3.2. CTC trim counter................................................................................................................. 316
7.3.3. Frequency evaluation and automatically trim process........................................................ 317
7.3.4. Software program guide ..................................................................................................... 318
7.4. Register definition ................................................................................................... 320
7.4.1. Control register 0 (CTC_CTL0)........................................................................................... 320
7.4.2. Control register 1 (CTC_CTL1)........................................................................................... 321
7.4.3. Status register (CTC_STAT) ............................................................................................... 322
7.4.4. Interrupt clear register (CTC_INTC) ................................................................................... 324
8. Interrupt / event controller (EXTI).......................................................................326
8.1. Overview .................................................................................................................. 326
8.2. Characteristics......................................................................................................... 326
8.3. Interrupts function overview................................................................................... 326
8.4. External interrupt and event (EXTI) block diagram ............................................... 333
8.5. External interrupt and event function overview .................................................... 333
8.6. Register definition................................................................................................... 336
8.6.1. Interrupt enable register 0 (EXTI_INTEN0) ........................................................................ 336

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8.6.2. Event enable register 0 (EXTI_EVEN0) ............................................................................. 336
8.6.3. Rising edge trigger enable register 0 (EXTI_RTEN0) ........................................................ 336
8.6.4. Falling edge trigger enable register 0 (EXTI_FTEN0) ........................................................ 337
8.6.5. Software interrupt event register 0 (EXTI_SWIEV0) .......................................................... 337
8.6.6. Pending register 0 (EXTI_PD0) .......................................................................................... 338
8.6.7. Interrupt enable register 1 (EXTI_INTEN1) ........................................................................ 338
8.6.8. Event enable register 1 (EXTI_EVEN1) ............................................................................. 339
8.6.9. Rising edge trigger enable register 1 (EXTI_RTEN1) ........................................................ 339
8.6.10. Falling edge trigger enable register 1 (EXTI_FTEN1) ........................................................ 339
8.6.11. Software interrupt event register 1 (EXTI_SWIEV1) .......................................................... 340
8.6.12. Pending register 1 (EXTI_PD1) .......................................................................................... 340
9. Trigger selection controller (TRIGSEL)..............................................................342
9.1. Overview .................................................................................................................. 342
9.2. Characteristics......................................................................................................... 342
9.3. Function overview ................................................................................................... 342
9.4. Internal connect....................................................................................................... 343
9.5. Register definition ................................................................................................... 354
9.5.1. Trigger selection for EXTOUT0 register (TRIGSEL_EXTOUT0) ........................................ 354
9.5.2. Trigger selection for EXTOUT1 register (TRIGSEL_EXTOUT1)........................................ 354
9.5.3. Trigger selection for EXTOUT2 register (TRIGSEL_EXTOUT2) ........................................ 355
9.5.4. Trigger selection for EXTOUT3 register (TRIGSEL_EXTOUT3)........................................ 356
9.5.5. Trigger selection for ADC0 register (TRIGSEL_ADC0) ...................................................... 356
9.5.6. Trigger selection for ADC1 register (TRIGSEL_ADC1) ...................................................... 357
9.5.7. Trigger selection for ADC2 register (TRIGSEL_ADC2) ...................................................... 358
9.5.8. Trigger selection for DAC_OUT0 register (TRIGSEL_DACOUT0)..................................... 358
9.5.9. Trigger selection for DAC_OUT1 register (TRIGSEL_DACOUT1)..................................... 359
9.5.10. Trigger selection for TIMER0_BRKIN register (TRIGSEL_TIMER0BRKIN) ...................... 360
9.5.11. Trigger selection for TIMER7_BRKIN register (TRIGSEL_TIMER7BRKIN) ...................... 360
9.5.12. Trigger selection for TIMER14_BRKIN register (TRIGSEL_TIMER14BRKIN) .................. 361
9.5.13. Trigger selection for TIMER15_BRKIN register (TRIGSEL_TIMER15BRKIN) .................. 362
9.5.14. Trigger selection for TIMER16_BRKIN register (TRIGSEL_TIMER16BRKIN) .................. 363
9.5.15. Trigger selection for TIMER40_BRKIN register (TRIGSEL_TIMER40BRKIN) .................. 363
9.5.16. Trigger selection for TIMER41_BRKIN register (TRIGSEL_TIMER41BRKIN) .................. 364
9.5.17. Trigger selection for TIMER42_BRKIN register (TRIGSEL_TIMER42BRKIN) .................. 365
9.5.18. Trigger selection for TIMER43_BRKIN register (TRIGSEL_TIMER43BRKIN) .................. 365
9.5.19. Trigger selection for TIMER44_BRKIN register (TRIGSEL_TIMER44BRKIN) .................. 366
9.5.20. Trigger selection for CAN0 register (TRIGSEL_CAN0) ...................................................... 366
9.5.21. Trigger selection for CAN1 register (TRIGSEL_CAN1) ...................................................... 367
9.5.22. Trigger selection for CAN2 register (TRIGSEL_CAN2) ...................................................... 368
9.5.23. Trigger selection for LPDTS register (TRIGSEL_LPDTS).................................................. 368
9.5.24. Trigger selection for TIMER0_ETI register (TRIGSEL_TIMER0ETI) ................................. 369

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9.5.25. Trigger selection for TIMER1_ETI register (TRIGSEL_TIMER1ETI) ................................. 369
9.5.26. Trigger selection for TIMER2_ETI register (TRIGSEL_TIMER2ETI) ................................. 370
9.5.27. Trigger selection for TIMER3_ETI register (TRIGSEL_TIMER3ETI) ................................. 371
9.5.28. Trigger selection for TIMER4_ETI register (TRIGSEL_TIMER4ETI) ................................. 371
9.5.29. Trigger selection for TIMER7_ETI register (TRIGSEL_TIMER7ETI) ................................. 372
9.5.30. Trigger selection for TIMER22_ETI register (TRIGSEL_TIMER22ETI) ............................. 372
9.5.31. Trigger selection for TIMER23_ETI register (TRIGSEL_TIMER23ETI) ............................. 373
9.5.32. Trigger selection for TIMER30_ETI register (TRIGSEL_TIMER30ETI) ............................. 374
9.5.33. Trigger selection for TIMER31_ETI register (TRIGSEL_TIMER31ETI) ............................. 374
9.5.34. Trigger selection for EDOUT register (TRIGSEL_EDOUT)................................................ 375
9.5.35. Trigger selection for HPDF_ITRG register (TRIGSEL_HPDF) ........................................... 375
9.5.36. Trigger selection for TIMER0_ITI14 register (TRIGSEL_TIMER0ITI14) ............................ 376
9.5.37. Trigger selection for TIMER1_ITI14 register (TRIGSEL_TIMER1ITI14) ............................ 377
9.5.38. Trigger selection for TIMER2_ITI14 register (TRIGSEL_TIMER2ITI14) ............................ 377
9.5.39. Trigger selection for TIMER3_ITI14 register (TRIGSEL_TIMER3ITI14) ............................ 378
9.5.40. Trigger selection for TIMER4_ITI14 register (TRIGSEL_TIMER4ITI14) ............................ 378
9.5.41. Trigger selection for TIMER7_ITI14 register (TRIGSEL_TIMER7ITI14) ............................ 379
9.5.42. Trigger selection for TIMER14_ITI14 register (TRIGSEL_TIMER14ITI14) ........................ 380
9.5.43. Trigger selection for TIMER22_ITI14 register (TRIGSEL_TIMER22ITI14) ........................ 380
9.5.44. Trigger selection for TIMER23_ITI14 register (TRIGSEL_TIMER23ITI14) ........................ 381
9.5.45. Trigger selection for TIMER30_ITI14 register (TRIGSEL_TIMER30ITI14) ........................ 381
9.5.46. Trigger selection for TIMER31_ITI14 register (TRIGSEL_TIMER31ITI14) ........................ 382
9.5.47. Trigger selection for TIMER40_ITI14 register (TRIGSEL_TIMER40ITI14) ........................ 383
9.5.48. Trigger selection for TIMER41_ITI14 register (TRIGSEL_TIMER41ITI14) ........................ 383
9.5.49. Trigger selection for TIMER42_ITI14 register (TRIGSEL_TIMER42ITI14) ........................ 384
9.5.50. Trigger selection for TIMER43_ITI14 register (TRIGSEL_TIMER43ITI14) ........................ 384
9.5.51. Trigger selection for TIMER44_ITI14 register (TRIGSEL_TIMER44ITI14) ........................ 385
10. General-purpose and alternate-function I/Os (GPIO and AFIO)....................387
10.1. Overview............................................................................................................... 387
10.2. Characteristics..................................................................................................... 387
10.3. Function overview................................................................................................ 387
10.3.1. GPIO pin configuration ....................................................................................................... 389
10.3.2. External interrupt/event lines .............................................................................................. 390
10.3.3. Alternate functions (AF) ...................................................................................................... 390
10.3.4. Additional functions............................................................................................................. 390
10.3.5. Input configuration .............................................................................................................. 390
10.3.6. Output configuration ........................................................................................................... 390
10.3.7. Analog configuration ........................................................................................................... 391
10.3.8. Alternate function (AF) configuration .................................................................................. 392
10.3.9. GPIO locking function ......................................................................................................... 392
10.3.10. GPIO single cycle toggle function....................................................................................... 393
10.3.11. I/O compensation unit ......................................................................................................... 393

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10.3.12. Analog configuration for ADC ............................................................................................. 393
10.3.13. Input filtering ....................................................................................................................... 394
10.4. Register definition................................................................................................ 397
10.4.1. Port control register (GPIOx_CTL, x=A...H, J, K) ............................................................... 397
10.4.2. Port output mode register (GPIOx_OMODE, x=A…H, J, K) .............................................. 399
10.4.3. Port output speed register (GPIOx_OSPD, x=A...H, J, K).................................................. 400
10.4.4. Port pull-up/down register (GPIOx_PUD, x=A…H, J, K) .................................................... 402
10.4.5. Port input status register (GPIOx_ISTAT, x=A…H, J, K) .................................................... 404
10.4.6. Port output control register (GPIOx_OCTL, x=A…H, J, K)................................................. 404
10.4.7. Port bit operate register (GPIOx_BOP, x=A...H, J, K) ........................................................ 405
10.4.8. Port configuration lock register (GPIOx_LOCK, x=A...H, J, K)........................................... 405
10.4.9. Alternate function selected register 0 (GPIOx_AFSEL0, x=A...H, J, K) ............................. 406
10.4.10. Alternate function selected register 1 (GPIOx_AFSEL1, x=A…H, J, K)............................. 407
10.4.11. Bit clear register (GPIOx_BC, x=A…H, J, K)...................................................................... 408
10.4.12. Port bit toggle register (GPIOx_TG, x=A…H, J, K) ............................................................ 409
10.4.13. Input filtering register (GPIOx_IFL, x=A...H, J, K) .............................................................. 409
10.4.14. Input filtering type register (GPIOx_IFTP, x=A...H, J, K) .................................................... 410
11. Cyclic redundancy checks management unit (CRC) .....................................412
11.1. Overview ............................................................................................................... 412
11.2. Characteristics ..................................................................................................... 412
11.3. Function overview................................................................................................ 413
11.4. Register definition................................................................................................ 414
11.4.1. Data register (CRC_DATA) ................................................................................................. 414
11.4.2. Free data register (CRC_FDATA)....................................................................................... 414
11.4.3. Control register (CRC_CTL) ............................................................................................... 415
11.4.4. Initialization data register (CRC_IDATA)............................................................................. 415
11.4.5. Polynomial register (CRC_POLY)....................................................................................... 416
12. True random number generator (TRNG).........................................................417
12.1. Overview ............................................................................................................... 417
12.2. Characteristics ..................................................................................................... 417
12.3. Function overview................................................................................................ 418
12.3.1. LFSR................................................................................................................................... 418
12.3.2. Post processing .................................................................................................................. 419
12.3.3. Conditioning ........................................................................................................................ 419
12.3.4. Output FIFO ........................................................................................................................ 419
12.3.5. Health tests ......................................................................................................................... 420
12.3.6. NIST mode state ................................................................................................................. 421
12.3.7. Operation flow..................................................................................................................... 421
12.3.8. Error flags ........................................................................................................................... 422
12.3.9. Low power usage................................................................................................................ 422

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12.4. Register definition................................................................................................ 423
12.4.1. Control register (TRNG_CTL)............................................................................................. 423
12.4.2. Status register (TRNG_STAT) ............................................................................................ 425
12.4.3. Data register (TRNG_DATA)............................................................................................... 426
12.4.4. Health tests configure register (TRNG_HTCFG)................................................................ 426
13. Cryptographic Acceleration Unit (CAU)..........................................................428
13.1. Overview............................................................................................................... 428
13.2. Characteristics..................................................................................................... 428
13.3. CAU data type and initialization vectors ............................................................ 429
13.3.1. Data type............................................................................................................................. 429
13.3.2. Initialization vectors ............................................................................................................ 430
13.4. Cryptographic acceleration processor............................................................... 430
13.4.1. DES / TDES cryptographic acceleration processor ............................................................ 431
13.4.2. AES cryptographic acceleration processor......................................................................... 435
13.5. Operating modes.................................................................................................. 443
13.6. CAU DMA interface .............................................................................................. 445
13.7. CAU interrupts...................................................................................................... 445
13.8. CAU suspended mode......................................................................................... 446
13.9. Register definition................................................................................................ 447
13.9.1. Control register (CAU_CTL) ............................................................................................... 447
13.9.2. Status register 0 (CAU_STAT0) .......................................................................................... 449
13.9.3. Data input register (CAU_DI).............................................................................................. 449
13.9.4. Data output register (CAU_DO).......................................................................................... 450
13.9.5. DMA enable register (CAU_DMAEN) ................................................................................. 451
13.9.6. Interrupt enable register (CAU_INTEN).............................................................................. 451
13.9.7. Status register 1 (CAU_STAT1) .......................................................................................... 452
13.9.8. Interrupt flag register (CAU_INTF)...................................................................................... 452
13.9.9. Key registers (CAU_KEY0..3(H / L)) .................................................................................. 453
13.9.10. Initial vector registers (CAU_IV0..1(H / L)) ......................................................................... 455
13.9.11. GCM or CCM mode context switch register x (CAU_GCMCCMCTXSx) (x=0..7).............. 457
13.9.12. GCM mode context switch register x (CAU_GCMCTXSx) (x=0..7) ................................... 457
14. Hash Acceleration Unit (HAU) .........................................................................459
14.1. Overview............................................................................................................... 459
14.2. Characteristics..................................................................................................... 459
14.3. HAU data type....................................................................................................... 459
14.4. HAU core............................................................................................................... 461
14.4.1. Automatic data padding ...................................................................................................... 461
14.4.2. Digest computing ................................................................................................................ 462

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14.4.3. Hash mode.......................................................................................................................... 463
14.4.4. HMAC mode ....................................................................................................................... 463
14.5. HAU suspended mode......................................................................................... 463
14.5.1. Transfer data by CPU ......................................................................................................... 464
14.5.2. Transfer data by DMA......................................................................................................... 464
14.6. HAU interrupt........................................................................................................ 465
14.6.1. Input FIFO interrupt ............................................................................................................ 465
14.6.2. Calculation completion interrupt ......................................................................................... 465
14.7. Register definition................................................................................................ 466
14.7.1. Control register (HAU_CTL) ............................................................................................... 466
14.7.2. Data input register (HAU_DI).............................................................................................. 467
14.7.3. Configuration register (HAU_CFG)..................................................................................... 468
14.7.4. Data output register (HAU_DO0..7).................................................................................... 469
14.7.5. Interrupt enable register (HAU_INTEN).............................................................................. 471
14.7.6. Status and flag register (HAU_STAT) ................................................................................. 472
14.7.7. Context switch register x (HAU_CTXSx) (x = 0...53).......................................................... 472
15. Trigonometric Math Unit (TMU) .......................................................................474
15.1. Overview ............................................................................................................... 474
15.2. Characteristics ..................................................................................................... 474
15.3. Block diagram ...................................................................................................... 474
15.4. Function overview................................................................................................ 475
15.4.1. Data format and configuration ............................................................................................ 475
15.4.2. Mode configuration ............................................................................................................. 476
15.4.3. TMU operation pending ...................................................................................................... 485
15.4.4. Zero-overhead mode .......................................................................................................... 486
15.4.5. Interrupt and DMA requests................................................................................................ 486
15.5. Registers definition.............................................................................................. 486
15.5.1. Control and status register (TMU_CS) ............................................................................... 486
15.5.2. Input data register (TMU_IDATA) ....................................................................................... 489
15.5.3. Output data register (TMU_ODATA)................................................................................... 490
16. Direct memory access controller (DMA).........................................................491
16.1. Overview............................................................................................................... 491
16.2. Characteristics..................................................................................................... 491
16.3. Function overview................................................................................................ 492
16.3.1. Block diagram ..................................................................................................................... 492
16.3.2. Peripheral handshake......................................................................................................... 494
16.3.3. Data process....................................................................................................................... 494
16.3.4. Address generation............................................................................................................. 499
16.3.5. Circular mode...................................................................................................................... 500

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16.3.6. Switch-buffer mode............................................................................................................. 500
16.3.7. Transfer operation............................................................................................................... 501
16.3.8. Transfer finish ..................................................................................................................... 502
16.3.9. Channel configuration......................................................................................................... 503
16.4. Interrupts.............................................................................................................. 504
16.4.1. Flag ..................................................................................................................................... 505
16.4.2. Exception ............................................................................................................................ 505
16.4.3. Error .................................................................................................................................... 506
16.4.4. DMA request mapping ........................................................................................................ 508
16.5. Register definition................................................................................................ 509
16.5.1. Interrupt flag register 0 (DMA_INTF0) ................................................................................ 509
16.5.2. Interrupt flag register 1 (DMA_INTF1) ................................................................................ 510
16.5.3. Interrupt flag clear register 0 (DMA_INTC0)........................................................................511
16.5.4. Interrupt flag clear register 1 (DMA_INTC1)....................................................................... 512
16.5.5. Channel x control register (DMA_CHxCTL) ....................................................................... 512
16.5.6. Channel x counter register (DMA_CHxCNT)...................................................................... 516
16.5.7. Channel x peripheral base address register (DMA_CHxPADDR) ...................................... 516
16.5.8. Channel x memory 0 base address register (DMA_CHxM0ADDR) ................................... 517
16.5.9. Channel x memory 1 base address register (DMA_CHxM1ADDR) ................................... 517
16.5.10. Channel x FIFO control register (DMA_CHxFCTL) ............................................................ 518
17. Master direct memory access controller (MDMA)..........................................520
17.1. Overview............................................................................................................... 520
17.2. Characteristics..................................................................................................... 520
17.3. Function overview................................................................................................ 521
17.3.1. Data process....................................................................................................................... 523
17.3.2. Address generation............................................................................................................. 526
17.3.3. Transfer modes................................................................................................................... 527
17.3.4. Transfer status .................................................................................................................... 530
17.3.5. MDMA interrupts and errors................................................................................................ 530
17.4. Register definition................................................................................................ 533
17.4.1. Global interrupt flag register (MDMA_GINTF) .................................................................... 533
17.4.2. Channel x status register 0 (MDMA_CHxSTAT0)............................................................... 533
17.4.3. Channel x status clear register (MDMA_CHxSTATC) ........................................................ 534
17.4.4. Channel x status register 1 (MDMA_CHxSTAT1)............................................................... 535
17.4.5. Channel x control register 0 (MDMA_CHxCTL0) ............................................................... 536
17.4.6. Channel x configure register (MDMA_CHxCFG)................................................................ 538
17.4.7. Channel x block transfer configure register (MDMA_CHxBTCFG) .................................... 542
17.4.8. Channel x source address register (MDMA_CHxSADDR)................................................. 542
17.4.9. Channel x destination address register (MDMA_CHxDADDR) .......................................... 543
17.4.10. Channel x multi-block address update register (MDMA_CHxMBADDRU)......................... 543
17.4.11. Channel x link address register (MDMA_CHxLADDR)....................................................... 544

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17.4.12. Channel x control register 1 (MDMA_CHxCTL1) ............................................................... 544
17.4.13. Channel x mask address register (MDMA_CHxMADDR) .................................................. 545
17.4.14. Channel x mask data register (MDMA_CHxMDATA) ......................................................... 546
18. DMA request multiplexer (DMAMUX) ..............................................................547
18.1. Overview............................................................................................................... 547
18.2. Characteristics..................................................................................................... 547
18.3. Block diagram ...................................................................................................... 548
18.4. Signal description................................................................................................ 548
18.5. Function overview................................................................................................ 549
18.5.1. DMAMUX request multiplexer ............................................................................................ 549
18.5.2. DMAMUX request generator .............................................................................................. 552
18.5.3. Channel configurations ....................................................................................................... 552
18.5.4. Interrupt............................................................................................................................... 553
18.5.5. DMAMUX mapping ............................................................................................................. 553
18.6. Register definition................................................................................................ 562
18.6.1. Request multiplexer channel x configuration register (DMAMUX_RM_CHxCFG) ............. 562
18.6.2. Request multiplexer channel interrupt flag register (DMAMUX_RM_INTF)....................... 563
18.6.3. Request multiplexer channel interrupt flag clear register (DMAMUX_RM_INTC).............. 563
18.6.4. Request generator channel x configuration register (DMAMUX_RG_CHxCFG) ............... 564
18.6.5. Request generator channel interrupt flag register (DMAMUX_RG_INTF) ......................... 565
18.6.6. Rquest generator channel interrupt flag clear register (DMAMUX_RG_INTC) .................. 565
19. Debug (DBG) .....................................................................................................567
19.1. Overview............................................................................................................... 567
19.2. JTAG / SW function overview.............................................................................. 567
19.2.1. Switch JTAG or SW interface ............................................................................................. 567
19.2.2. Pin assignment ................................................................................................................... 567
19.2.3. JTAG ................................................................................................................................... 568
19.2.4. Debug reset ........................................................................................................................ 570
19.2.5. JEDEC-106 ID code ........................................................................................................... 570
19.3. Debug hold function overview ............................................................................ 570
19.3.1. Debug support for power saving mode............................................................................... 570
19.3.2. Debug support for TIMER, I2C, WWDGT, FWDGT, RTC and CAN ................................... 570
19.4. Register definition................................................................................................ 571
19.4.1. ID code register (DBG_ID).................................................................................................. 571
19.4.2. Control register0 (DBG_CTL0) ........................................................................................... 571
19.4.3. Control register1 (DBG_CTL1) ........................................................................................... 572
19.4.4. Control register2 (DBG_CTL2) ........................................................................................... 573
19.4.5. Control register3 (DBG_CTL3) ........................................................................................... 575
19.4.6. Control register4 (DBG_CTL4) ........................................................................................... 576

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20. Analog-to-digital converter (ADC)...................................................................578
20.1. Overview............................................................................................................... 578
20.2. Characteristics..................................................................................................... 578
20.3. Pins and internal signals..................................................................................... 579
20.4. Function overview................................................................................................ 580
20.4.1. Foreground calibration function .......................................................................................... 580
20.4.2. Dual clock domain architecture........................................................................................... 581
20.4.3. ADC enable......................................................................................................................... 581
20.4.4. Single-enden and differential input channels...................................................................... 581
20.4.5. Routine sequence............................................................................................................... 582
20.4.6. Operation modes ................................................................................................................ 583
20.4.7. Conversion result threshold monitor function ..................................................................... 586
20.4.8. Data storage mode ............................................................................................................. 586
20.4.9. Sample time configuration .................................................................................................. 587
20.4.10. External trigger configuration.............................................................................................. 587
20.4.11. DMA request ....................................................................................................................... 588
20.4.12. Overflow detection .............................................................................................................. 588
20.4.13. ADC internal channels ........................................................................................................ 588
20.4.14. Battery voltage monitoring .................................................................................................. 590
20.4.15. Using HPDF to managing the conversion results............................................................... 590
20.4.16. Programmable resolution (DRES) ...................................................................................... 590
20.4.17. On-chip hardware oversampling......................................................................................... 591
20.5. ADC sync mode.................................................................................................... 593
20.5.1. Free mode........................................................................................................................... 594
20.5.2. Routine parallel mode......................................................................................................... 594
20.5.3. Routine follow-up mode ...................................................................................................... 595
20.5.4. Use DMA in ADC sync mode .............................................................................................. 596
20.6. ADC interrupts...................................................................................................... 597
20.7. Register definition................................................................................................ 598
20.7.1. Status register (ADC_STAT) ............................................................................................... 598
20.7.2. Control register 0 (ADC_CTL0) .......................................................................................... 599
20.7.3. Control register 1 (ADC_CTL1) .......................................................................................... 601
20.7.4. Watchdog high threshold register0 (ADC_WDHT0) ........................................................... 604
20.7.5. Watchdog low threshold register0 (ADC_WDLT0) ............................................................. 604
20.7.6. Routine sequence register 0 (ADC_RSQ0)........................................................................ 604
20.7.7. Routine sequence register 1 (ADC_RSQ1)........................................................................ 605
20.7.8. Routine sequence register 2 (ADC_RSQ2)........................................................................ 606
20.7.9. Routine sequence register 3 (ADC_RSQ3)........................................................................ 607
20.7.10. Routine sequence register 4 (ADC_RSQ4)........................................................................ 608
20.7.11. Routine sequence register 5 (ADC_RSQ5) ........................................................................ 609
20.7.12. Routine sequence register 6 (ADC_RSQ6)........................................................................ 610

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20.7.13. Routine sequence register 7 (ADC_RSQ7).........................................................................611
20.7.14. Routine sequence register 8 (ADC_RSQ8)........................................................................ 612
20.7.15. Routine data register (ADC_RDATA).................................................................................. 613
20.7.16. Oversample control register (ADC_OVSAMPCTL) ............................................................ 613
20.7.17. Watchdog 1 Channel Selection Register (ADC_WD1SR).................................................. 615
20.7.18. Watchdog 2 Channel Selection Register (ADC_WD2SR).................................................. 615
20.7.19. Watchdog high threshold register1 (ADC_WDHT1) ........................................................... 616
20.7.20. Watchdog low threshold register1 (ADC_WDLT1) ............................................................. 616
20.7.21. Watchdog high threshold register2 (ADC_WDHT2) ........................................................... 617
20.7.22. Watchdog low threshold register2 (ADC_WDLT2) ............................................................. 617
20.7.23. Differential mode control register (ADC_DIFCTL) .............................................................. 618
20.7.24. Summary status register (ADC_SSTAT)............................................................................. 618
20.7.25. Sync control register (ADC_SYNCCTL) ............................................................................. 620
20.7.26. Sync routine data register0 (ADC_SYNCDATA0) .............................................................. 621
20.7.27. Sync routine data register1 (ADC_SYNCDATA1) .............................................................. 622
21. Digital-to-analog converter (DAC) ...................................................................623
21.1. Overview ............................................................................................................... 623
21.2. Characteristics ..................................................................................................... 623
21.3. Function description............................................................................................ 624
21.3.1. DAC enable......................................................................................................................... 624
21.3.2. DAC output buffer ............................................................................................................... 624
21.3.3. DAC data configuration....................................................................................................... 624
21.3.4. DAC trigger ......................................................................................................................... 625
21.3.5. DAC conversion .................................................................................................................. 625
21.3.6. DAC noise wave ................................................................................................................. 625
21.3.7. DAC modes......................................................................................................................... 626
21.3.8. DAC output voltage............................................................................................................. 627
21.3.9. DAC output buffer calibration.............................................................................................. 627
21.3.10. DMA request ....................................................................................................................... 628
21.3.11. DAC concurrent conversion................................................................................................ 628
21.3.12. DAC low-power modes ....................................................................................................... 629
21.4. DAC registers ....................................................................................................... 630
21.4.1. Control register 0 (DAC_CTL0) .......................................................................................... 630
21.4.2. Software trigger register (DAC_SWT) ................................................................................ 632
21.4.3. DAC_OUT0 12-bit right-aligned data holding register (OUT0_R12DH) ............................. 633
21.4.4. DAC_OUT0 12-bit left-aligned data holding register (OUT0_L12DH)................................ 633
21.4.5. DAC_OUT0 8-bit right-aligned data holding register (OUT0_R8DH) ................................. 634
21.4.6. DAC_OUT1 12-bit right-aligned data holding register (OUT1_R12DH) ............................. 634
21.4.7. DAC_OUT1 12-bit left-aligned data holding register (OUT1_L12DH)................................ 635
21.4.8. DAC_OUT1 8-bit right-aligned data holding register (OUT1_R8DH) ................................. 635
21.4.9. DAC concurrent mode 12-bit right-aligned data holding register (DACC_R12DH) ............ 636
21.4.10. DAC concurrent mode 12-bit left-aligned data holding register (DACC_L12DH)............... 636

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21.4.11. DAC concurrent mode 8-bit right-aligned data holding register (DACC_R8DH) ................ 637
21.4.12. DAC_OUT0 data output register (OUT0_DO) .................................................................... 637
21.4.13. DAC_OUT1 data output register (OUT1_DO) .................................................................... 638
21.4.14. DAC Status register 0 (DAC_STAT0) ................................................................................. 638
21.4.15. DAC calibration Register (DAC_CALR).............................................................................. 639
21.4.16. DAC mode control Register (DAC_MDCR) ........................................................................ 639
21.4.17. DAC sample and keep sample time Register 0 (DAC_SKSTR0)....................................... 641
21.4.18. DAC sample and keep sample time Register 1 (DAC_SKSTR1)....................................... 641
21.4.19. DAC sample and keep keep time Register (DAC_SKKTR) ............................................... 641
21.4.20. DAC sample and keep refresh time Register (DAC_SKRTR) ............................................ 642
22. Watchdog timer (WDGT) ..................................................................................643
22.1. Free watchdog timer (FWDGT)............................................................................ 643
22.1.1. Overview ............................................................................................................................. 643
22.1.2. Characteristics .................................................................................................................... 643
22.1.3. Function overview ............................................................................................................... 644
22.1.4. Register definition ............................................................................................................... 646
22.2. Window watchdog timer (WWDGT)..................................................................... 650
22.2.1. Overview ............................................................................................................................. 650
22.2.2. Characteristics .................................................................................................................... 650
22.2.3. Function overview............................................................................................................... 650
22.2.4. Register definition ............................................................................................................... 653
23. Real time clock (RTC).......................................................................................655
23.1. Overview............................................................................................................... 655
23.2. Characteristics..................................................................................................... 655
23.3. Function overview................................................................................................ 656
23.3.1. Block diagram ..................................................................................................................... 656
23.3.2. Clock source and prescalers .............................................................................................. 656
23.3.3. Shadow registers introduction ............................................................................................ 657
23.3.4. Configurable and field maskable alarm .............................................................................. 657
23.3.5. Configurable periodic auto-wakeup counter ....................................................................... 658
23.3.6. RTC initialization and configuration .................................................................................... 658
23.3.7. Calendar reading ................................................................................................................ 659
23.3.8. Resetting the RTC .............................................................................................................. 661
23.3.9. RTC shift function ............................................................................................................... 661
23.3.10. RTC reference clock detection ........................................................................................... 662
23.3.11. RTC smooth digital calibration............................................................................................ 662
23.3.12. Time-stamp function ........................................................................................................... 664
23.3.13. Tamper detection ................................................................................................................ 664
23.3.14. Calibration clock output ...................................................................................................... 666
23.3.15. Alarm output........................................................................................................................ 666
23.3.16. RTC pin configuration ......................................................................................................... 666

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23.3.17. RTC power saving mode management .............................................................................. 667
23.3.18. RTC interrupts..................................................................................................................... 668
23.4. Register definition................................................................................................ 669
23.4.1. Time register (RTC_TIME).................................................................................................. 669
23.4.2. Date register (RTC_DATE) ................................................................................................. 669
23.4.3. Control register (RTC_CTL)................................................................................................ 670
23.4.4. Status register (RTC_STAT) ............................................................................................... 673
23.4.5. Prescaler register (RTC_PSC) ........................................................................................... 675
23.4.6. Wakeup timer register (RTC_WUT).................................................................................... 675
23.4.7. Alarm 0 time and date register (RTC_ALRM0TD).............................................................. 676
23.4.8. Alarm 1 time and date register (RTC_ALRM1TD).............................................................. 677
23.4.9. Write protection key register (RTC_WPK) .......................................................................... 678
23.4.10. Sub second register (RTC_SS) .......................................................................................... 678
23.4.11. Shift function control register (RTC_SHIFTCTL) ................................................................ 679
23.4.12. Time of time stamp register (RTC_TTS)............................................................................. 680
23.4.13. Date of time stamp register (RTC_DTS)............................................................................. 680
23.4.14. Sub second of time stamp register (RTC_SSTS) ............................................................... 681
23.4.15. High resolution frequency compensation register (RTC_HRFC) ....................................... 681
23.4.16. Tamper register (RTC_TAMP) ............................................................................................ 682
23.4.17. Alarm 0 sub second register (RTC_ALRM0SS) ................................................................. 684
23.4.18. Alarm 1 sub second register (RTC_ALRM1SS) ................................................................. 685
23.4.19. Configuration register (RTC_CFG) ..................................................................................... 686
23.4.20. Backup registers (RTC_BKPx) (x=0..31)............................................................................ 687
24. TIMER (TIMERx) ................................................................................................688
24.1. Advanced timer (TIMERx, x=0, 7)........................................................................ 691
24.1.1. Overview ............................................................................................................................. 691
24.1.2. Characteristics .................................................................................................................... 691
24.1.3. Block diagram ..................................................................................................................... 692
24.1.4. Function overview ............................................................................................................... 692
24.1.5. Registers definition (TIMERx, x=0, 7)................................................................................. 735
24.2. General level0 timer (TIMERx, x=1,2,3,4,22,23,30,31)......................................... 804
24.2.1. Overview ............................................................................................................................. 804
24.2.2. Characteristics .................................................................................................................... 804
24.2.3. Block diagram ..................................................................................................................... 804
24.2.4. Function overview ............................................................................................................... 805
24.2.5. Registers definition (TIMERx, x=1,2,3,4,22,23,30,31)........................................................ 831
24.3. General level3 timer (TIMERx, x=14,40,41,42,43,44).......................................... 863
24.3.1. Overview ............................................................................................................................. 863
24.3.2. Characteristics .................................................................................................................... 863
24.3.3. Block diagram ..................................................................................................................... 863
24.3.4. Function overview ............................................................................................................... 864
24.3.5. Register definition(TIMERx, x=14,40,41,42,43,44) ............................................................ 890

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24.4. General level4 timer (TIMERx, x=15,16).............................................................. 924
24.4.1. Overview ............................................................................................................................. 924
24.4.2. Characteristics .................................................................................................................... 924
24.4.3. Block diagram ..................................................................................................................... 924
24.4.4. Function overview ............................................................................................................... 925
24.4.5. Register definition(TIMERx, x=15,16)................................................................................. 942
24.5. Basic timer (TIMERx, x=5,6,50,51)....................................................................... 968
24.5.1. Overview ............................................................................................................................. 968
24.5.2. Characteristics .................................................................................................................... 968
24.5.3. Block diagram ..................................................................................................................... 968
24.5.4. Function overview ............................................................................................................... 968
24.5.5. Registers definition (TIMERx, x=5,6,50,51)........................................................................ 972
25. Universal synchronous / asynchronous receiver / transmitter (USART).....980
25.1. Overview............................................................................................................... 980
25.2. Characteristics..................................................................................................... 980
25.3. Function overview................................................................................................ 982
25.3.1. USART frame format .......................................................................................................... 982
25.3.2. Baud rate generation .......................................................................................................... 983
25.3.3. USART transmitter.............................................................................................................. 984
25.3.4. USART receiver .................................................................................................................. 985
25.3.5. Use DMA for data buffer access ......................................................................................... 986
25.3.6. Hardware flow control ......................................................................................................... 988
25.3.7. Multi-processor communication .......................................................................................... 989
25.3.8. LIN mode ............................................................................................................................ 990
25.3.9. Synchronous mode............................................................................................................. 991
25.3.10. IrDA SIR ENDEC mode ...................................................................................................... 992
25.3.11. Half-duplex communication mode ...................................................................................... 994
25.3.12. Smartcard (ISO7816-3) mode ............................................................................................ 994
25.3.13. ModBus communication ..................................................................................................... 996
25.3.14. Receive / Transmitter FIFO................................................................................................. 996
25.3.15. Wakeup from deep-sleep mode.......................................................................................... 997
25.3.16. USART interrupts................................................................................................................ 998
25.4. Register definition.............................................................................................. 1000
25.4.1. Control register 0 (USART_CTL0).................................................................................... 1000
25.4.2. Control register 1 (USART_CTL1).................................................................................... 1003
25.4.3. Control register 2 (USART_CTL2).................................................................................... 1005
25.4.4. Baud rate generator register (USART_BAUD) ................................................................. 1009
25.4.5. Prescaler and guard time configuration register (USART_GP) ........................................ 1009
25.4.6. Receiver timeout register (USART_RT) ........................................................................... 1010
25.4.7. Command register (USART_CMD) ...................................................................................1011
25.4.8. Status register (USART_STAT) ........................................................................................ 1012

GD32H737/757/759 User Manual
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25.4.9. Interrupt status clear register (USART_INTC).................................................................. 1017
25.4.10. Receive data register (USART_RDATA) .......................................................................... 1018
25.4.11. Transmit data register (USART_TDATA) .......................................................................... 1019
25.4.12. USART coherence control register (USART_CHC).......................................................... 1019
25.4.13. USART FIFO control and status register (USART_FCS) ................................................. 1020
26. Inter-integrated circuit interface (I2C)...........................................................1024
26.1. Overview ............................................................................................................. 1024
26.2. Characteristics ................................................................................................... 1024
26.3. Function overview.............................................................................................. 1024
26.3.1. Clock requirements ........................................................................................................... 1025
26.3.2. I2C communication flow.................................................................................................... 1026
26.3.3. Noise filter ......................................................................................................................... 1029
26.3.4. I2C timings configuration .................................................................................................. 1029
26.3.5. I2C reset ........................................................................................................................... 1031
26.3.6. Data transfer ..................................................................................................................... 1031
26.3.7. I2C slave mode................................................................................................................. 1033
26.3.8. I2C master mode .............................................................................................................. 1038
26.3.9. SMBus support ................................................................................................................. 1043
26.3.10. SMBus mode .................................................................................................................... 1046
26.3.11. Wakeup from power saving mode .................................................................................... 1047
26.3.12. Use DMA for data transfer ................................................................................................ 1048
26.3.13. I2C error and interrupts..................................................................................................... 1048
26.3.14. I2C debug mode ............................................................................................................... 1049
26.4. Register definition.............................................................................................. 1050
26.4.1. Control register 0 (I2C_CTL0) .......................................................................................... 1050
26.4.2. Control register 1 (I2C_CTL1) .......................................................................................... 1052
26.4.3. Slave address register 0 (I2C_SADDR0) ......................................................................... 1054
26.4.4. Slave address register 1 (I2C_SADDR1) ......................................................................... 1055
26.4.5. Timing register (I2C_TIMING) .......................................................................................... 1056
26.4.6. Timeout register (I2C_TIMEOUT)..................................................................................... 1057
26.4.7. Status register (I2C_STAT) ............................................................................................... 1058
26.4.8. Status clear register (I2C_STATC) ................................................................................... 1061
26.4.9. PEC register (I2C_PEC) ................................................................................................... 1062
26.4.10. Receive data register (I2C_RDATA) ................................................................................. 1062
26.4.11. Transmit data register (I2C_TDATA)................................................................................. 1062
26.4.12. Control register 2 (I2C_CTL2) .......................................................................................... 1063
27. Serial peripheral interface/Inter-IC sound (SPI/I2S) .....................................1064
27.1. Overview............................................................................................................. 1064
27.2. Characteristics................................................................................................... 1064
27.2.1. SPI characteristics ............................................................................................................ 1064
27.2.2. I2S characteristics ............................................................................................................ 1064