GigaDevice Semiconductor GD32E23 Series User manual

GigaDevice Semiconductor Inc.
GD32E23x
Arm®Cortex®-M23 32-bit MCU
User Manual
Revision 1.5
(Jul. 2022)

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Table of Contents
Table of Contents...........................................................................................................2
List of Figures ..............................................................................................................13
List of Table..................................................................................................................19
1. System and memory architecture ........................................................................21
1.1. Arm®Cortex®-M23 processor ................................................................................... 21
1.2. System architecture .................................................................................................. 22
1.3. Memory map .............................................................................................................. 23
1.3.1. On-chip SRAM memory........................................................................................................ 26
1.3.2. On-chip Flash memory ......................................................................................................... 26
1.4. Boot configuration..................................................................................................... 27
1.5. System configuration registers (SYSCFG) .............................................................. 28
1.5.1. System configuration register 0 (SYSCFG_CFG0) .............................................................. 28
1.5.2. EXTI sources selection register 0 (SYSCFG_EXTISS0)...................................................... 31
1.5.3. EXTI sources selection register 1 (SYSCFG_EXTISS1)...................................................... 32
1.5.4. EXTI sources selection register 2 (SYSCFG_EXTISS2)...................................................... 33
1.5.5. EXTI sources selection register 3 (SYSCFG_EXTISS3)...................................................... 35
1.5.6. System configuration register 2 (SYSCFG_CFG2) .............................................................. 38
1.5.7. IRQ Latency register (SYSCFG_CPU_IRQ_LAT)................................................................ 39
1.6. Device electronic signature...................................................................................... 39
1.6.1. Memory density information.................................................................................................. 40
1.6.2. Unique device ID (96 bits) .................................................................................................... 40
2. Flash memory controller (FMC)............................................................................42
2.1. Overview .................................................................................................................... 42
2.2. Characteristics........................................................................................................... 42
2.3. Function overview..................................................................................................... 42
2.3.1. Flash memory architecture ................................................................................................... 42
2.3.2. Read operations ................................................................................................................... 43
2.3.3. Unlock the FMC_CTL register .............................................................................................. 44
2.3.4. Page erase............................................................................................................................ 44
2.3.5. Mass erase ........................................................................................................................... 46
2.3.6. Main flash programming ....................................................................................................... 47
2.3.7. OTP programming ................................................................................................................ 49
2.3.8. Option byte erase ................................................................................................................. 50
2.3.9. Option byte programming ..................................................................................................... 50
2.3.10. Option byte description......................................................................................................... 51

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2.3.11. Page erase/Program protection............................................................................................ 52
2.3.12. Security protection................................................................................................................ 52
2.4. Register definition..................................................................................................... 54
2.4.1. Wait state register (FMC_WS).............................................................................................. 54
2.4.2. Unlock key register (FMC_KEY)........................................................................................... 54
2.4.3. Option byte unlock key register (FMC_OBKEY)................................................................... 55
2.4.4. Status register (FMC_STAT)................................................................................................. 55
2.4.5. Control register (FMC_CTL)................................................................................................. 56
2.4.6. Address register (FMC_ADDR) ............................................................................................ 58
2.4.7. Option byte status register (FMC_OBSTAT)......................................................................... 58
2.4.8. Write protection register (FMC_WP)..................................................................................... 59
2.4.9. Product ID register (FMC_PID)............................................................................................. 59
3. Power management unit (PMU)............................................................................60
3.1. Overview .................................................................................................................... 60
3.2. Characteristics........................................................................................................... 60
3.3. Function overview..................................................................................................... 60
3.3.1. Backup domain..................................................................................................................... 61
3.3.2. VDD / VDDA power domain...................................................................................................... 62
3.3.3. 1.2V power domain............................................................................................................... 64
3.3.4. Power saving modes ............................................................................................................ 64
3.4. PMU registers ............................................................................................................ 67
3.4.1. Control register (PMU_CTL)................................................................................................. 67
3.4.2. Control and status register (PMU_CS)................................................................................. 68
4. Reset and clock unit (RCU)...................................................................................72
4.1. Reset control unit (RCTL) ......................................................................................... 72
4.1.1. Overview............................................................................................................................... 72
4.1.2. Function overview................................................................................................................. 72
4.2. Clock control unit (CCTL) ......................................................................................... 73
4.2.1. Overview............................................................................................................................... 73
4.2.2. Characteristics...................................................................................................................... 75
4.2.3. Function overview................................................................................................................. 75
4.3. Register definition..................................................................................................... 79
4.3.1. Control register 0 (RCU_CTL0)............................................................................................ 79
4.3.2. Configuration register 0 (RCU_CFG0) ................................................................................. 80
4.3.3. Interrupt register (RCU_INT) ................................................................................................ 84
4.3.4. APB2 reset register (RCU_APB2RST)................................................................................. 87
4.3.5. APB1 reset register (RCU_APB1RST)................................................................................. 88
4.3.6. AHB enable register (RCU_AHBEN).................................................................................... 90
4.3.7. APB2 enable register (RCU_APB2EN) ................................................................................ 91
4.3.8. APB1 enable register (RCU_APB1EN) ................................................................................ 93

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4.3.9. Backup domain control register (RCU_BDCTL)................................................................... 94
4.3.10. Reset source /clock register (RCU_RSTSCK) ..................................................................... 96
4.3.11. AHB reset register (RCU_AHBRST)..................................................................................... 97
4.3.12. Configuration register 1 (RCU_CFG1) ................................................................................. 98
4.3.13. Configuration register 2 (RCU_CFG2) ................................................................................. 99
4.3.14. Control register 1 (RCU_CTL1).......................................................................................... 100
4.3.15. Voltage key register (RCU_VKEY) ..................................................................................... 101
4.3.16. Deep-sleep mode voltage register (RCU_DSV)................................................................. 101
5. Interrupt/event controller (EXTI).........................................................................103
5.1. Overview .................................................................................................................. 103
5.2. Characteristics......................................................................................................... 103
5.3. Interrupts function overview................................................................................... 103
5.4. External interrupt and event (EXTI) block diagram ............................................... 106
5.5. External interrupt and Event function overview.................................................... 106
5.6. Register definition................................................................................................... 109
5.6.1. Interrupt enable register (EXTI_INTEN) ............................................................................. 109
5.6.2. Event enable register (EXTI_EVEN) .................................................................................. 109
5.6.3. Rising edge trigger enable register (EXTI_RTEN) ..............................................................110
5.6.4. Falling edge trigger enable register (EXTI_FTEN)..............................................................110
5.6.5. Software interrupt event register (EXTI_SWIEV) ................................................................111
5.6.6. Pending register (EXTI_PD) ................................................................................................112
6. General-purpose and alternate-function I/Os (GPIO and AFIO)....................... 113
6.1. Overview ...................................................................................................................113
6.2. Characteristics..........................................................................................................113
6.3. Function overview....................................................................................................113
6.3.1. GPIO pin configuration ........................................................................................................114
6.3.2. Alternate functions (AF).......................................................................................................115
6.3.3. Additional functions..............................................................................................................115
6.3.4. Input configuration ...............................................................................................................115
6.3.5. Output configuration ............................................................................................................116
6.3.6. Analog configuration............................................................................................................116
6.3.7. Alternate function (AF) configuration...................................................................................117
6.3.8. GPIO locking function..........................................................................................................118
6.3.9. GPIO single cycle toggle function........................................................................................118
6.4. Register definition....................................................................................................119
6.4.1. Port control register (GPIOx_CTL, x=A..C,F)......................................................................119
6.4.2. Port output mode register (GPIOx_OMODE, x=A..C,F)..................................................... 120
6.4.3. Port output speed register (GPIOx_OSPD, x=A..C,F)........................................................ 122
6.4.4. Port pull-up/down register (GPIOx_PUD, x=A..C,F)........................................................... 124

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6.4.5. Port input status register (GPIOx_ISTAT, x=A..C,F)........................................................... 125
6.4.6. Port output control register (GPIOx_OCTL, x=A..C,F) ....................................................... 126
6.4.7. Port bit operate register (GPIOx_BOP, x=A..C,F)............................................................... 126
6.4.8. Port configuration lock register (GPIOx_LOCK, x=A,B) ..................................................... 127
6.4.9. Alternate function selected register 0 (GPIOx_AFSEL0, x=A,B,C).................................... 128
6.4.10. Alternate function selected register 1 (GPIOx_AFSEL1, x=A,B,C).................................... 129
6.4.11. Bit clear register (GPIOx_BC, x=A..C,F) ............................................................................ 130
6.4.12. Port bit toggle register (GPIOx_TG, x=A..C,F)................................................................... 130
7. Cyclic redundancy checks management unit (CRC) ........................................132
7.1. Overview .................................................................................................................. 132
7.2. Characteristics......................................................................................................... 132
7.3. Function overview................................................................................................... 133
7.4. Register definition................................................................................................... 135
7.4.1. Data register (CRC_DATA)................................................................................................. 135
7.4.2. Free data register (CRC_FDATA)....................................................................................... 135
7.4.3. Control register (CRC_CTL)............................................................................................... 136
7.4.4. Initialization data register (CRC_IDATA)............................................................................. 137
7.4.5. Polynomial register (CRC_POLY)....................................................................................... 137
8. Direct memory access controller (DMA)............................................................138
8.1. Overview .................................................................................................................. 138
8.2. Characteristics......................................................................................................... 138
8.3. Block diagram.......................................................................................................... 139
8.4. Function overview................................................................................................... 139
8.4.1. DMA operation.................................................................................................................... 139
8.4.2. Peripheral handshake......................................................................................................... 141
8.4.3. Arbitration............................................................................................................................ 142
8.4.4. Address generation............................................................................................................. 142
8.4.5. Circular mode...................................................................................................................... 142
8.4.6. Memory to memory mode................................................................................................... 142
8.4.7. Channel configuration......................................................................................................... 143
8.4.8. Interrupt............................................................................................................................... 143
8.4.9. DMA request mapping ........................................................................................................ 144
8.5. Register definition................................................................................................... 147
8.5.1. Interrupt flag register (DMA_INTF)..................................................................................... 147
8.5.2. Interrupt flag clear register (DMA_INTC)............................................................................ 147
8.5.3. Channel x control register (DMA_CHxCTL) ....................................................................... 148
8.5.4. Channel x counter register (DMA_CHxCNT)...................................................................... 150
8.5.5. Channel x peripheral base address register (DMA_CHxPADDR)...................................... 151
8.5.6. Channel x memory base address register (DMA_CHxMADDR)........................................ 151

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9. Debug (DBG) ........................................................................................................153
9.1. Overview .................................................................................................................. 153
9.2. SW function overview ............................................................................................. 153
9.2.1. Pin assignment ................................................................................................................... 153
9.3. Debug hold function overview................................................................................ 153
9.3.1. Debug support for power saving mode............................................................................... 153
9.3.2. Debug support for TIMER, I2C, RTC, WWDGT and FWDGT............................................ 154
9.4. Register definition................................................................................................... 155
9.4.1. ID code register (DBG_ID).................................................................................................. 155
9.4.2. Control register 0 (DBG_CTL0).......................................................................................... 155
9.4.3. Control register 1 (DBG_CTL1).......................................................................................... 157
10. Analog to digital converter (ADC)...................................................................159
10.1. Overview............................................................................................................... 159
10.2. Characteristics..................................................................................................... 159
10.3. Pins and internal signals..................................................................................... 160
10.4. Function overview................................................................................................ 161
10.4.1. Foreground calibration function.......................................................................................... 161
10.4.2. Dual clock domain architecture........................................................................................... 162
10.4.3. ADC enable......................................................................................................................... 162
10.4.4. Routine sequence............................................................................................................... 162
10.4.5. Operation mode.................................................................................................................. 162
10.4.6. Conversion result threshold monitor function ..................................................................... 165
10.4.7. Data storage mode ............................................................................................................. 165
10.4.8. Sample time configuration .................................................................................................. 167
10.4.9. External trigger configuration.............................................................................................. 167
10.4.10. DMA request ....................................................................................................................... 167
10.4.11. ADC internal channels........................................................................................................ 167
10.4.12. Programmable resolution (DRES) - fast conversion mode ................................................ 168
10.4.13. On-chip hardware oversampling......................................................................................... 168
10.4.14. ADC interrupts .................................................................................................................... 171
10.5. Register definition................................................................................................ 172
10.5.1. Status register (ADC_STAT)............................................................................................... 172
10.5.2. Control register 0 (ADC_CTL0) .......................................................................................... 172
10.5.3. Control register 1 (ADC_CTL1) .......................................................................................... 174
10.5.4. Sample time register 0 (ADC_SAMPT0) ............................................................................ 175
10.5.5. Sample time register 1 (ADC_SAMPT1) ............................................................................ 176
10.5.6. Watchdog low threshold register (ADC_WDLT) ................................................................. 177
10.5.7. Routine sequence register 0 (ADC_RSQ0)........................................................................ 177
10.5.8. Routine sequence register 1 (ADC_RSQ1)........................................................................ 178
10.5.9. Routine sequence register 2 (ADC_RSQ2)........................................................................ 179

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10.5.10. Routine data register (ADC_RDATA).................................................................................. 179
10.5.11. Oversampling control register (ADC_OVSAMPCTL) ......................................................... 180
11. Comparator (CMP)............................................................................................182
11.1. Introduction.......................................................................................................... 182
11.2. Main features........................................................................................................ 182
11.3. Function description............................................................................................ 182
11.3.1. CMP clock and reset........................................................................................................... 183
11.3.2. CMP I/O configuration......................................................................................................... 183
11.3.3. CMP operating mode.......................................................................................................... 183
11.3.4. CMP hysteresis................................................................................................................... 184
11.3.5. CMP register write protection ............................................................................................. 184
11.4. CMP registers....................................................................................................... 185
11.4.1. Control/status register (CMP_CS)...................................................................................... 185
12. Watchdog timer (WDGT) ..................................................................................187
12.1. Free watchdog timer (FWDGT)............................................................................ 187
12.1.1. Overview............................................................................................................................ 187
12.1.2. Characteristics.................................................................................................................. 187
12.1.3. Function overview ............................................................................................................ 187
12.1.4. Register definition ............................................................................................................ 190
12.2. Window watchdog timer (WWDGT)..................................................................... 194
12.2.1. Overview............................................................................................................................ 194
12.2.2. Characteristics.................................................................................................................. 194
12.2.3. Function overview ............................................................................................................ 194
12.2.4. Register definition ............................................................................................................ 197
13. Real-time clock(RTC)........................................................................................199
13.1. Overview............................................................................................................... 199
13.2. Characteristics..................................................................................................... 199
13.3. Function overview................................................................................................ 200
13.3.1. Block diagram..................................................................................................................... 200
13.3.2. Clock source and prescalers .............................................................................................. 201
13.3.3. Shadow registers introduction ............................................................................................ 201
13.3.4. Configurable and field maskable alarm .............................................................................. 201
13.3.5. RTC initialization and configuration .................................................................................... 202
13.3.6. Calendar reading ................................................................................................................ 203
13.3.7. Resetting the RTC .............................................................................................................. 204
13.3.8. RTC shift function ............................................................................................................... 205
13.3.9. RTC reference clock detection ........................................................................................... 205
13.3.10. RTC smooth digital calibration............................................................................................ 206
13.3.11. Time-stamp function (Only for GD32E230xx devices) ....................................................... 208

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13.3.12. Tamper detection ................................................................................................................ 208
13.3.13. Calibration clock output ...................................................................................................... 209
13.3.14. Alarm output........................................................................................................................ 209
13.3.15. RTC power saving mode management.............................................................................. 210
13.3.16. RTC interrupts..................................................................................................................... 210
13.4. Register definition................................................................................................ 212
13.4.1. Time register (RTC_TIME).................................................................................................. 212
13.4.2. Date register (RTC_DATE)................................................................................................. 212
13.4.3. Control register (RTC_CTL)................................................................................................ 213
13.4.4. Status register (RTC_STAT) ............................................................................................... 217
13.4.5. Prescaler register (RTC_PSC) ........................................................................................... 220
13.4.6. Alarm 0 time and date register (RTC_ALRM0TD).............................................................. 220
13.4.7. Write protection key register (RTC_WPK).......................................................................... 221
13.4.8. Sub second register (RTC_SS) .......................................................................................... 222
13.4.9. Shift function control register (RTC_SHIFTCTL)................................................................ 222
13.4.10. Time of time stamp register (RTC_TTS)............................................................................. 223
13.4.11. Date of time stamp register (RTC_DTS)............................................................................. 224
13.4.12. Sub second of time stamp register (RTC_SSTS)............................................................... 224
13.4.13. High resolution frequency compensation register (RTC_HRFC) ....................................... 225
13.4.14. Tamper register (RTC_TAMP) ............................................................................................ 226
13.4.15. Alarm 0 sub second register (RTC_ALRM0SS) ................................................................. 230
13.4.16. Backup registers (RTC_BKPx) (x=0..4).............................................................................. 231
14. Timer (TIMERx) .................................................................................................232
14.1. Advanced timer (TIMERx, x=0)............................................................................ 233
14.1.1. Overview............................................................................................................................. 233
14.1.2. Characteristics.................................................................................................................... 233
14.1.3. Block diagram..................................................................................................................... 234
14.1.4. Function overview............................................................................................................... 235
14.1.5. TIMERx registers(x=0)........................................................................................................ 262
14.2. General level0 timer (TIMERx, x=2)..................................................................... 290
14.2.1. Overview............................................................................................................................. 290
14.2.2. Characteristics.................................................................................................................... 290
14.2.3. Block diagram..................................................................................................................... 290
14.2.4. Function overview............................................................................................................... 291
14.2.5. TIMERx registers(x=2)........................................................................................................ 305
14.3. General level2 timer (TIMERx, x=13)................................................................... 328
14.3.1. Overview............................................................................................................................. 328
14.3.2. Characteristics.................................................................................................................... 328
14.3.3. Block diagram..................................................................................................................... 328
14.3.4. Function overview............................................................................................................... 330
14.3.5. TIMERx registers(x=13)...................................................................................................... 338

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14.4. General level3 timer (TIMERx, x=14)................................................................... 348
14.4.1. Overview............................................................................................................................. 348
14.4.2. Characteristics.................................................................................................................... 348
14.4.3. Block diagram..................................................................................................................... 348
14.4.4. Function overview............................................................................................................... 349
14.4.5. TIMERx registers(x=14)...................................................................................................... 366
14.5. General level4 timer (TIMERx, x=15, 16)............................................................. 386
14.5.1. Overview............................................................................................................................. 386
14.5.2. Characteristics.................................................................................................................... 386
14.5.3. Block diagram..................................................................................................................... 386
14.5.4. Function overview............................................................................................................... 387
14.5.5. TIMERx registers(x=15, 16)................................................................................................ 401
14.6. Basic timer (TIMERx, x=5) ................................................................................... 417
14.6.1. Overview............................................................................................................................. 417
14.6.2. Characteristics.................................................................................................................... 417
14.6.3. Block diagram..................................................................................................................... 417
14.6.4. Function overview............................................................................................................... 417
14.6.5. TIMERx registers(x=5)........................................................................................................ 422
15. Infrared ray port (IFRP) ....................................................................................427
15.1. Overview............................................................................................................... 427
15.2. Characteristics..................................................................................................... 427
15.3. Function overview................................................................................................ 427
16. Universal synchronous/asynchronous receiver /transmitter (USART)........429
16.1. Overview............................................................................................................... 429
16.2. Characteristics..................................................................................................... 429
16.3. Function overview................................................................................................ 431
16.3.1. USART frame format .......................................................................................................... 431
16.3.2. Baud rate generation .......................................................................................................... 432
16.3.3. USART transmitter.............................................................................................................. 433
16.3.4. USART receiver.................................................................................................................. 434
16.3.5. Use DMA for data buffer access......................................................................................... 435
16.3.6. Hardware flow control......................................................................................................... 437
16.3.7. Multi-processor communication.......................................................................................... 438
16.3.8. LIN mode ............................................................................................................................ 439
16.3.9. Synchronous mode............................................................................................................. 440
16.3.10. IrDA SIR ENDEC mode ...................................................................................................... 441
16.3.11. Half-duplex communication mode ...................................................................................... 442
16.3.12. Smartcard (ISO7816-3) mode ............................................................................................ 442
16.3.13. ModBus communication ..................................................................................................... 444
16.3.14. Receive FIFO...................................................................................................................... 445

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16.3.15. Wakeup from Deep-sleep mode......................................................................................... 445
16.3.16. USART interrupts................................................................................................................ 446
16.4. Register definition................................................................................................ 448
16.4.1. Control register 0 (USART_CTL0)...................................................................................... 448
16.4.2. Control register 1 (USART_CTL1)...................................................................................... 450
16.4.3. Control register 2 (USART_CTL2)...................................................................................... 453
16.4.4. Baud rate generator register (USART_BAUD)................................................................... 456
16.4.5. Prescaler and guard time configuration register (USART_GP).......................................... 456
16.4.6. Receiver timeout register (USART_RT) ............................................................................. 457
16.4.7. Command register (USART_CMD) .................................................................................... 458
16.4.8. Status register (USART_STAT) .......................................................................................... 459
16.4.9. Interrupt status clear register (USART_INTC).................................................................... 462
16.4.10. Receive data register (USART_RDATA) ............................................................................ 464
16.4.11. Transmit data register (USART_TDATA)............................................................................ 464
16.4.12. USART coherence control register (USART_CHC)............................................................ 465
16.4.13. USART receive FIFOcontrol and status register (USART_RFCS)..................................... 465
17. Inter-integrated circuit interface (I2C).............................................................467
17.1. Overview............................................................................................................... 467
17.2. Characteristics..................................................................................................... 467
17.3. Function overview................................................................................................ 467
17.3.1. SDA and SCL lines ............................................................................................................. 468
17.3.2. Data validation.................................................................................................................... 469
17.3.3. START and STOP signal .................................................................................................... 469
17.3.4. Clock synchronization......................................................................................................... 469
17.3.5. Arbitration............................................................................................................................ 470
17.3.6. I2C communication flow...................................................................................................... 470
17.3.7. Programming model ........................................................................................................... 471
17.3.8. SCL line stretching.............................................................................................................. 479
17.3.9. Use DMA for data transfer.................................................................................................. 480
17.3.10. Packet error checking......................................................................................................... 480
17.3.11. SMBus support ................................................................................................................... 480
17.3.12. SAM_V support................................................................................................................... 482
17.3.13. Status, errors and interrupts............................................................................................... 482
17.4. Register definition................................................................................................ 484
17.4.1. Control register 0 (I2C_CTL0) ............................................................................................ 484
17.4.2. Control register 1 (I2C_CTL1) ............................................................................................ 486
17.4.3. Slave address register 0 (I2C_SADDR0) ........................................................................... 487
17.4.4. Slave address register 1 (I2C_SADDR1) ........................................................................... 487
17.4.5. Transfer buffer register (I2C_DATA)................................................................................... 488
17.4.6. Transfer status register 0 (I2C_STAT0).............................................................................. 488
17.4.7. Transfer status register 1 (I2C_STAT1).............................................................................. 491
17.4.8. Clock configure register (I2C_CKCFG) .............................................................................. 492