GigaDevice Semiconductor GD32F1 0 Series User manual

GigaDevice Semiconductor Inc.
GD32F1x0
ARM® Cortex®-M3 32-bit MCU
User Manual
Revision 3.6
(Jul. 2022)

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Table of Contents
Table of Contents ...........................................................................................................2
List of Figures ..............................................................................................................17
List of Tables ................................................................................................................24
1. System and memory architecture ........................................................................27
1.1. ARM Cortex-M3 processor........................................................................................ 27
1.2. System architecture .................................................................................................. 28
1.3. Memory map .............................................................................................................. 30
1.3.1. Bit-banding............................................................................................................................ 35
1.3.2. On-chip SRAM memory........................................................................................................ 35
1.3.3. On-chip Flash memory ......................................................................................................... 36
1.4. Boot configuration..................................................................................................... 36
1.5. System configuration registers (SYSCFG) .............................................................. 38
1.5.1. System configuration register 0 (SYSCFG_CFG0) .............................................................. 38
1.5.2. System configuration register 1 (SYSCFG_CFG1) .............................................................. 39
1.5.3. EXTI sources selection register 0 (SYSCFG_EXTISS0)...................................................... 39
1.5.4. EXTI sources selection register 1 (SYSCFG_EXTISS1)...................................................... 41
1.5.5. EXTI sources selection register 2 (SYSCFG_EXTISS2)...................................................... 42
1.5.6. EXTI sources selection register 3 (SYSCFG_EXTISS3)...................................................... 43
1.5.7. System configuration register 2 (SYSCFG_CFG2) .............................................................. 44
1.6. Device electronic signature...................................................................................... 45
1.6.1. Memory density information.................................................................................................. 46
1.6.2. Unique device ID (96 bits) .................................................................................................... 46
2. Flash memory controller (FMC)............................................................................48
2.1. Overview .................................................................................................................... 48
2.2. Characteristics........................................................................................................... 48
2.3. Function overview..................................................................................................... 48
2.3.1. Flash memory architecture ................................................................................................... 48
2.3.2. Read operations ................................................................................................................... 49
2.3.3. Unlock the FMC_CTL register .............................................................................................. 49
2.3.4. Page erase............................................................................................................................ 49
2.3.5. Mass erase ........................................................................................................................... 50
2.3.6. Main flash programming ....................................................................................................... 52
2.3.7. Option bytes erase................................................................................................................ 53
2.3.8. Option bytes programming ................................................................................................... 54
2.3.9. Option bytes description ....................................................................................................... 54

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2.3.10. Page erase/Program protection............................................................................................ 55
2.3.11. Security protection ................................................................................................................ 56
2.4. Register definition..................................................................................................... 57
2.4.1. Wait state register (FMC_WS).............................................................................................. 57
2.4.2. Unlock key register (FMC_KEY)........................................................................................... 57
2.4.3. Option bytes unlock key register (FMC_OBKEY) ................................................................. 58
2.4.4. Status register (FMC_STAT)................................................................................................. 58
2.4.5. Control register (FMC_CTL) ................................................................................................. 59
2.4.6. Address register (FMC_ADDR) ............................................................................................ 60
2.4.7. Option bytes status register (FMC_OBSTAT)....................................................................... 61
2.4.8. Write protection register (FMC_WP)..................................................................................... 61
2.4.9. Wait state enable register (FMC_WSEN) ............................................................................. 62
2.4.10. Product ID register (FMC_PID)............................................................................................. 63
3. Power management unit (PMU) ............................................................................64
3.1. Overview .................................................................................................................... 64
3.2. Characteristics........................................................................................................... 64
3.3. Function overview..................................................................................................... 64
3.3.1. Backup domain ..................................................................................................................... 66
3.3.2. VDD / VDDA power domain ...................................................................................................... 67
3.3.3. VDD domain ........................................................................................................................... 67
3.3.4. 1.2V power domain for GD32F130xx and GD32F150xx devices......................................... 69
3.3.5. 1.8V power domain for GD32F170xx and GD32F190xx devices......................................... 69
3.3.6. Power saving modes ............................................................................................................ 70
3.4. Register definition..................................................................................................... 72
3.4.1. Control register (PMU_CTL) ................................................................................................. 72
3.4.2. Power control/status register (PMU_CS).............................................................................. 75
4. Reset and clock unit (RCU)...................................................................................77
4.1. Reset control unit (RCTL) ......................................................................................... 77
4.1.1. Overview ............................................................................................................................... 77
4.1.2. Function overview ................................................................................................................. 77
4.2. Clock control unit (CCTL) ......................................................................................... 78
4.2.1. Overview ............................................................................................................................... 78
4.2.2. Characteristics ...................................................................................................................... 81
4.2.3. Function overview ................................................................................................................. 81
4.3. Register definition..................................................................................................... 86
4.3.1. Control register 0 (RCU_CTL0) ............................................................................................ 86
4.3.2. Configuration register 0 (RCU_CFG0) ................................................................................. 87
4.3.3. Interrupt register (RCU_INT) ................................................................................................ 94
4.3.4. APB2 reset register (RCU_APB2RST) ............................................................................... 100
4.3.5. APB1 reset register (RCU_APB1RST) ............................................................................... 101

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4.3.6. AHB enable register (RCU_AHBEN) .................................................................................. 106
4.3.7. APB2 enable register (RCU_APB2EN) .............................................................................. 107
4.3.8. APB1 enable register (RCU_APB1EN) .............................................................................. 109
4.3.9. Backup domain control register (RCU_BDCTL) ..................................................................113
4.3.10. Reset source /clock register (RCU_RSTSCK) ....................................................................116
4.3.11. AHB reset register (RCU_AHBRST)....................................................................................118
4.3.12. Configuration register 1 (RCU_CFG1) ................................................................................119
4.3.13. Configuration register 2 (RCU_CFG2) ............................................................................... 120
4.3.14. Control register 1 (RCU_CTL1) .......................................................................................... 122
4.3.15. Configuration register 3 (RCU_CFG3) of GD32F170xx and GD32F190xx devices .......... 123
4.3.16. APB1 additional enable register (RCU_ADDAPB1EN) ...................................................... 124
4.3.17. APB1 additional reset register (RCU_ADDAPB1RST)....................................................... 124
4.3.18. Voltage key register (RCU_VKEY) ..................................................................................... 125
4.3.19. Deep-sleep mode voltage register (RCU_DSV) ................................................................. 125
4.3.20. Power down voltage select register (RCU_PDVSEL) of GD32F130xx and GD32F150xx
devices 126
5. Interrupt/event controller (EXTI).........................................................................128
5.1. Overview .................................................................................................................. 128
5.2. Characteristics......................................................................................................... 128
5.3. Interrupts function overview................................................................................... 128
5.4. External interrupt and event (EXTI) block diagram ............................................... 132
5.5. External interrupt and Event function overview .................................................... 133
5.6. Register definition ................................................................................................... 136
5.6.1. Interrupt Enable register (EXTI_INTEN) ............................................................................. 136
5.6.2. Event enable register (EXTI_EVEN) .................................................................................. 136
5.6.3. Rising edge trigger enable register (EXTI_RTEN) ............................................................. 137
5.6.4. Falling edge trigger enable register (EXTI_FTEN) ............................................................. 137
5.6.5. Software interrupt event register (EXTI_SWIEV) ............................................................... 138
5.6.6. Pending register (EXTI_PD) ............................................................................................... 139
6. General-purpose I/Os (GPIO) ..............................................................................140
6.1. Overview .................................................................................................................. 140
6.2. Characiteristics........................................................................................................ 140
6.3. Function overview................................................................................................... 140
6.3.1. GPIO pin configuration ....................................................................................................... 141
6.3.2. Alternate functions (AF) ...................................................................................................... 142
6.3.3. Additional functions............................................................................................................. 142
6.3.4. Input configuration .............................................................................................................. 142
6.3.5. Output configuration ........................................................................................................... 143
6.3.6. Analog configuration ........................................................................................................... 144
6.3.7. Alternate function (AF) configuration .................................................................................. 144

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6.3.8. GPIO locking function ......................................................................................................... 145
6.3.9. GPIO single cycle toggle function....................................................................................... 145
6.4. Register definition................................................................................................... 146
6.4.1. Port control register (GPIOx_CTL, x=A..D,F) ..................................................................... 146
6.4.2. Port output mode register (GPIOx_OMODE, x=A..D,F) ..................................................... 147
6.4.3. Port output speed register (GPIOx_OSPD, x=A..D,F)........................................................ 149
6.4.4. Port pull-up/down register (GPIOx_PUD, x=A..D,F)........................................................... 151
6.4.5. Port input status register (GPIOx_ISTAT, x=A..D,F) ........................................................... 152
6.4.6. Port output control register (GPIOx_OCTL, x=A..D,F) ....................................................... 153
6.4.7. Port bit operate register (GPIOx_BOP, x=A..D,F)............................................................... 153
6.4.8. Port configuration lock register (GPIOx_LOCK, x=A, B) .................................................... 154
6.4.9. Alternate function selected register0 (GPIOx_AFSEL0, x=A, B, C) ................................... 155
6.4.10. Alternate function selected register1 (GPIOx_AFSEL1, x=A,B,C) ..................................... 156
6.4.11. Bit clear register (GPIOx_BC, x=A..D,F) ............................................................................ 157
6.4.12. Port bit toggle register (GPIOx_TG, x=A..D,F) (Only for GD32F170xx and GD32F190xx
devices) 158
7. Cyclic redundancy checks management unit (CRC) ........................................159
7.1. Overview .................................................................................................................. 159
7.2. Characteristics......................................................................................................... 159
7.3. Function overview................................................................................................... 160
7.4. Register definition................................................................................................... 162
7.4.1. Data Register (CRC_DATA)................................................................................................ 162
7.4.2. Free Data Register (CRC_FDATA)..................................................................................... 162
7.4.3. Control Register (CRC_CTL).............................................................................................. 163
7.4.4. Initialization Data Register (CRC_IDATA)........................................................................... 163
8. Direct memory access controller (DMA)............................................................165
8.1. Overview .................................................................................................................. 165
8.2. Characteristics......................................................................................................... 165
8.3. Block diagram.......................................................................................................... 166
8.4. Function overview................................................................................................... 166
8.4.1. DMA operation .................................................................................................................... 166
8.4.2. Peripheral handshake......................................................................................................... 168
8.4.3. Arbitration............................................................................................................................ 168
8.4.4. Address generation............................................................................................................. 169
8.4.5. Circular mode...................................................................................................................... 169
8.4.6. Memory to memory mode................................................................................................... 169
8.4.7. Channel configuration......................................................................................................... 169
8.4.8. Interrupt............................................................................................................................... 170
8.4.9. DMA request mapping ........................................................................................................ 171

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8.5. Register definition................................................................................................... 174
8.5.1. Interrupt flag register (DMA_INTF) ..................................................................................... 174
8.5.2. Interrupt flag clear register (DMA_INTC) ............................................................................ 174
8.5.3. Channel x control register (DMA_CHxCTL) ....................................................................... 175
8.5.4. Channel x counter register (DMA_CHxCNT)...................................................................... 177
8.5.5. Channel x peripheral base address register (DMA_CHxPADDR) ...................................... 178
8.5.6. Channel x memory base address register (DMA_CHxMADDR) ........................................ 178
9. Debug (DBG) ........................................................................................................180
9.1. Overview .................................................................................................................. 180
9.2. Serial Wire Debug port overview............................................................................ 180
9.2.1. Pin assignment ................................................................................................................... 180
9.2.2. JEDEC-106 ID code ........................................................................................................... 180
9.3. Debug hold function overview................................................................................ 181
9.3.1. Debug support for power saving mode............................................................................... 181
9.3.2. Debug support for TIMER, I2C, RTC, WWDGT and FWDGT ............................................ 181
9.4. DBG registers .......................................................................................................... 182
9.4.1. ID code register (DBG_ID).................................................................................................. 182
9.4.2. Control register 0(DBG_CTL0) ........................................................................................... 182
9.4.3. Control register 1 (DBG_CTL1) .......................................................................................... 186
10. Analog to digital converter (ADC) ...................................................................188
10.1. Overview............................................................................................................... 188
10.2. Characteristics..................................................................................................... 188
10.3. Pins and internal signals..................................................................................... 189
10.4. Function overview................................................................................................ 191
10.4.1. Foreground calibration function .......................................................................................... 192
10.4.2. Dual clock domain architecture........................................................................................... 193
10.4.3. ADCON enable ................................................................................................................... 193
10.4.4. Routine sequence............................................................................................................... 193
10.4.5. Operation modes ................................................................................................................ 193
10.4.6. Conversion result threshold monitor function ..................................................................... 196
10.4.7. Data storage mode ............................................................................................................. 196
10.4.8. Sample time configuration .................................................................................................. 197
10.4.9. External trigger configuration.............................................................................................. 198
10.4.10. DMA request ................................................................................................................... 198
10.4.11. ADC internal channels .................................................................................................... 198
10.4.12. Battery voltage monitoring .............................................................................................. 199
10.4.13. ADC interrupts ................................................................................................................ 199
10.4.14. Programmable resolution (DRES) .................................................................................. 199
10.4.15. On-chip hardware oversampling ..................................................................................... 200
10.5. Register definition................................................................................................ 203

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10.5.1. Status register (ADC_STAT) ............................................................................................... 203
10.5.2. Control register 0 (ADC_CTL0) .......................................................................................... 203
10.5.3. Control register 1 (ADC_CTL1) .......................................................................................... 206
10.5.4. Sampling time register 0 (ADC_SAMPT0) ......................................................................... 208
10.5.5. Sampling time register 1 (ADC_SAMPT1) ......................................................................... 210
10.5.6. Watchdog high threshold register (ADC_WDHT) ................................................................211
10.5.7. Watchdog low threshold register (ADC_WDLT) ..................................................................211
10.5.8. Routine sequence register 0 (ADC_RSQ0)........................................................................ 212
10.5.9. Routine sequence register 1 (ADC_RSQ1)........................................................................ 212
10.5.10. Routine sequence register 2 (ADC_RSQ2) .................................................................... 213
10.5.11. Routine data register (ADC_RDATA).............................................................................. 213
10.5.12. Oversampling control register (ADC_OVSAMPCTL)...................................................... 214
11. Digital-to-analog converter (DAC) ...................................................................216
11.1. Overview ............................................................................................................... 216
11.2. Characteristic ....................................................................................................... 216
11.3. Function overview................................................................................................ 217
11.3.1. DAC enable......................................................................................................................... 217
11.3.2. DAC output buffer ............................................................................................................... 217
11.3.3. DAC data configuration....................................................................................................... 218
11.3.4. DAC trigger ......................................................................................................................... 218
11.3.5. DAC workflow ..................................................................................................................... 219
11.3.6. DAC output calculate .......................................................................................................... 219
11.3.7. DMA function....................................................................................................................... 219
11.3.8. DAC concurrent conversion for GD32F190xx devices ....................................................... 219
11.4. Register definition................................................................................................ 221
11.4.1. Control register (DAC_CTL) ............................................................................................... 221
11.4.2. Software trigger register (DAC_SWT) ................................................................................ 224
11.4.3. DAC0 12-bit right-aligned data holding register (DAC0_R12DH)....................................... 225
11.4.4. DAC0 12-bit left-aligned data holding register (DAC0_L12DH) ......................................... 225
11.4.5. DAC0 8-bit right-aligned data holding register (DAC0_R8DH)........................................... 226
11.4.6. DAC1 12-bit right-aligned data holding register (DAC1_R12DH) of GD32F190xx devices 226
11.4.7. DAC1 12-bit left-aligned data holding register (DAC1_L12DH) of GD32F190xx devices.. 227
11.4.8. DAC1 8-bit right-aligned data holding register (DAC1_R8DH) of GD32F190xx devices ... 227
11.4.9. DAC concurrent mode 12-bit right-aligned data holding register (DACC_R12DH) of
GD32F190xx devices......................................................................................................................... 228
11.4.10. DAC concurrent mode 12-bit left-aligned data holding register (DACC_L12DH) of
GD32F190xx devices......................................................................................................................... 228
11.4.11. DAC concurrent mode 8-bit right-aligned data holding register (DACC_R8DH) of
GD32F190xx devices......................................................................................................................... 229
11.4.12. DAC0 data output register (DAC0_DO) .......................................................................... 230
11.4.13. DAC1 data output register (DAC1_DO) of GD32F190xx devices .................................. 230
11.4.14. Status register (DAC_STAT) ........................................................................................... 230

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12. Comparator (CMP) ............................................................................................233
12.1. Overview ............................................................................................................... 233
12.2. Characteristics ..................................................................................................... 233
12.3. Function overview................................................................................................ 233
12.3.1. CMP clock and reset........................................................................................................... 235
12.3.2. CMP I/O configure .............................................................................................................. 235
12.3.3. CMP operating mode.......................................................................................................... 235
12.3.4. CMP hysteresis................................................................................................................... 235
12.3.5. CMP register write protection ............................................................................................. 236
12.4. Register definition................................................................................................ 237
12.4.1. Control/status register (CMP_CS) ...................................................................................... 237
13. Watchdog timer (WDGT) ..................................................................................244
13.1. Free watchdog timer (FWDGT)............................................................................ 244
13.1.1. Overview ............................................................................................................................. 244
13.1.2. Characteristics .................................................................................................................... 244
13.1.3. Function overview ............................................................................................................... 244
13.1.4. Register definition ............................................................................................................... 247
13.2. Window watchdog timer (WWDGT)..................................................................... 251
13.2.1. Overview ............................................................................................................................. 251
13.2.2. Characteristics .................................................................................................................... 251
13.2.3. Function overview ............................................................................................................... 251
13.2.4. Register definition ............................................................................................................... 254
14. Real-time clock(RTC)........................................................................................256
14.1. Overview ............................................................................................................... 256
14.2. Characteristics ..................................................................................................... 256
14.3. Function overview................................................................................................ 257
14.3.1. Block diagram ..................................................................................................................... 257
14.3.2. Clock source and prescalers .............................................................................................. 257
14.3.3. Shadow registers introduction ............................................................................................ 258
14.3.4. Configurable and field maskable alarm .............................................................................. 258
14.3.5. RTC initialization and configuration .................................................................................... 259
14.3.6. Calendar reading ................................................................................................................ 260
14.3.7. Resetting the RTC .............................................................................................................. 261
14.3.8. RTC shift function ............................................................................................................... 261
14.3.9. RTC reference clock detection ........................................................................................... 262
14.3.10. RTC smooth digital calibration ........................................................................................ 263
14.3.11. Time-stamp function........................................................................................................ 265
14.3.12. Tamper detection ............................................................................................................ 265
14.3.13. Calibration clock output................................................................................................... 266
14.3.14. Alarm output.................................................................................................................... 266

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14.3.15. RTC power saving mode management .......................................................................... 267
14.3.16. RTC interrupts................................................................................................................. 267
14.4. Register definition................................................................................................ 268
14.4.1. Time register (RTC_TIME).................................................................................................. 268
14.4.2. Date register (RTC_DATE) ................................................................................................. 268
14.4.3. Control register (RTC_CTL)................................................................................................ 269
14.4.4. Status register (RTC_STAT) ............................................................................................... 271
14.4.5. Prescaler register (RTC_PSC) ........................................................................................... 273
14.4.6. Alarm 0 time and date register (RTC_ALRM0TD).............................................................. 274
14.4.7. Write protection key register (RTC_WPK) .......................................................................... 275
14.4.8. Sub second register (RTC_SS) .......................................................................................... 275
14.4.9. Shift function control register (RTC_SHIFTCTL) ................................................................ 276
14.4.10. Time of time stamp register (RTC_TTS)......................................................................... 276
14.4.11. Date of time stamp register (RTC_DTS)......................................................................... 277
14.4.12. Sub second of time stamp register (RTC_SSTS) ........................................................... 278
14.4.13. High resolution frequency compensation register (RTC_HRFC).................................... 278
14.4.14. Tamper register (RTC_TAMP) ........................................................................................ 279
14.4.15. Alarm 0 sub second register (RTC_ALRM0SS) ............................................................. 281
14.4.16. Backup registers (RTC_BKPx) (x=0..4) .......................................................................... 282
15. Timer (TIMERx) .................................................................................................284
15.1. Advanced timer (TIMERx,x=0)............................................................................. 285
15.1.1. Overview ............................................................................................................................. 285
15.1.2. Characteristics .................................................................................................................... 285
15.1.3. Block diagram ..................................................................................................................... 286
15.1.4. Function overview ............................................................................................................... 286
15.1.5. TIMERx registers(x=0)........................................................................................................ 313
15.2. General level0 timer (TIMERx, x=1, 2)................................................................. 341
15.2.1. Overview ............................................................................................................................. 341
15.2.2. Characteristics .................................................................................................................... 341
15.2.3. Block diagram ..................................................................................................................... 341
15.2.4. Function overview ............................................................................................................... 342
15.2.5. TIMERx registers(x=1, 2).................................................................................................... 355
15.3. General level2 timer (TIMERx, x=13)................................................................... 381
15.3.1. Overview ............................................................................................................................. 381
15.3.2. Characteristics .................................................................................................................... 381
15.3.3. Block diagram ..................................................................................................................... 381
15.3.4. Function overview ............................................................................................................... 382
15.3.5. TIMERx registers(x=13)...................................................................................................... 390
15.4. General level3 timer (TIMERx, x=14)................................................................... 401
15.4.1. Overview ............................................................................................................................. 401
15.4.2. Characteristics .................................................................................................................... 401
15.4.3. Block diagram ..................................................................................................................... 401

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15.4.4. Function overview ............................................................................................................... 402
15.4.5. TIMERx registers(x=14)...................................................................................................... 418
15.5. General level4 timer (TIMERx, x=15,16).............................................................. 438
15.5.1. Overview ............................................................................................................................. 438
15.5.2. Characteristics .................................................................................................................... 438
15.5.3. Block diagram ..................................................................................................................... 438
15.5.4. Function overview ............................................................................................................... 439
15.5.5. TIMERx registers(x=15,16)................................................................................................. 452
15.6. Basic timer (TIMERx, x=5) ................................................................................... 468
15.6.1. Overview ............................................................................................................................. 468
15.6.2. Characteristics .................................................................................................................... 468
15.6.3. Block diagram ..................................................................................................................... 468
15.6.4. Function overview ............................................................................................................... 468
15.6.5. TIMERx registers(x=5)........................................................................................................ 473
16. Infrared ray port (IFRP) ....................................................................................478
16.1. Overview............................................................................................................... 478
16.2. Characteristics..................................................................................................... 478
16.3. Function overview................................................................................................ 478
17. Universal synchronous asynchronous receiver transmitter (USART).........480
17.1. Overview ............................................................................................................... 480
17.2. Characteristics ..................................................................................................... 480
17.3. Function overview................................................................................................ 481
17.3.1. USART frame format .......................................................................................................... 482
17.3.2. Baud rate generation .......................................................................................................... 483
17.3.3. USART transmitter.............................................................................................................. 484
17.3.4. USART receiver .................................................................................................................. 485
17.3.5. Use DMA for data buffer access ......................................................................................... 486
17.3.6. Hardware flow control ......................................................................................................... 488
17.3.7. Multi-processor communication .......................................................................................... 489
17.3.8. LIN mode ............................................................................................................................ 490
17.3.9. Synchronous mode............................................................................................................. 491
17.3.10. IrDA SIR ENDEC mode .................................................................................................. 492
17.3.11. Half-duplex communication mode .................................................................................. 493
17.3.12. Smartcard (ISO7816) mode............................................................................................ 493
17.3.13. ModBus communication.................................................................................................. 495
17.3.14. Wakeup from deep-sleep mode...................................................................................... 496
17.3.15. USART interrupts ............................................................................................................ 496
17.4. Register definition................................................................................................ 498
17.4.1. Control register 0 (USART_CTL0)...................................................................................... 498
17.4.2. Control register 1 (USART_CTL1)...................................................................................... 500