GigaDevice Semiconductor GD32F1 0 Series User manual

GigaDevice Semiconductor Inc.
GD32F1x0
ARM® Cortex®-M3 32-bit MCU
User Manual
Revision 3.6
(Jul. 2022)

GD32F1x0 User Manual
2
Table of Contents
Table of Contents ...........................................................................................................2
List of Figures ..............................................................................................................17
List of Tables ................................................................................................................24
1. System and memory architecture ........................................................................27
1.1. ARM Cortex-M3 processor........................................................................................ 27
1.2. System architecture .................................................................................................. 28
1.3. Memory map .............................................................................................................. 30
1.3.1. Bit-banding............................................................................................................................ 35
1.3.2. On-chip SRAM memory........................................................................................................ 35
1.3.3. On-chip Flash memory ......................................................................................................... 36
1.4. Boot configuration..................................................................................................... 36
1.5. System configuration registers (SYSCFG) .............................................................. 38
1.5.1. System configuration register 0 (SYSCFG_CFG0) .............................................................. 38
1.5.2. System configuration register 1 (SYSCFG_CFG1) .............................................................. 39
1.5.3. EXTI sources selection register 0 (SYSCFG_EXTISS0)...................................................... 39
1.5.4. EXTI sources selection register 1 (SYSCFG_EXTISS1)...................................................... 41
1.5.5. EXTI sources selection register 2 (SYSCFG_EXTISS2)...................................................... 42
1.5.6. EXTI sources selection register 3 (SYSCFG_EXTISS3)...................................................... 43
1.5.7. System configuration register 2 (SYSCFG_CFG2) .............................................................. 44
1.6. Device electronic signature...................................................................................... 45
1.6.1. Memory density information.................................................................................................. 46
1.6.2. Unique device ID (96 bits) .................................................................................................... 46
2. Flash memory controller (FMC)............................................................................48
2.1. Overview .................................................................................................................... 48
2.2. Characteristics........................................................................................................... 48
2.3. Function overview..................................................................................................... 48
2.3.1. Flash memory architecture ................................................................................................... 48
2.3.2. Read operations ................................................................................................................... 49
2.3.3. Unlock the FMC_CTL register .............................................................................................. 49
2.3.4. Page erase............................................................................................................................ 49
2.3.5. Mass erase ........................................................................................................................... 50
2.3.6. Main flash programming ....................................................................................................... 52
2.3.7. Option bytes erase................................................................................................................ 53
2.3.8. Option bytes programming ................................................................................................... 54
2.3.9. Option bytes description ....................................................................................................... 54

GD32F1x0 User Manual
3
2.3.10. Page erase/Program protection............................................................................................ 55
2.3.11. Security protection ................................................................................................................ 56
2.4. Register definition..................................................................................................... 57
2.4.1. Wait state register (FMC_WS).............................................................................................. 57
2.4.2. Unlock key register (FMC_KEY)........................................................................................... 57
2.4.3. Option bytes unlock key register (FMC_OBKEY) ................................................................. 58
2.4.4. Status register (FMC_STAT)................................................................................................. 58
2.4.5. Control register (FMC_CTL) ................................................................................................. 59
2.4.6. Address register (FMC_ADDR) ............................................................................................ 60
2.4.7. Option bytes status register (FMC_OBSTAT)....................................................................... 61
2.4.8. Write protection register (FMC_WP)..................................................................................... 61
2.4.9. Wait state enable register (FMC_WSEN) ............................................................................. 62
2.4.10. Product ID register (FMC_PID)............................................................................................. 63
3. Power management unit (PMU) ............................................................................64
3.1. Overview .................................................................................................................... 64
3.2. Characteristics........................................................................................................... 64
3.3. Function overview..................................................................................................... 64
3.3.1. Backup domain ..................................................................................................................... 66
3.3.2. VDD / VDDA power domain ...................................................................................................... 67
3.3.3. VDD domain ........................................................................................................................... 67
3.3.4. 1.2V power domain for GD32F130xx and GD32F150xx devices......................................... 69
3.3.5. 1.8V power domain for GD32F170xx and GD32F190xx devices......................................... 69
3.3.6. Power saving modes ............................................................................................................ 70
3.4. Register definition..................................................................................................... 72
3.4.1. Control register (PMU_CTL) ................................................................................................. 72
3.4.2. Power control/status register (PMU_CS).............................................................................. 75
4. Reset and clock unit (RCU)...................................................................................77
4.1. Reset control unit (RCTL) ......................................................................................... 77
4.1.1. Overview ............................................................................................................................... 77
4.1.2. Function overview ................................................................................................................. 77
4.2. Clock control unit (CCTL) ......................................................................................... 78
4.2.1. Overview ............................................................................................................................... 78
4.2.2. Characteristics ...................................................................................................................... 81
4.2.3. Function overview ................................................................................................................. 81
4.3. Register definition..................................................................................................... 86
4.3.1. Control register 0 (RCU_CTL0) ............................................................................................ 86
4.3.2. Configuration register 0 (RCU_CFG0) ................................................................................. 87
4.3.3. Interrupt register (RCU_INT) ................................................................................................ 94
4.3.4. APB2 reset register (RCU_APB2RST) ............................................................................... 100
4.3.5. APB1 reset register (RCU_APB1RST) ............................................................................... 101

GD32F1x0 User Manual
4
4.3.6. AHB enable register (RCU_AHBEN) .................................................................................. 106
4.3.7. APB2 enable register (RCU_APB2EN) .............................................................................. 107
4.3.8. APB1 enable register (RCU_APB1EN) .............................................................................. 109
4.3.9. Backup domain control register (RCU_BDCTL) ..................................................................113
4.3.10. Reset source /clock register (RCU_RSTSCK) ....................................................................116
4.3.11. AHB reset register (RCU_AHBRST)....................................................................................118
4.3.12. Configuration register 1 (RCU_CFG1) ................................................................................119
4.3.13. Configuration register 2 (RCU_CFG2) ............................................................................... 120
4.3.14. Control register 1 (RCU_CTL1) .......................................................................................... 122
4.3.15. Configuration register 3 (RCU_CFG3) of GD32F170xx and GD32F190xx devices .......... 123
4.3.16. APB1 additional enable register (RCU_ADDAPB1EN) ...................................................... 124
4.3.17. APB1 additional reset register (RCU_ADDAPB1RST)....................................................... 124
4.3.18. Voltage key register (RCU_VKEY) ..................................................................................... 125
4.3.19. Deep-sleep mode voltage register (RCU_DSV) ................................................................. 125
4.3.20. Power down voltage select register (RCU_PDVSEL) of GD32F130xx and GD32F150xx
devices 126
5. Interrupt/event controller (EXTI).........................................................................128
5.1. Overview .................................................................................................................. 128
5.2. Characteristics......................................................................................................... 128
5.3. Interrupts function overview................................................................................... 128
5.4. External interrupt and event (EXTI) block diagram ............................................... 132
5.5. External interrupt and Event function overview .................................................... 133
5.6. Register definition ................................................................................................... 136
5.6.1. Interrupt Enable register (EXTI_INTEN) ............................................................................. 136
5.6.2. Event enable register (EXTI_EVEN) .................................................................................. 136
5.6.3. Rising edge trigger enable register (EXTI_RTEN) ............................................................. 137
5.6.4. Falling edge trigger enable register (EXTI_FTEN) ............................................................. 137
5.6.5. Software interrupt event register (EXTI_SWIEV) ............................................................... 138
5.6.6. Pending register (EXTI_PD) ............................................................................................... 139
6. General-purpose I/Os (GPIO) ..............................................................................140
6.1. Overview .................................................................................................................. 140
6.2. Characiteristics........................................................................................................ 140
6.3. Function overview................................................................................................... 140
6.3.1. GPIO pin configuration ....................................................................................................... 141
6.3.2. Alternate functions (AF) ...................................................................................................... 142
6.3.3. Additional functions............................................................................................................. 142
6.3.4. Input configuration .............................................................................................................. 142
6.3.5. Output configuration ........................................................................................................... 143
6.3.6. Analog configuration ........................................................................................................... 144
6.3.7. Alternate function (AF) configuration .................................................................................. 144

GD32F1x0 User Manual
5
6.3.8. GPIO locking function ......................................................................................................... 145
6.3.9. GPIO single cycle toggle function....................................................................................... 145
6.4. Register definition................................................................................................... 146
6.4.1. Port control register (GPIOx_CTL, x=A..D,F) ..................................................................... 146
6.4.2. Port output mode register (GPIOx_OMODE, x=A..D,F) ..................................................... 147
6.4.3. Port output speed register (GPIOx_OSPD, x=A..D,F)........................................................ 149
6.4.4. Port pull-up/down register (GPIOx_PUD, x=A..D,F)........................................................... 151
6.4.5. Port input status register (GPIOx_ISTAT, x=A..D,F) ........................................................... 152
6.4.6. Port output control register (GPIOx_OCTL, x=A..D,F) ....................................................... 153
6.4.7. Port bit operate register (GPIOx_BOP, x=A..D,F)............................................................... 153
6.4.8. Port configuration lock register (GPIOx_LOCK, x=A, B) .................................................... 154
6.4.9. Alternate function selected register0 (GPIOx_AFSEL0, x=A, B, C) ................................... 155
6.4.10. Alternate function selected register1 (GPIOx_AFSEL1, x=A,B,C) ..................................... 156
6.4.11. Bit clear register (GPIOx_BC, x=A..D,F) ............................................................................ 157
6.4.12. Port bit toggle register (GPIOx_TG, x=A..D,F) (Only for GD32F170xx and GD32F190xx
devices) 158
7. Cyclic redundancy checks management unit (CRC) ........................................159
7.1. Overview .................................................................................................................. 159
7.2. Characteristics......................................................................................................... 159
7.3. Function overview................................................................................................... 160
7.4. Register definition................................................................................................... 162
7.4.1. Data Register (CRC_DATA)................................................................................................ 162
7.4.2. Free Data Register (CRC_FDATA)..................................................................................... 162
7.4.3. Control Register (CRC_CTL).............................................................................................. 163
7.4.4. Initialization Data Register (CRC_IDATA)........................................................................... 163
8. Direct memory access controller (DMA)............................................................165
8.1. Overview .................................................................................................................. 165
8.2. Characteristics......................................................................................................... 165
8.3. Block diagram.......................................................................................................... 166
8.4. Function overview................................................................................................... 166
8.4.1. DMA operation .................................................................................................................... 166
8.4.2. Peripheral handshake......................................................................................................... 168
8.4.3. Arbitration............................................................................................................................ 168
8.4.4. Address generation............................................................................................................. 169
8.4.5. Circular mode...................................................................................................................... 169
8.4.6. Memory to memory mode................................................................................................... 169
8.4.7. Channel configuration......................................................................................................... 169
8.4.8. Interrupt............................................................................................................................... 170
8.4.9. DMA request mapping ........................................................................................................ 171

GD32F1x0 User Manual
6
8.5. Register definition................................................................................................... 174
8.5.1. Interrupt flag register (DMA_INTF) ..................................................................................... 174
8.5.2. Interrupt flag clear register (DMA_INTC) ............................................................................ 174
8.5.3. Channel x control register (DMA_CHxCTL) ....................................................................... 175
8.5.4. Channel x counter register (DMA_CHxCNT)...................................................................... 177
8.5.5. Channel x peripheral base address register (DMA_CHxPADDR) ...................................... 178
8.5.6. Channel x memory base address register (DMA_CHxMADDR) ........................................ 178
9. Debug (DBG) ........................................................................................................180
9.1. Overview .................................................................................................................. 180
9.2. Serial Wire Debug port overview............................................................................ 180
9.2.1. Pin assignment ................................................................................................................... 180
9.2.2. JEDEC-106 ID code ........................................................................................................... 180
9.3. Debug hold function overview................................................................................ 181
9.3.1. Debug support for power saving mode............................................................................... 181
9.3.2. Debug support for TIMER, I2C, RTC, WWDGT and FWDGT ............................................ 181
9.4. DBG registers .......................................................................................................... 182
9.4.1. ID code register (DBG_ID).................................................................................................. 182
9.4.2. Control register 0(DBG_CTL0) ........................................................................................... 182
9.4.3. Control register 1 (DBG_CTL1) .......................................................................................... 186
10. Analog to digital converter (ADC) ...................................................................188
10.1. Overview............................................................................................................... 188
10.2. Characteristics..................................................................................................... 188
10.3. Pins and internal signals..................................................................................... 189
10.4. Function overview................................................................................................ 191
10.4.1. Foreground calibration function .......................................................................................... 192
10.4.2. Dual clock domain architecture........................................................................................... 193
10.4.3. ADCON enable ................................................................................................................... 193
10.4.4. Routine sequence............................................................................................................... 193
10.4.5. Operation modes ................................................................................................................ 193
10.4.6. Conversion result threshold monitor function ..................................................................... 196
10.4.7. Data storage mode ............................................................................................................. 196
10.4.8. Sample time configuration .................................................................................................. 197
10.4.9. External trigger configuration.............................................................................................. 198
10.4.10. DMA request ................................................................................................................... 198
10.4.11. ADC internal channels .................................................................................................... 198
10.4.12. Battery voltage monitoring .............................................................................................. 199
10.4.13. ADC interrupts ................................................................................................................ 199
10.4.14. Programmable resolution (DRES) .................................................................................. 199
10.4.15. On-chip hardware oversampling ..................................................................................... 200
10.5. Register definition................................................................................................ 203

GD32F1x0 User Manual
7
10.5.1. Status register (ADC_STAT) ............................................................................................... 203
10.5.2. Control register 0 (ADC_CTL0) .......................................................................................... 203
10.5.3. Control register 1 (ADC_CTL1) .......................................................................................... 206
10.5.4. Sampling time register 0 (ADC_SAMPT0) ......................................................................... 208
10.5.5. Sampling time register 1 (ADC_SAMPT1) ......................................................................... 210
10.5.6. Watchdog high threshold register (ADC_WDHT) ................................................................211
10.5.7. Watchdog low threshold register (ADC_WDLT) ..................................................................211
10.5.8. Routine sequence register 0 (ADC_RSQ0)........................................................................ 212
10.5.9. Routine sequence register 1 (ADC_RSQ1)........................................................................ 212
10.5.10. Routine sequence register 2 (ADC_RSQ2) .................................................................... 213
10.5.11. Routine data register (ADC_RDATA).............................................................................. 213
10.5.12. Oversampling control register (ADC_OVSAMPCTL)...................................................... 214
11. Digital-to-analog converter (DAC) ...................................................................216
11.1. Overview ............................................................................................................... 216
11.2. Characteristic ....................................................................................................... 216
11.3. Function overview................................................................................................ 217
11.3.1. DAC enable......................................................................................................................... 217
11.3.2. DAC output buffer ............................................................................................................... 217
11.3.3. DAC data configuration....................................................................................................... 218
11.3.4. DAC trigger ......................................................................................................................... 218
11.3.5. DAC workflow ..................................................................................................................... 219
11.3.6. DAC output calculate .......................................................................................................... 219
11.3.7. DMA function....................................................................................................................... 219
11.3.8. DAC concurrent conversion for GD32F190xx devices ....................................................... 219
11.4. Register definition................................................................................................ 221
11.4.1. Control register (DAC_CTL) ............................................................................................... 221
11.4.2. Software trigger register (DAC_SWT) ................................................................................ 224
11.4.3. DAC0 12-bit right-aligned data holding register (DAC0_R12DH)....................................... 225
11.4.4. DAC0 12-bit left-aligned data holding register (DAC0_L12DH) ......................................... 225
11.4.5. DAC0 8-bit right-aligned data holding register (DAC0_R8DH)........................................... 226
11.4.6. DAC1 12-bit right-aligned data holding register (DAC1_R12DH) of GD32F190xx devices 226
11.4.7. DAC1 12-bit left-aligned data holding register (DAC1_L12DH) of GD32F190xx devices.. 227
11.4.8. DAC1 8-bit right-aligned data holding register (DAC1_R8DH) of GD32F190xx devices ... 227
11.4.9. DAC concurrent mode 12-bit right-aligned data holding register (DACC_R12DH) of
GD32F190xx devices......................................................................................................................... 228
11.4.10. DAC concurrent mode 12-bit left-aligned data holding register (DACC_L12DH) of
GD32F190xx devices......................................................................................................................... 228
11.4.11. DAC concurrent mode 8-bit right-aligned data holding register (DACC_R8DH) of
GD32F190xx devices......................................................................................................................... 229
11.4.12. DAC0 data output register (DAC0_DO) .......................................................................... 230
11.4.13. DAC1 data output register (DAC1_DO) of GD32F190xx devices .................................. 230
11.4.14. Status register (DAC_STAT) ........................................................................................... 230

GD32F1x0 User Manual
8
12. Comparator (CMP) ............................................................................................233
12.1. Overview ............................................................................................................... 233
12.2. Characteristics ..................................................................................................... 233
12.3. Function overview................................................................................................ 233
12.3.1. CMP clock and reset........................................................................................................... 235
12.3.2. CMP I/O configure .............................................................................................................. 235
12.3.3. CMP operating mode.......................................................................................................... 235
12.3.4. CMP hysteresis................................................................................................................... 235
12.3.5. CMP register write protection ............................................................................................. 236
12.4. Register definition................................................................................................ 237
12.4.1. Control/status register (CMP_CS) ...................................................................................... 237
13. Watchdog timer (WDGT) ..................................................................................244
13.1. Free watchdog timer (FWDGT)............................................................................ 244
13.1.1. Overview ............................................................................................................................. 244
13.1.2. Characteristics .................................................................................................................... 244
13.1.3. Function overview ............................................................................................................... 244
13.1.4. Register definition ............................................................................................................... 247
13.2. Window watchdog timer (WWDGT)..................................................................... 251
13.2.1. Overview ............................................................................................................................. 251
13.2.2. Characteristics .................................................................................................................... 251
13.2.3. Function overview ............................................................................................................... 251
13.2.4. Register definition ............................................................................................................... 254
14. Real-time clock(RTC)........................................................................................256
14.1. Overview ............................................................................................................... 256
14.2. Characteristics ..................................................................................................... 256
14.3. Function overview................................................................................................ 257
14.3.1. Block diagram ..................................................................................................................... 257
14.3.2. Clock source and prescalers .............................................................................................. 257
14.3.3. Shadow registers introduction ............................................................................................ 258
14.3.4. Configurable and field maskable alarm .............................................................................. 258
14.3.5. RTC initialization and configuration .................................................................................... 259
14.3.6. Calendar reading ................................................................................................................ 260
14.3.7. Resetting the RTC .............................................................................................................. 261
14.3.8. RTC shift function ............................................................................................................... 261
14.3.9. RTC reference clock detection ........................................................................................... 262
14.3.10. RTC smooth digital calibration ........................................................................................ 263
14.3.11. Time-stamp function........................................................................................................ 265
14.3.12. Tamper detection ............................................................................................................ 265
14.3.13. Calibration clock output................................................................................................... 266
14.3.14. Alarm output.................................................................................................................... 266

GD32F1x0 User Manual
9
14.3.15. RTC power saving mode management .......................................................................... 267
14.3.16. RTC interrupts................................................................................................................. 267
14.4. Register definition................................................................................................ 268
14.4.1. Time register (RTC_TIME).................................................................................................. 268
14.4.2. Date register (RTC_DATE) ................................................................................................. 268
14.4.3. Control register (RTC_CTL)................................................................................................ 269
14.4.4. Status register (RTC_STAT) ............................................................................................... 271
14.4.5. Prescaler register (RTC_PSC) ........................................................................................... 273
14.4.6. Alarm 0 time and date register (RTC_ALRM0TD).............................................................. 274
14.4.7. Write protection key register (RTC_WPK) .......................................................................... 275
14.4.8. Sub second register (RTC_SS) .......................................................................................... 275
14.4.9. Shift function control register (RTC_SHIFTCTL) ................................................................ 276
14.4.10. Time of time stamp register (RTC_TTS)......................................................................... 276
14.4.11. Date of time stamp register (RTC_DTS)......................................................................... 277
14.4.12. Sub second of time stamp register (RTC_SSTS) ........................................................... 278
14.4.13. High resolution frequency compensation register (RTC_HRFC).................................... 278
14.4.14. Tamper register (RTC_TAMP) ........................................................................................ 279
14.4.15. Alarm 0 sub second register (RTC_ALRM0SS) ............................................................. 281
14.4.16. Backup registers (RTC_BKPx) (x=0..4) .......................................................................... 282
15. Timer (TIMERx) .................................................................................................284
15.1. Advanced timer (TIMERx,x=0)............................................................................. 285
15.1.1. Overview ............................................................................................................................. 285
15.1.2. Characteristics .................................................................................................................... 285
15.1.3. Block diagram ..................................................................................................................... 286
15.1.4. Function overview ............................................................................................................... 286
15.1.5. TIMERx registers(x=0)........................................................................................................ 313
15.2. General level0 timer (TIMERx, x=1, 2)................................................................. 341
15.2.1. Overview ............................................................................................................................. 341
15.2.2. Characteristics .................................................................................................................... 341
15.2.3. Block diagram ..................................................................................................................... 341
15.2.4. Function overview ............................................................................................................... 342
15.2.5. TIMERx registers(x=1, 2).................................................................................................... 355
15.3. General level2 timer (TIMERx, x=13)................................................................... 381
15.3.1. Overview ............................................................................................................................. 381
15.3.2. Characteristics .................................................................................................................... 381
15.3.3. Block diagram ..................................................................................................................... 381
15.3.4. Function overview ............................................................................................................... 382
15.3.5. TIMERx registers(x=13)...................................................................................................... 390
15.4. General level3 timer (TIMERx, x=14)................................................................... 401
15.4.1. Overview ............................................................................................................................. 401
15.4.2. Characteristics .................................................................................................................... 401
15.4.3. Block diagram ..................................................................................................................... 401

GD32F1x0 User Manual
10
15.4.4. Function overview ............................................................................................................... 402
15.4.5. TIMERx registers(x=14)...................................................................................................... 418
15.5. General level4 timer (TIMERx, x=15,16).............................................................. 438
15.5.1. Overview ............................................................................................................................. 438
15.5.2. Characteristics .................................................................................................................... 438
15.5.3. Block diagram ..................................................................................................................... 438
15.5.4. Function overview ............................................................................................................... 439
15.5.5. TIMERx registers(x=15,16)................................................................................................. 452
15.6. Basic timer (TIMERx, x=5) ................................................................................... 468
15.6.1. Overview ............................................................................................................................. 468
15.6.2. Characteristics .................................................................................................................... 468
15.6.3. Block diagram ..................................................................................................................... 468
15.6.4. Function overview ............................................................................................................... 468
15.6.5. TIMERx registers(x=5)........................................................................................................ 473
16. Infrared ray port (IFRP) ....................................................................................478
16.1. Overview............................................................................................................... 478
16.2. Characteristics..................................................................................................... 478
16.3. Function overview................................................................................................ 478
17. Universal synchronous asynchronous receiver transmitter (USART).........480
17.1. Overview ............................................................................................................... 480
17.2. Characteristics ..................................................................................................... 480
17.3. Function overview................................................................................................ 481
17.3.1. USART frame format .......................................................................................................... 482
17.3.2. Baud rate generation .......................................................................................................... 483
17.3.3. USART transmitter.............................................................................................................. 484
17.3.4. USART receiver .................................................................................................................. 485
17.3.5. Use DMA for data buffer access ......................................................................................... 486
17.3.6. Hardware flow control ......................................................................................................... 488
17.3.7. Multi-processor communication .......................................................................................... 489
17.3.8. LIN mode ............................................................................................................................ 490
17.3.9. Synchronous mode............................................................................................................. 491
17.3.10. IrDA SIR ENDEC mode .................................................................................................. 492
17.3.11. Half-duplex communication mode .................................................................................. 493
17.3.12. Smartcard (ISO7816) mode............................................................................................ 493
17.3.13. ModBus communication.................................................................................................. 495
17.3.14. Wakeup from deep-sleep mode...................................................................................... 496
17.3.15. USART interrupts ............................................................................................................ 496
17.4. Register definition................................................................................................ 498
17.4.1. Control register 0 (USART_CTL0)...................................................................................... 498
17.4.2. Control register 1 (USART_CTL1)...................................................................................... 500

GD32F1x0 User Manual
11
17.4.3. Control register 2 (USART_CTL2)...................................................................................... 503
17.4.4. Baud rate generator register (USART_BAUD) ................................................................... 506
17.4.5. Prescaler and guard time configuration register (USART_GP) .......................................... 506
17.4.6. Receiver timeout register (USART_RT) ............................................................................. 507
17.4.7. Command register (USART_CMD) .................................................................................... 508
17.4.8. Status register (USART_STAT) .......................................................................................... 509
17.4.9. Interrupt status clear register (USART_INTC).................................................................... 512
17.4.10. Receive data register (USART_RDATA)......................................................................... 514
17.4.11. Transmit data register (USART_TDATA) ........................................................................ 514
18. Inter-integrated circuit interface (I2C).............................................................516
18.1. Overview............................................................................................................... 516
18.2. Characteristics..................................................................................................... 516
18.3. Function overview................................................................................................ 516
18.3.1. SDA and SCL lines............................................................................................................ 517
18.3.2. Data validation .................................................................................................................. 518
18.3.3. START and STOP signal................................................................................................... 518
18.3.4. Clock synchronization ..................................................................................................... 518
18.3.5. Arbitration.......................................................................................................................... 519
18.3.6. I2C communication flow .................................................................................................. 519
18.3.7. Programming model ......................................................................................................... 520
18.3.8. SCL line stretching ........................................................................................................... 529
18.3.9. Use DMA for data transfer................................................................................................ 530
18.3.10. Packet error checking .................................................................................................. 530
18.3.11. SMBus support ............................................................................................................. 530
18.3.12. SAM_V support (only for GD32F170/F190 series) ..................................................... 532
18.3.13. Status, errors and interrupts ....................................................................................... 532
18.4. Register definition................................................................................................ 534
18.4.1. Control register 0 (I2C_CTL0).......................................................................................... 534
18.4.2. Control register 1 (I2C_CTL1).......................................................................................... 536
18.4.3. Slave address register 0 (I2C_SADDR0) ........................................................................ 537
18.4.4. Slave address register 1 (I2C_SADDR1) ........................................................................ 537
18.4.5. Transfer buffer register (I2C_DATA)................................................................................ 538
18.4.6. Transfer status register 0 (I2C_STAT0)........................................................................... 538
18.4.7. Transfer status register 1 (I2C_STAT1)........................................................................... 541
18.4.8. Clock configure register (I2C_CKCFG) .......................................................................... 542
18.4.9. Rise time register (I2C_RT).............................................................................................. 543
18.4.10. SAM control and status register (I2C_SAMCS) of GD32F170xx and GD32F190xx
series 543
19. Serial peripheral interface/Inter-IC sound (SPI/I2S) .......................................545
19.1. Overview............................................................................................................... 545
19.2. Characteristics..................................................................................................... 545

GD32F1x0 User Manual
12
19.2.1. SPI characteristics .............................................................................................................. 545
19.2.2. I2S characteristics .............................................................................................................. 545
19.3. SPI function overview.......................................................................................... 546
19.3.1. SPI block diagram............................................................................................................... 546
19.3.2. SPI signal description ......................................................................................................... 546
19.3.3. SPI clock timing and data format ........................................................................................ 547
19.3.4. NSS function ....................................................................................................................... 548
19.3.5. SPI operation modes .......................................................................................................... 550
19.3.6. DMA function....................................................................................................................... 556
19.3.7. CRC function....................................................................................................................... 556
19.3.8. SPI interrupts ...................................................................................................................... 556
19.4. I2S function overview .......................................................................................... 558
19.4.1. I2S block diagram ............................................................................................................. 558
19.4.2. I2S signal description....................................................................................................... 558
19.4.3. I2S audio standards.......................................................................................................... 558
19.4.4. I2S clock ............................................................................................................................ 567
19.4.5. Operation ........................................................................................................................... 567
19.4.6. DMA function..................................................................................................................... 572
19.4.7. I2S interrupts..................................................................................................................... 572
19.5. Register definition................................................................................................ 574
19.5.1. Control register 0 (SPI_CTL0) ............................................................................................ 574
19.5.2. Control register 1 (SPI_CTL1) ............................................................................................ 576
19.5.3. Status register (SPI_STAT)................................................................................................. 577
19.5.4. Data register (SPI_DATA) ................................................................................................... 578
19.5.5. CRC polynomial register (SPI_CRCPOLY) ........................................................................ 579
19.5.6. RX CRC register (SPI_RCRC) ........................................................................................... 579
19.5.7. TX CRC register (SPI_TCRC) ............................................................................................ 580
19.5.8. I2S control register (SPI_I2SCTL) ...................................................................................... 580
19.5.9. I2S clock prescaler register (SPI_I2SPSC) ........................................................................ 582
19.5.10. Quad-SPI mode control register (SPI_QCTL) of GD32F170xx and GD32F190xx devices
583
20. HDMI-CEC controller(HDMI-CEC) ....................................................................584
20.1. Overview............................................................................................................... 584
20.2. Characteristics..................................................................................................... 584
20.3. Function overview................................................................................................ 584
20.3.1. CEC bus pin........................................................................................................................ 584
20.3.2. Message description........................................................................................................... 585
20.3.3. Bit timing description........................................................................................................... 586
20.3.4. Arbitration............................................................................................................................ 587
20.3.5. SFT option bit description ................................................................................................... 588
20.3.6. Error definition..................................................................................................................... 588

GD32F1x0 User Manual
13
20.3.7. HDMI-CEC interrupt............................................................................................................ 592
20.4. Register definition................................................................................................ 593
20.4.1. Control register (CEC_CTL) ............................................................................................... 593
20.4.2. Configuration register (CEC_CFG)..................................................................................... 594
20.4.3. Transmit data register (CEC_TDATA)................................................................................. 595
20.4.4. Receive data register (CEC_RDATA) ................................................................................. 596
20.4.5. Interrupt Flag Register (CEC_INTF) ................................................................................... 596
20.4.6. Interrupt enable register (CEC_INTEN).............................................................................. 598
21. Touch sensing interface(TSI)...........................................................................601
21.1. Overview............................................................................................................... 601
21.2. Characteristics..................................................................................................... 601
21.3. Function overview................................................................................................ 601
21.3.1. TSI block diagram ............................................................................................................... 601
21.3.2. Touch sensing technique overview ..................................................................................... 602
21.3.3. Charge transfer sequence .................................................................................................. 602
21.3.4. Charge transfer sequence FSM.......................................................................................... 604
21.3.5. Clock and duration time of states ....................................................................................... 606
21.3.6. PIN mode control of TSI ..................................................................................................... 606
21.3.7. ASW and hysteresis mode ................................................................................................. 607
21.3.8. TSI operation flow ............................................................................................................... 607
21.3.9. TSI flags and interrupts....................................................................................................... 608
21.3.10. TSI GPIOs....................................................................................................................... 608
21.4. Register definition................................................................................................ 609
21.4.1. Control register (TSI_CTL) ................................................................................................. 609
21.4.2. Interrupt enable register (TSI_INTEN).................................................................................611
21.4.3. Interrupt flag clear register (TSI_INTC) ...............................................................................611
21.4.4. Interrupt flag register (TSI_INTF)........................................................................................ 612
21.4.5. Pin hysteresis mode register (TSI_PHM) ........................................................................... 613
21.4.6. Analog switch register (TSI_ASW) ..................................................................................... 613
21.4.7. Sample configuration register (TSI_SAMPCFG) ................................................................ 614
21.4.8. Channel configuration register (TSI_CHCFG).................................................................... 614
21.4.9. Group control register (TSI_GCTL) .................................................................................... 615
21.4.10. Group x cycle number registers (TSI_GxCYCN) (x= 0..5).............................................. 615
22. Universal Serial Bus full-speed device interface (USBD)..............................617
22.1. Overview............................................................................................................... 617
22.2. Main features........................................................................................................ 617
22.3. Block diagram ...................................................................................................... 617
22.4. Signal description................................................................................................ 618
22.5. Clock configuration.............................................................................................. 618

GD32F1x0 User Manual
14
22.6. Function overview................................................................................................ 618
22.6.1. USB endpoints .................................................................................................................... 618
22.6.2. Operation procedure ........................................................................................................... 621
22.6.3. USB events and interrupts.................................................................................................. 624
22.6.4. Operation guide .................................................................................................................. 625
22.7. Register definition................................................................................................ 628
22.7.1. USBD control register (USBD_CTL)................................................................................... 628
22.7.2. USBD interrupt flag register (USBD_INTF) ........................................................................ 629
22.7.3. USBD status register (USBD_STAT) .................................................................................. 630
22.7.4. USBD device address register (USBD_DADDR) ............................................................... 631
22.7.5. USBD buffer address register (USBD_BADDR)................................................................. 632
22.7.6. USBD endpoint x control and status register (USBD_EPxCS), x=[0..7] ............................ 632
22.7.7. USBD endpoint x transmission buffer address register (USBD_EPxTBADDR), x=[0..7]... 634
22.7.8. USBD endpoint x transmission buffer byte count register (USBD_EPxTBCNT), x=[0..7].. 635
22.7.9. USBD endpoint x reception buffer address register (USBD_EPxRBADDR), x=[0..7] ..... 635
22.7.10. USBD endpoint x reception buffer byte count register (USBD_EPxRBCNT), x=[0..7] 636
23. Segment LCD controller (SLCD)......................................................................637
23.1. Overview............................................................................................................... 637
23.2. Characteristics..................................................................................................... 637
23.3. Function overview................................................................................................ 637
23.3.1. SLCD Architecture .............................................................................................................. 637
23.3.2. Clock generator................................................................................................................... 638
23.3.3. Blink control ........................................................................................................................ 639
23.3.4. SEG/COM Driver ................................................................................................................ 639
23.3.5. Double buffer memory ........................................................................................................ 642
23.3.6. ANALOG matrix .................................................................................................................. 642
23.4. Register definition................................................................................................ 644
23.4.1. Control register (SLCD_CTL) ............................................................................................. 644
23.4.2. Configuration register (SLCD_CFG)................................................................................... 645
23.4.3. Status flag register (SLCD_STAT) ...................................................................................... 647
23.4.4. Status flag clear register (SLCD_STATC)........................................................................... 648
23.4.5. Display data registers (SLCD_DATAx, x=0~7) ................................................................... 649
24. Operational amplifiers (OPA) ...........................................................................650
24.1. Overview ............................................................................................................... 650
24.2. Characteristics ..................................................................................................... 650
24.3. Function overview................................................................................................ 650
24.3.1. Signal routing ...................................................................................................................... 650
24.3.2. Calibration........................................................................................................................... 651
24.4. Register definition................................................................................................ 654
24.4.1. Control register (OPA_CTL)................................................................................................ 654

GD32F1x0 User Manual
15
24.4.2. Bias trimming register for normal mode (OPA_BT) ............................................................ 656
24.4.3. Bias trimming register for low power mode (OPA_LPBT)................................................... 657
25. Programmable Current and Voltage Reference (IVREF)................................659
25.1. Overview ............................................................................................................... 659
25.2. Characteristics ..................................................................................................... 659
25.3. Function overview................................................................................................ 659
25.3.1. Signal routing ...................................................................................................................... 659
25.3.2. User Trimming..................................................................................................................... 660
25.4. Register definition................................................................................................ 661
25.4.1. Control register (IVREF_CTL) ............................................................................................ 661
26. Controller area network (CAN) ........................................................................663
26.1. Overview ............................................................................................................... 663
26.2. Characteristics ..................................................................................................... 663
26.3. Function overview................................................................................................ 664
26.3.1. Working mode..................................................................................................................... 664
26.3.2. Communication modes ....................................................................................................... 665
26.3.3. Data transmission ............................................................................................................... 666
26.3.4. Data reception..................................................................................................................... 668
26.3.5. Filtering function.................................................................................................................. 669
26.3.6. Time-triggered communication ........................................................................................... 672
26.3.7. Communication parameters................................................................................................ 673
26.3.8. Error flags ........................................................................................................................... 674
26.3.9. CAN interrupts .................................................................................................................... 675
26.3.10. CAN PHY mode .............................................................................................................. 676
26.4. Register definition................................................................................................ 678
26.4.1. Control register (CAN_CTL) ............................................................................................... 678
26.4.2. Status register (CAN_STAT) ............................................................................................... 679
26.4.3. Transmit status register (CAN_TSTAT) .............................................................................. 681
26.4.4. Receive message FIFO0 register (CAN_RFIFO0) ............................................................. 684
26.4.5. Receive message FIFO1 register (CAN_RFIFO1) ............................................................. 684
26.4.6. Interrupt enable register (CAN_INTEN).............................................................................. 685
26.4.7. Error register (CAN_ERR) .................................................................................................. 687
26.4.8. Bit timing register (CAN_BT) .............................................................................................. 688
26.4.9. Transmit mailbox identifier register (CAN_TMIx) (x=0..2) .................................................. 689
26.4.10. Transmit mailbox property register (CAN_TMPx) (x=0..2) ............................................. 689
26.4.11. Transmit mailbox data0 register (CAN_TMDATA0x) (x=0..2) ......................................... 690
26.4.12. Transmit mailbox data1 register (CAN_TMDATA1x) (x=0..2) ......................................... 691
26.4.13. Receive FIFO mailbox identifier register (CAN_RFIFOMIx) (x=0,1) .............................. 691
26.4.14. Receive FIFO mailbox property register (CAN_RFIFOMPx) (x=0,1) ............................. 692
26.4.15. Receive FIFO mailbox data0 register (CAN_RFIFOMDATA0x) (x=0,1) ......................... 692

GD32F1x0 User Manual
16
26.4.16. Receive FIFO mailbox data1 register (CAN_RFIFOMDATA1x) (x=0,1) ......................... 693
26.4.17. Filter control register (CAN_FCTL) (Just for CAN0) ....................................................... 693
26.4.18. Filter mode configuration register (CAN_FMCFG) (Just for CAN0) ............................... 694
26.4.19. Filter scale configuration register (CAN_FSCFG) (Just for CAN0)................................. 694
26.4.20. Filter associated FIFO register (CAN_FAFIFO) (Just for CAN0) .................................... 695
26.4.21. Filter working register (CAN_FW) (Just for CAN0) ......................................................... 695
26.4.22. Filter x data y register (CAN_FxDATAy) (x=0..27, y=0,1) (Just for CAN0) ..................... 696
26.4.23. PHY control register (CAN_PHYCTL)............................................................................. 696
27. Appendix ...........................................................................................................698
27.1. List of abbreviations used in register................................................................. 698
27.2. List of terms.......................................................................................................... 698
27.3. Available peripherals........................................................................................... 699
28. Revision history................................................................................................700

GD32F1x0 User Manual
17
List of Figures
Figure 1-1. The structure of the Cortex®-M3 processor.......................................................... 28
Figure 1-2. Series system architecture of GD32F130xx and GD32F150xx devices............. 29
Figure 1-3. Series system architecture of GD32F170xx and GD32F190xx devices............. 30
Figure 2-1. Process of page erase operation........................................................................... 50
Figure 2-2. Process of the mass erase operation ................................................................... 51
Figure 2-3. Process of the word programming operation ...................................................... 53
Figure 3-1. Power supply overview of GD32F130xx and GD32F150xx devices................... 65
Figure 3-2. Power supply overview of GD32F170xx and GD32F190xx devices................... 66
Figure 3-3. Waveform of the POR/PDR ..................................................................................... 68
Figure 3-4. Waveform of LVD threshold.................................................................................... 69
Figure 4-1. The system reset circuit ......................................................................................... 78
Figure 4-2. Clock tree of GD32F130xx and GD32F150xx devices ......................................... 79
Figure 4-3. Clock tree of GD32F170xx and GD32F190xx devices ......................................... 80
Figure 4-4. HXTAL clock source ................................................................................................ 81
Figure 5-1. Block diagram of EXTI. ......................................................................................... 132
Figure 6-1. Basic structure of a general-pupose I/O............................................................. 141
Figure 6-2. Basic structure of Input configuration................................................................ 143
Figure 6-3. Basic structure of Output configuration............................................................. 143
Figure 6-4. Basic structure of Analog configuration ............................................................ 144
Figure 6-5. Basic structure of Alternate function configuration.......................................... 145
Figure 7-1. Block Diagram of CRC management unit ........................................................... 160
Figure 8-1. Block diagram of DMA.......................................................................................... 166
Figure 8-2. Handshake mechanism......................................................................................... 168
Figure 8-3. DMA interrupt logic ............................................................................................... 170
Figure 8-4. DMA request mapping .......................................................................................... 172
Figure 10-1. ADC module block diagram of GD32F130xx and GD32F150xx devices ....... 191
Figure 10-2. ADC module block diagram of GD32F170xx and GD32F190xx devices ....... 192
Figure 10-3. Single operation mode........................................................................................ 193
Figure 10-4. Continuous operation mode .............................................................................. 194
Figure 10-5. Scan operation mode, continuous disable....................................................... 195
Figure 10-6. Scan operation mode, continuous enable........................................................ 195
Figure 10-7. Discontinuous operation mode ......................................................................... 196
Figure 10-8. Data storage mode of 12-bit resolution ............................................................ 197
Figure 10-9. Data storage mode of 10-bit resolution ............................................................ 197
Figure 10-10. Data storage mode of 8-bit resolution ............................................................ 197
Figure 10-11. Data storage mode of 6-bit resolution ............................................................ 197
Figure 10-12. 20-bit to 16-bit result truncation ...................................................................... 200
Figure 10-13. Numerical example with 5-bits shift and rounding........................................ 201
Figure 11-1. DAC block diagram.............................................................................................. 217
Figure 12-1. CMP block diagram of GD32F150xx devices.................................................... 234

GD32F1x0 User Manual
18
Figure 12-2. CMP block diagram of GD32F190xx devices.................................................... 234
Figure 12-3. CMP hysteresis .................................................................................................... 236
Figure 13-1. Free watchdog timer block diagram.................................................................. 245
Figure 13-2. Window watchdog timer block diagram ........................................................... 252
Figure 13-3. Window watchdog timer timing diagram .......................................................... 253
Figure 14-1. Block diagram of RTC ......................................................................................... 257
Figure 15-1. Advanced timer block diagram.......................................................................... 286
Figure 15-2. Timing chart of internal clock divided by 1...................................................... 287
Figure 15-3. Timing chart of PSC value change from 0 to 2 ................................................ 288
Figure 15-4. Timing chart of up counting mode, PSC=0/2 ................................................... 289
Figure 15-5. Timing chart of up counting mode, change TIMERx_CAR on the go............ 289
Figure 15-6. Timing chart of down counting mode, PSC=0/2 .............................................. 290
Figure 15-7. Timing chart of down counting mode, change TIMERx_CAR on the go....... 291
Figure 15-8. Center-aligned counter timechart...................................................................... 292
Figure 15-9. Repetition counter timing chart of center-aligned counting mode................ 293
Figure 15-10. Repetition counter timing chart of up counting mode.................................. 293
Figure 15-11. Repetition counter timing chart of down counting mode ............................. 294
Figure 15-12. Channel input capture principle ...................................................................... 295
Figure 15-13. Channel output compare principle (with complementary output, x=0, 1, 2)296
Figure 15-14. Channel output compare principle (CH3_O) .................................................. 296
Figure 15-15. Output-compare under three modes............................................................... 298
Figure 15-16. EAPWM timechart.............................................................................................. 299
Figure 15-17. CAPWM timechart ............................................................................................. 299
Figure 15-18. Channel output complementary PWM with dead-time insertion.................. 302
Figure 15-19. Output behavior in response to a break(The break high active) ................. 303
Figure 15-20. Example of counter operation in encoder interface mode ........................... 304
Figure 15-21. Example of encoder interface mode with CI0FE0 polarity inverted ............ 304
Figure 15-22. Hall sensor is used to BLDC motor................................................................. 305
Figure 15-23. Hall sensor timing between two timers........................................................... 306
Figure 15-24. Restart mode...................................................................................................... 307
Figure 15-25. Pause mode........................................................................................................ 307
Figure 15-26. Event mode ........................................................................................................ 308
Figure 15-27. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60 ................. 309
Figure 15-28. TIMER0 Master/Slave mode timer example .................................................... 309
Figure 15-29. Triggering TIMER0 with Enable of TIMER2......................................................311
Figure 15-30. Triggering TIMER0 and TIMER2 with TIMER2’s CI0 input............................. 312
Figure 15-31. General Level 0 timer block diagram .............................................................. 342
Figure 15-32. Timing chart of internal clock divided by 1.................................................... 343
Figure 15-33. Timing chart of PSC value change from 0 to 2 .............................................. 344
Figure 15-34. Timing chart of up counting mode, PSC=0/2 ................................................. 345
Figure 15-35. Timing chart of up counting mode, change TIMERx_CAR on the go.......... 345
Figure 15-36. Timing chart of down counting mode, PSC=0/2 ............................................ 346
Figure 15-37. Timing chart of down counting mode, change TIMERx_CAR on the go..... 347
Figure 15-38. Center-aligned counter timechart.................................................................... 348

GD32F1x0 User Manual
19
Figure 15-39. Channel input capture principle ...................................................................... 349
Figure 15-40. Channel output compare principle (x=0,1,2,3) ............................................... 350
Figure 15-41. Output-compare under three modes............................................................... 351
Figure 15-42. Timing chart of EAPWM.................................................................................... 352
Figure 15-43. Timing chart of CAPWM.................................................................................... 352
Figure 15-44. General level2 timer block diagram................................................................. 382
Figure 15-45. Timing chart of internal clock divided by 1.................................................... 383
Figure 15-46. Timing chart of PSC value change from 0 to 2 .............................................. 383
Figure 15-47. Timing chart of up counting mode, PSC=0/2 ................................................. 384
Figure 15-48. Timing chart of up counting mode, change TIMERx_CAR on the go.......... 385
Figure 15-49. Channel input capture principle ...................................................................... 386
Figure 15-50. Channel output compare principle.................................................................. 387
Figure 15-51. Output-compare under three modes............................................................... 388
Figure 15-52. PWM mode timechart........................................................................................ 389
Figure 15-53. General level3 timer block diagram................................................................. 402
Figure 15-54. Timing chart of internal clock divided by 1.................................................... 403
Figure 15-55. Timing chart of PSC value change from 0 to 2 .............................................. 404
Figure 15-56. Timing chart of up counting mode, PSC=0/2 ................................................. 405
Figure 15-57. Timing chart of up counting mode, change TIMERx_CAR on the go.......... 405
Figure 15-58. Repetition counter timing chart of up counting mode.................................. 406
Figure 15-59. Channel input capture principle ...................................................................... 407
Figure 15-60. Channel output compare principle (with complementary output, x=0)....... 408
Figure 15-61. Channel output compare principle (CH1_O).................................................. 408
Figure 15-62. Output-compare under three modes............................................................... 410
Figure 15-63. PWM mode timechart.........................................................................................411
Figure 15-64. Complementary output with dead-time insertion. ......................................... 413
Figure 15-65. Output behavior in response to a break(The break high active) ................. 414
Figure 15-66. Restart mode...................................................................................................... 415
Figure 15-67. Pause mode........................................................................................................ 415
Figure 15-68. Event mode ........................................................................................................ 416
Figure 15-69. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99 ........................... 417
Figure 15-70. General level4 timer block diagram................................................................. 439
Figure 15-71. Timing chart of internal clock divided by 1.................................................... 440
Figure 15-72. Timing chart of PSC value change from 0 to 2 .............................................. 440
Figure 15-73. Timing chart of up counting mode, PSC=0/2 ................................................. 441
Figure 15-74. Timing chart of up counting mode, change TIMERx_CAR on the go.......... 442
Figure 15-75. Repetition counter timing chart of up counting mode.................................. 443
Figure 15-76. Channel input capture principle ...................................................................... 444
Figure 15-77. Output-compare under three modes............................................................... 446
Figure 15-78. PWM mode timechart........................................................................................ 447
Figure 15-79. Channel output complementary PWM with dead-time insertion.................. 449
Figure 15-80. Output behavior in response to a break(The break high active) ................. 450
Figure 15-81. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60 ................. 451
Figure 15-82. Basic timer block diagram................................................................................ 468

GD32F1x0 User Manual
20
Figure 15-83. Timing chart of internal clock divided by 1.................................................... 469
Figure 15-84. Timing chart of PSC value change from 0 to 2 .............................................. 470
Figure 15-85. Timing chart of up counting mode, PSC=0/2 ................................................. 471
Figure 15-86. Timing chart of up counting mode, change TIMERx_CAR on the go.......... 471
Figure 16-1. IFRP output timechart 1 ...................................................................................... 478
Figure 16-2. IFRP output timechart 2 ...................................................................................... 479
Figure 16-3. IFRP output timechart 3 ...................................................................................... 479
Figure 17-1. USART module block diagram........................................................................... 482
Figure 17-2. USART character frame (8 bits data and 1 stop bit)........................................ 483
Figure 17-3. USART transmit procedure ................................................................................ 485
Figure 17-4. Oversampling method of a receive frame bit (OSB=0).................................... 486
Figure 17-5. Configuration step when using DMA for USART transmission ..................... 487
Figure 17-6. Configuration step when using DMA for USART reception............................ 488
Figure 17-7. Hardware flow control between two USARTs................................................... 488
Figure 17-8. Hardware flow control......................................................................................... 489
Figure 17-9. Break frame occurs during idle state................................................................ 490
Figure 17-10. Break frame occurs during a frame................................................................. 491
Figure 17-11. Example of USART in synchronous mode ..................................................... 491
Figure 17-12. 8-bit format USART synchronous waveform (CLEN=1) ................................ 492
Figure 17-13. IrDA SIR ENDEC module................................................................................... 492
Figure 17-14. IrDA data modulation ........................................................................................ 493
Figure 17-15. ISO7816-3 frame format .................................................................................... 494
Figure 17-16. USART interrupt mapping diagram ................................................................. 497
Figure 18-1. I2C module block diagram.................................................................................. 517
Figure 18-2. Data validation ..................................................................................................... 518
Figure 18-3. START and STOP signal ..................................................................................... 518
Figure 18-4. Clock synchronization ........................................................................................ 519
Figure 18-5. SDA line arbitration ............................................................................................. 519
Figure 18-6. I2C communication flow with 7-bit address ..................................................... 520
Figure 18-7. I2C communication flow with 10-bit address (Master Transmit).................... 520
Figure 18-8. I2C communication flow with 10-bit address (Master Receive) ..................... 520
Figure 18-9. Programming model for slave transmitting (10-bit address mode)............... 522
Figure 18-10. Programming model for slave receiving (10-bit address mode).................. 523
Figure 18-11. Programming model for master transmitting (10-bit address mode).......... 525
Figure 18-12. Programming model for master receiving using Solution A (10-bit address
mode) .................................................................................................................................. 527
Figure 18-13. Programming model for master receiving mode using solution B (10-bit
address mode) ................................................................................................................... 528
Figure 19-1. Block diagram of SPI for GD32F130xx and GD32F150xx devices................. 546
Figure 19-2. Block diagram of SPI for GD32F170xx and GD32F190xx devices................. 546
Figure 19-3. SPI timing diagram in normal mode.................................................................. 548
Figure 19-4. SPI timing diagram in Quad-SPI mode (CKPL=1, CKPH=1, LF=0) for
GD32F170xx and GD32F190xx devices........................................................................... 548
Figure 19-5. A typical full-duplex connection........................................................................ 551