GigaDevice Semiconductor GD32F403 Series User manual

GigaDevice Semiconductor Inc.
GD32F403xx
Arm® Cortex®-M4 32-bit MCU
User Manual
Revision 2.6
( Jul. 2022 )

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Table of Contents
Table of Contents................................................................................................................. 2
List of Figures ....................................................................................................................16
List of Table ........................................................................................................................ 23
1. System and memory architecture ............................................................................ 26
1.1. Arm®Cortex®-M4 processor...........................................................................................26
1.2. System architecture .....................................................................................................27
1.3. Memory map...............................................................................................................29
1.3.1. Bit-banding...............................................................................................................................................33
1.3.2. On-chip SRAM memory ........................................................................................................................34
1.3.3. On-chip flash memory overview..........................................................................................................34
1.4. Boot configuration.......................................................................................................34
1.5. Device electronic signature ...........................................................................................36
1.5.1. Memory density information.................................................................................................................36
1.5.2. Unique device ID (96 bits)....................................................................................................................36
1.6. System configuration registers ......................................................................................37
2. Flash memory controller (FMC) ................................................................................39
2.1. Introduction................................................................................................................39
2.2. Main features..............................................................................................................39
2.3. Function description.....................................................................................................39
2.3.1. Flash memory architecture...................................................................................................................39
2.3.2. Read operations......................................................................................................................................40
2.3.3. Unlock the FMC_CTLx registers.........................................................................................................40
2.3.4. Page erase...............................................................................................................................................41
2.3.5. Mass erase...............................................................................................................................................42
2.3.6. Main flash programming........................................................................................................................44
2.3.7. Option bytes Erase.................................................................................................................................45
2.3.8. Option bytes modify................................................................................................................................46
2.3.9. Option bytes description........................................................................................................................46
2.3.10. Page erase/program protection...........................................................................................................47
2.3.11. Security protection..................................................................................................................................48
2.4. FMC registers ..............................................................................................................49
2.4.1. Wait state register (FMC_WS).............................................................................................................49
2.4.2. Unlock key register 0(FMC_KEY0).....................................................................................................49
2.4.3. Option byte unlock key register (FMC_OBKEY) .............................................................................50
2.4.4. Status register 0 (FMC_STAT0)..........................................................................................................50

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2.4.5. Control register 0(FMC_CTL0)............................................................................................................51
2.4.6. Address register 0 (FMC_ADDR0).....................................................................................................52
2.4.7. Option byte status register (FMC_OBSTAT)....................................................................................53
2.4.8. Erase/Program Protection register (FMC_WP)...............................................................................53
2.4.9. Unlock key register 1(FMC_KEY1).....................................................................................................54
2.4.10. Status register 1 (FMC_STAT1)..........................................................................................................54
2.4.11. Control register 1(FMC_CTL1)............................................................................................................55
2.4.12. Address register 1 (FMC_ADDR1).....................................................................................................56
2.4.13. Wait state enable register (FMC_WSEN) .........................................................................................56
2.4.14. Product ID register (FMC_PID)...........................................................................................................57
3. Power management unit (PMU) ................................................................................ 58
3.1. Overview....................................................................................................................58
3.2. Characteristics.............................................................................................................58
3.3. Function overview .......................................................................................................58
3.3.1. Backup domain........................................................................................................................................59
3.3.2. VDD / VDDA power domain......................................................................................................................60
3.3.3. 1.2V power domain................................................................................................................................62
3.3.4. Power saving modes..............................................................................................................................62
3.4. PMU registers..............................................................................................................66
3.4.1. Control register (PMU_CTL) ................................................................................................................66
3.4.2. Control and status register (PMU_CS)..............................................................................................68
4. Backup registers (BKP).............................................................................................. 70
4.1. Introduction................................................................................................................70
4.2. Main features..............................................................................................................70
4.3. Function description.....................................................................................................70
4.3.1. RTC clock calibration.............................................................................................................................70
4.3.2. Tamper detection....................................................................................................................................70
4.4. BKP registers...............................................................................................................72
4.4.1. Backup data register x (BKP_DATAx) (x= 0..41).............................................................................72
4.4.2. RTC signal output control register (BKP_OCTL).............................................................................72
4.4.3. Tamper pin control register (BKP_TPCTL).......................................................................................73
4.4.4. Tamper control and status register (BKP_TPCS)............................................................................73
5. Reset and clock unit (RCU) ....................................................................................... 75
5.1. Reset controlunit (RCTL)...............................................................................................75
5.1.1. Overview...................................................................................................................................................75
5.1.2. Function overview...................................................................................................................................75
5.2. Clock control unit (CCTL)........................................................................................76
5.2.1. Overview...................................................................................................................................................76
5.2.2. Characteristics.........................................................................................................................................78

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5.2.3. Function overview...................................................................................................................................78
5.3. Register definition....................................................................................................83
5.3.1. Control register (RCU_CTL).................................................................................................................83
5.3.2. Clock configuration register 0 (RCU_CFG0)....................................................................................85
5.3.3. Clock interrupt register (RCU_INT)....................................................................................................88
5.3.4. APB2 reset register (RCU_APB2RST)..............................................................................................92
5.3.5. APB1 reset register (RCU_APB1RST)..............................................................................................94
5.3.6. AHB enable register (RCU_AHBEN).................................................................................................97
5.3.7. APB2 enable register (RCU_APB2EN).............................................................................................98
5.3.8. APB1 enable register (RCU_APB1EN)...........................................................................................100
5.3.9. Backup domain control register (RCU_BDCTL)............................................................................103
5.3.10. Reset source/clock register (RCU_RSTSCK)................................................................................105
5.3.11. AHB reset register (RCU_AHBRST)................................................................................................106
5.3.12. Clock configuration register 1 (RCU_CFG1)..................................................................................107
5.3.13. Deep-sleep mode voltage register (RCU_DSV)............................................................................110
5.3.14. Additional clock control register (RCU_ADDCTL).........................................................................110
5.3.15. Additional clock interrupt register (RCU_ADDINT).......................................................................111
5.3.16. APB1 additional reset register (RCU_ADDAPB1RST)................................................................112
5.3.17. APB1 additional enable register (RCU_ADDAPB1EN) ...............................................................112
6. Clock trim controller (CTC)...................................................................................... 114
6.1. Overview..................................................................................................................114
6.2. Characteristics...........................................................................................................114
6.3. Function overview .....................................................................................................114
6.3.1. REF sync pulse generator..................................................................................................................115
6.3.2. CTC trim counter...................................................................................................................................115
6.3.3. Frequency evaluation and automatically trim process.................................................................116
6.3.4. Software program guide......................................................................................................................117
6.4. Registerdefinition......................................................................................................119
6.4.1. Control register 0 (CTC_CTL0).........................................................................................................119
6.4.2. Control register 1 (CTC_CTL1).........................................................................................................120
6.4.3. Status register (CTC_STAT)...............................................................................................................121
6.4.4. Interrupt clear register (CTC_INTC).................................................................................................123
7. Interrupt/event controller (EXTI) .............................................................................125
7.1. Overview.................................................................................................................125
7.2. Characteristics .......................................................................................................125
7.3. Interrupts function overview..................................................................................125
7.4. External interrupt and event (EXTI) block diagram...............................................129
7.5. External Interrupt and Event function overview....................................................129
7.6. EXTI Register..........................................................................................................131

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7.6.1. Interrupt enable register (EXTI_INTEN)..........................................................................................131
7.6.2. Event enable register (EXTI_EVEN)................................................................................................131
7.6.3. Rising edge trigger enable register (EXTI_RTEN)........................................................................132
7.6.4. Falling edge trigger enable register (EXTI_FTEN)........................................................................132
7.6.5. Software interrupt event register (EXTI_SWIEV)..........................................................................132
7.6.6. Pending register (EXTI_PD)...............................................................................................................133
8. General-purpose and alternate-function I/Os (GPIO and AFIO).........................134
8.1. Overview ..................................................................................................................134
8.2. Characteristics...........................................................................................................134
8.3. Function overview......................................................................................................134
8.3.1. GPIO pin configuration........................................................................................................................135
8.3.2. External interrupt/event lines..............................................................................................................136
8.3.3. Alternate functions (AF).......................................................................................................................136
8.3.4. Input configuration................................................................................................................................136
8.3.5. Output configuration.............................................................................................................................137
8.3.6. Analog configuration............................................................................................................................138
8.3.7. Alternate function (AF) configuration................................................................................................138
8.3.8. GPIO locking function..........................................................................................................................139
8.3.9. GPIO I/O compensation cell...............................................................................................................139
8.4. Remapping function I/O and debug configuration..........................................................139
8.4.1. Introduction.............................................................................................................................................139
8.4.2. Main features.........................................................................................................................................140
8.4.3. JTAG/SWD alternate function remapping.......................................................................................140
8.4.4. ADC AF remapping..............................................................................................................................141
8.4.5. TIMER AF remapping..........................................................................................................................141
8.4.6. USART AF remapping.........................................................................................................................143
8.4.7. I2C0 AF remapping..............................................................................................................................143
8.4.8. SPI/I2S AF remapping.........................................................................................................................144
8.4.9. CAN AF remapping..............................................................................................................................144
8.4.10. Ethernet AF remapping.......................................................................................................................145
8.4.11. CTC AF remapping...............................................................................................................................145
8.4.12. CLK pins AF remapping......................................................................................................................145
8.5. Register definition......................................................................................................147
8.5.1. Port control register 0 (GPIOx_CTL0, x=A..G)..............................................................................147
8.5.2. Port control register 1 (GPIOx_CTL1, x=A..G)..............................................................................149
8.5.3. Port input status register (GPIOx_ISTAT, x=A..G).........................................................................150
8.5.4. Port output control register (GPIOx_OCTL, x=A..G)....................................................................151
8.5.5. Port bit operate register (GPIOx_BOP, x=A..G).............................................................................151
8.5.6. Port bit clear register (GPIOx_BC, x=A..G)....................................................................................152
8.5.7. Port configuration lock register (GPIOx_LOCK, x=A..G).............................................................152
8.5.8. Port bit speed register (GPIOx_ SPD, x=A..G)..............................................................................153

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8.5.9. Event control register (AFIO_EC).....................................................................................................154
8.5.10. AFIO port configuration register 0 (AFIO_PCF0)..........................................................................154
8.5.11. EXTI sources selection register 0 (AFIO_EXTISS0)....................................................................157
8.5.12. EXTI sources selection register 1 (AFIO_EXTISS1)....................................................................159
8.5.13. EXTI sources selection register 2 (AFIO_EXTISS2)....................................................................160
8.5.14. EXTI sources selection register 3 (AFIO_EXTISS3)....................................................................161
8.5.15. AFIO port configuration register 1 (AFIO_PCF1)..........................................................................162
8.5.16. IO compensation control register (AFIO_CPSCTL)......................................................................164
9. Cyclic redundancy checks management unit (CRC)........................................... 165
9.1. Overview..................................................................................................................165
9.2. Characteristics...........................................................................................................165
9.3. Function overview .....................................................................................................166
9.4. Registerdefinition......................................................................................................167
9.4.1. Data register (CRC_DATA).................................................................................................................167
9.4.2. Free data register (CRC_FDATA).....................................................................................................167
9.4.3. Control register (CRC_CTL)...............................................................................................................168
10. Direct memory access controller (DMA) ............................................................169
10.1. Overview .............................................................................................................169
10.2. Characteristics....................................................................................................169
10.3. Block diagram.....................................................................................................170
10.4. Function overview ..............................................................................................170
10.4.1. DMA operation.......................................................................................................................................170
10.4.2. Peripheral handshake..........................................................................................................................172
10.4.3. Arbitration...............................................................................................................................................172
10.4.4. Address generation..............................................................................................................................172
10.4.5. Circular mode........................................................................................................................................173
10.4.6. Memory to memory mode...................................................................................................................173
10.4.7. Channel configuration..........................................................................................................................173
10.4.8. Interrupt...................................................................................................................................................173
10.4.9. DMA request mapping.........................................................................................................................174
10.5. Register definition ..............................................................................................178
10.5.1. Interrupt flag register (DMA_INTF)...................................................................................................178
10.5.2. Interrupt flag clear register (DMA_INTC) ........................................................................................179
10.5.3. Channel x control register (DMA_CHxCTL)...................................................................................179
10.5.4. Channel x counter register (DMA_CHxCNT).................................................................................181
10.5.5. Channel x peripheral base address register (DMA_CHxPADDR).............................................182
10.5.6. Channel x memory base address register (DMA_CHxMADDR)...............................................182
11. Debug (DBG)........................................................................................................... 184
11.1. Introduction...........................................................................................................184

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11.2. JTAG/SW function description..................................................................................184
11.2.1. Switch JTAG or SW interface.............................................................................................................184
11.2.2. Pin assignment......................................................................................................................................184
11.2.3. JTAG daisy chained structure............................................................................................................185
11.2.4. Debug reset............................................................................................................................................185
11.2.5. JEDEC-106 ID code.............................................................................................................................185
11.3. Debug hold function description...............................................................................185
11.3.1. Debug support for power saving mode............................................................................................185
11.3.2. Debug support for TIMER, I2C, WWDGT, FWDGT and CAN....................................................186
11.4. DBG registers .........................................................................................................187
11.4.1. ID code register (DBG_ID) .................................................................................................................187
11.4.2. Control register 0 (DBG_CTL0).........................................................................................................187
12. Analog-to-digital converter (ADC).......................................................................191
12.1. Overview...............................................................................................................191
12.2. Characteristics........................................................................................................191
12.3. Pins and internal signals..........................................................................................192
12.4. Functionaloverview................................................................................................193
12.4.1. Foreground calibration function.........................................................................................................193
12.4.2. ADC clock...............................................................................................................................................194
12.4.3. ADC enable............................................................................................................................................194
12.4.4. Routine sequence.................................................................................................................................194
12.4.5. Operation modes ..................................................................................................................................194
12.4.6. Conversion result threshold monitor function.................................................................................197
12.4.7. Data storagemode...............................................................................................................................197
12.4.8. Sample time configuration..................................................................................................................198
12.4.9. External trigger configuration.............................................................................................................198
12.4.10. DMA request......................................................................................................................................199
12.4.11. ADC internal channels.....................................................................................................................199
12.4.12. Programmable resolution (DRES)................................................................................................200
12.4.13. On-chip hardware oversampling...................................................................................................200
12.5. ADC sync mode ......................................................................................................202
12.5.1. Free mode..............................................................................................................................................203
12.5.2. Routine parallel mode..........................................................................................................................203
12.5.3. Routine follow-up fast mode...............................................................................................................204
12.5.4. Routine follow-up slow mode.............................................................................................................204
12.6. ADC interrupts .......................................................................................................205
12.7. ADC registers .........................................................................................................206
12.7.1. Status register (ADC_STAT)..............................................................................................................206
12.7.2. Control register 0 (ADC_CTL0).........................................................................................................207
12.7.3. Control register 1 (ADC_CTL1).........................................................................................................208

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12.7.4. Sample time register 0 (ADC_SAMPT0).........................................................................................210
12.7.5. Sample time register 1 (ADC_SAMPT1).........................................................................................211
12.7.6. Watchdog high threshold register (ADC_WDHT)..........................................................................212
12.7.7. Watchdog low threshold register (ADC_WDLT)............................................................................212
12.7.8. Routine sequence register 0 (ADC_RSQ0)....................................................................................213
12.7.9. Routine sequence register 1 (ADC_RSQ1)....................................................................................213
12.7.10. Routine sequence register 2 (ADC_RSQ2) ...............................................................................214
12.7.11. Routine data register (ADC_RDATA)...........................................................................................215
12.7.12. Oversample control register (ADC_OVSAMPCTL)..................................................................215
13. Digital-to-analog converter (DAC) .......................................................................218
13.1. Introduction...........................................................................................................218
13.2. Characteristics........................................................................................................218
13.3. Function description ...............................................................................................219
13.3.1. DAC enable............................................................................................................................................219
13.3.2. DAC output buffer.................................................................................................................................219
13.3.3. DAC data configuration.......................................................................................................................220
13.3.4. DAC trigger.............................................................................................................................................220
13.3.5. DAC workflow........................................................................................................................................220
13.3.6. DAC noise wave....................................................................................................................................220
13.3.7. DAC output calculate...........................................................................................................................221
13.3.8. DMA function..........................................................................................................................................221
13.3.9. DAC concurrent conversion...............................................................................................................222
13.4. DAC registers..........................................................................................................223
13.4.1. Control register (DAC_CTL)...............................................................................................................223
13.4.2. Software trigger register (DAC_SWT)..............................................................................................225
13.4.3. DAC0 12-bit right-aligned data holding register (DAC0_R12DH)..............................................226
13.4.4. DAC0 12-bit left-aligned data holding register (DAC0_L12DH).................................................226
13.4.5. DAC0 8-bit right-aligned data holding register (DAC0_R8DH)..................................................227
13.4.6. DAC1 12-bit right-aligned data holding register (DAC1_R12DH)..............................................227
13.4.7. DAC1 12-bit left-aligned data holding register (DAC1_L12DH).................................................228
13.4.8. DAC1 8-bit right-aligned data holding register (DAC1_R8DH)..................................................228
13.4.9. DAC concurrent mode 12-bit right-aligned data holding register (DACC_R12DH)...............229
13.4.10. DAC concurrent mode 12-bit left-aligned data holding register (DACC_L12DH)..............229
13.4.11. DAC concurrent mode 8-bit right-aligned data holding register (DACC_R8DH)...............230
13.4.12. DAC0 data output register (DAC0_DO)......................................................................................230
13.4.13. DAC1 data output register (DAC1_DO)......................................................................................231
14. Watchdog timer (WDGT) .......................................................................................232
14.1. Free watchdog timer (FWDGT)...........................................................................232
14.1.1. Overview.................................................................................................................................................232
14.1.2. Characteristics.......................................................................................................................................232
14.1.3. Function overview.................................................................................................................................232

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14.1.4. Register definition.................................................................................................................................235
14.2. Window watchdog timer (WWDGT)....................................................................238
14.2.1. Overview.................................................................................................................................................238
14.2.2. Characteristics.......................................................................................................................................238
14.2.3. Function overview.................................................................................................................................238
14.2.4. Register definition.................................................................................................................................241
15. Real-time Clock(RTC) ............................................................................................243
15.1. Overview...............................................................................................................243
15.2. Characteristics........................................................................................................243
15.3. Function overview..................................................................................................243
15.3.1. RTC reset ...............................................................................................................................................244
15.3.2. RTC reading...........................................................................................................................................244
15.3.3. RTC configuration.................................................................................................................................244
15.3.4. RTC flag assertion................................................................................................................................245
15.4. RTC Register...........................................................................................................247
15.4.1. RTC interrupt enable register(RTC_INTEN)...................................................................................247
15.4.2. RTC control register(RTC_CTL)........................................................................................................247
15.4.3. RTC prescaler high register (RTC_PSCH).....................................................................................248
15.4.4. RTC prescaler low register(RTC_PSCL).........................................................................................249
15.4.5. RTC divider high register (RTC_DIVH)............................................................................................249
15.4.6. RTC divider low register (RTC_DIVL)..............................................................................................249
15.4.7. RTC counter high register(RTC_CNTH)..........................................................................................250
15.4.8. RTC counter low register (RTC_CNTL)...........................................................................................250
15.4.9. RTC alarm high register(RTC_ALRMH)..........................................................................................251
15.4.10. RTC alarm low register (RTC_ALRML).......................................................................................251
16. Timers(TIMERx) ......................................................................................................252
16.1. Advanced timer (TIMERx, x=0, 7)..............................................................................253
16.1.1. Overview.................................................................................................................................................253
16.1.2. Characteristics.......................................................................................................................................253
16.1.3. Block diagram........................................................................................................................................254
16.1.4. Function overview.................................................................................................................................255
16.1.5. TIMERx registers(x=0, 7)....................................................................................................................281
16.2. General level0 timer (TIMERx, x= 2, 3).......................................................................307
16.2.1. Overview.................................................................................................................................................307
16.2.2. Characteristics.......................................................................................................................................307
16.2.3. Block diagram........................................................................................................................................307
16.2.4. Function overview.................................................................................................................................309
16.2.5. TIMERx registers(x=2, 3)....................................................................................................................324
16.3. General level1 timer (TIMERx, x=8, 11)......................................................................345
16.3.1. Overview.................................................................................................................................................345

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16.3.2. Characteristics.......................................................................................................................................345
16.3.3. Block diagram........................................................................................................................................346
16.3.4. Function overview.................................................................................................................................347
16.3.5. TIMERx registers(x=8, 11)..................................................................................................................358
16.4. General level2 timer (TIMERx, x=9, 10, 12, 13)............................................................370
16.4.1. Overview.................................................................................................................................................370
16.4.2. Characteristics.......................................................................................................................................370
16.4.3. Block diagram........................................................................................................................................370
16.4.4. Function overview.................................................................................................................................372
16.4.5. TIMERx registers(x=9, 10, 12, 13)....................................................................................................379
16.5. Basic timer (TIMERx, x=5, 6).....................................................................................389
16.5.1. Overview.................................................................................................................................................389
16.5.2. Characteristics.......................................................................................................................................389
16.5.3. Block diagram........................................................................................................................................389
16.5.4. Function overview.................................................................................................................................389
16.5.5. TIMERx registers(x=5, 6)....................................................................................................................393
17. Universal synchronous/asynchronous receiver /transmitter (USART) ......... 398
17.1. Overview...............................................................................................................398
17.2. Characteristics....................................................................................................398
17.3. Function overview..............................................................................................399
17.3.1. USART frame format............................................................................................................................400
17.3.2. Baud rate generation...........................................................................................................................401
17.3.3. USART transmitter................................................................................................................................401
17.3.4. USART receiver....................................................................................................................................402
17.3.5. Use DMA for data buffer access........................................................................................................404
17.3.6. Hardware flow control..........................................................................................................................405
17.3.7. Multi-processor communication.........................................................................................................406
17.3.8. LIN mode................................................................................................................................................407
17.3.9. Synchronous mode..............................................................................................................................408
17.3.10. IrDA SIR ENDEC mode..................................................................................................................409
17.3.11. Half-duplex communication mode................................................................................................410
17.3.12. Smartcard (ISO7816-3) mode.......................................................................................................410
17.3.13. USART interrupts..............................................................................................................................412
17.4. Register definition ..................................................................................................414
17.4.1. Status register 0 (USART_STAT0)...................................................................................................414
17.4.2. Data register (USART_DATA)............................................................................................................416
17.4.3. Baud rate register (USART_BAUD).................................................................................................416
17.4.4. Control register 0 (USART_CTL0)....................................................................................................417
17.4.5. Control register 1 (USART_CTL1)....................................................................................................419
17.4.6. Control register 2 (USART_CTL2)....................................................................................................420
17.4.7. Guard time and prescaler register (USART_GP)..........................................................................422