GigaDevice Semiconductor GD32F403 Series User manual

GigaDevice Semiconductor Inc.
GD32F403xx
Arm® Cortex®-M4 32-bit MCU
User Manual
Revision 2.6
( Jul. 2022 )

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Table of Contents
Table of Contents................................................................................................................. 2
List of Figures ....................................................................................................................16
List of Table ........................................................................................................................ 23
1. System and memory architecture ............................................................................ 26
1.1. Arm®Cortex®-M4 processor...........................................................................................26
1.2. System architecture .....................................................................................................27
1.3. Memory map...............................................................................................................29
1.3.1. Bit-banding...............................................................................................................................................33
1.3.2. On-chip SRAM memory ........................................................................................................................34
1.3.3. On-chip flash memory overview..........................................................................................................34
1.4. Boot configuration.......................................................................................................34
1.5. Device electronic signature ...........................................................................................36
1.5.1. Memory density information.................................................................................................................36
1.5.2. Unique device ID (96 bits)....................................................................................................................36
1.6. System configuration registers ......................................................................................37
2. Flash memory controller (FMC) ................................................................................39
2.1. Introduction................................................................................................................39
2.2. Main features..............................................................................................................39
2.3. Function description.....................................................................................................39
2.3.1. Flash memory architecture...................................................................................................................39
2.3.2. Read operations......................................................................................................................................40
2.3.3. Unlock the FMC_CTLx registers.........................................................................................................40
2.3.4. Page erase...............................................................................................................................................41
2.3.5. Mass erase...............................................................................................................................................42
2.3.6. Main flash programming........................................................................................................................44
2.3.7. Option bytes Erase.................................................................................................................................45
2.3.8. Option bytes modify................................................................................................................................46
2.3.9. Option bytes description........................................................................................................................46
2.3.10. Page erase/program protection...........................................................................................................47
2.3.11. Security protection..................................................................................................................................48
2.4. FMC registers ..............................................................................................................49
2.4.1. Wait state register (FMC_WS).............................................................................................................49
2.4.2. Unlock key register 0(FMC_KEY0).....................................................................................................49
2.4.3. Option byte unlock key register (FMC_OBKEY) .............................................................................50
2.4.4. Status register 0 (FMC_STAT0)..........................................................................................................50

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2.4.5. Control register 0(FMC_CTL0)............................................................................................................51
2.4.6. Address register 0 (FMC_ADDR0).....................................................................................................52
2.4.7. Option byte status register (FMC_OBSTAT)....................................................................................53
2.4.8. Erase/Program Protection register (FMC_WP)...............................................................................53
2.4.9. Unlock key register 1(FMC_KEY1).....................................................................................................54
2.4.10. Status register 1 (FMC_STAT1)..........................................................................................................54
2.4.11. Control register 1(FMC_CTL1)............................................................................................................55
2.4.12. Address register 1 (FMC_ADDR1).....................................................................................................56
2.4.13. Wait state enable register (FMC_WSEN) .........................................................................................56
2.4.14. Product ID register (FMC_PID)...........................................................................................................57
3. Power management unit (PMU) ................................................................................ 58
3.1. Overview....................................................................................................................58
3.2. Characteristics.............................................................................................................58
3.3. Function overview .......................................................................................................58
3.3.1. Backup domain........................................................................................................................................59
3.3.2. VDD / VDDA power domain......................................................................................................................60
3.3.3. 1.2V power domain................................................................................................................................62
3.3.4. Power saving modes..............................................................................................................................62
3.4. PMU registers..............................................................................................................66
3.4.1. Control register (PMU_CTL) ................................................................................................................66
3.4.2. Control and status register (PMU_CS)..............................................................................................68
4. Backup registers (BKP).............................................................................................. 70
4.1. Introduction................................................................................................................70
4.2. Main features..............................................................................................................70
4.3. Function description.....................................................................................................70
4.3.1. RTC clock calibration.............................................................................................................................70
4.3.2. Tamper detection....................................................................................................................................70
4.4. BKP registers...............................................................................................................72
4.4.1. Backup data register x (BKP_DATAx) (x= 0..41).............................................................................72
4.4.2. RTC signal output control register (BKP_OCTL).............................................................................72
4.4.3. Tamper pin control register (BKP_TPCTL).......................................................................................73
4.4.4. Tamper control and status register (BKP_TPCS)............................................................................73
5. Reset and clock unit (RCU) ....................................................................................... 75
5.1. Reset controlunit (RCTL)...............................................................................................75
5.1.1. Overview...................................................................................................................................................75
5.1.2. Function overview...................................................................................................................................75
5.2. Clock control unit (CCTL)........................................................................................76
5.2.1. Overview...................................................................................................................................................76
5.2.2. Characteristics.........................................................................................................................................78

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5.2.3. Function overview...................................................................................................................................78
5.3. Register definition....................................................................................................83
5.3.1. Control register (RCU_CTL).................................................................................................................83
5.3.2. Clock configuration register 0 (RCU_CFG0)....................................................................................85
5.3.3. Clock interrupt register (RCU_INT)....................................................................................................88
5.3.4. APB2 reset register (RCU_APB2RST)..............................................................................................92
5.3.5. APB1 reset register (RCU_APB1RST)..............................................................................................94
5.3.6. AHB enable register (RCU_AHBEN).................................................................................................97
5.3.7. APB2 enable register (RCU_APB2EN).............................................................................................98
5.3.8. APB1 enable register (RCU_APB1EN)...........................................................................................100
5.3.9. Backup domain control register (RCU_BDCTL)............................................................................103
5.3.10. Reset source/clock register (RCU_RSTSCK)................................................................................105
5.3.11. AHB reset register (RCU_AHBRST)................................................................................................106
5.3.12. Clock configuration register 1 (RCU_CFG1)..................................................................................107
5.3.13. Deep-sleep mode voltage register (RCU_DSV)............................................................................110
5.3.14. Additional clock control register (RCU_ADDCTL).........................................................................110
5.3.15. Additional clock interrupt register (RCU_ADDINT).......................................................................111
5.3.16. APB1 additional reset register (RCU_ADDAPB1RST)................................................................112
5.3.17. APB1 additional enable register (RCU_ADDAPB1EN) ...............................................................112
6. Clock trim controller (CTC)...................................................................................... 114
6.1. Overview..................................................................................................................114
6.2. Characteristics...........................................................................................................114
6.3. Function overview .....................................................................................................114
6.3.1. REF sync pulse generator..................................................................................................................115
6.3.2. CTC trim counter...................................................................................................................................115
6.3.3. Frequency evaluation and automatically trim process.................................................................116
6.3.4. Software program guide......................................................................................................................117
6.4. Registerdefinition......................................................................................................119
6.4.1. Control register 0 (CTC_CTL0).........................................................................................................119
6.4.2. Control register 1 (CTC_CTL1).........................................................................................................120
6.4.3. Status register (CTC_STAT)...............................................................................................................121
6.4.4. Interrupt clear register (CTC_INTC).................................................................................................123
7. Interrupt/event controller (EXTI) .............................................................................125
7.1. Overview.................................................................................................................125
7.2. Characteristics .......................................................................................................125
7.3. Interrupts function overview..................................................................................125
7.4. External interrupt and event (EXTI) block diagram...............................................129
7.5. External Interrupt and Event function overview....................................................129
7.6. EXTI Register..........................................................................................................131

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7.6.1. Interrupt enable register (EXTI_INTEN)..........................................................................................131
7.6.2. Event enable register (EXTI_EVEN)................................................................................................131
7.6.3. Rising edge trigger enable register (EXTI_RTEN)........................................................................132
7.6.4. Falling edge trigger enable register (EXTI_FTEN)........................................................................132
7.6.5. Software interrupt event register (EXTI_SWIEV)..........................................................................132
7.6.6. Pending register (EXTI_PD)...............................................................................................................133
8. General-purpose and alternate-function I/Os (GPIO and AFIO).........................134
8.1. Overview ..................................................................................................................134
8.2. Characteristics...........................................................................................................134
8.3. Function overview......................................................................................................134
8.3.1. GPIO pin configuration........................................................................................................................135
8.3.2. External interrupt/event lines..............................................................................................................136
8.3.3. Alternate functions (AF).......................................................................................................................136
8.3.4. Input configuration................................................................................................................................136
8.3.5. Output configuration.............................................................................................................................137
8.3.6. Analog configuration............................................................................................................................138
8.3.7. Alternate function (AF) configuration................................................................................................138
8.3.8. GPIO locking function..........................................................................................................................139
8.3.9. GPIO I/O compensation cell...............................................................................................................139
8.4. Remapping function I/O and debug configuration..........................................................139
8.4.1. Introduction.............................................................................................................................................139
8.4.2. Main features.........................................................................................................................................140
8.4.3. JTAG/SWD alternate function remapping.......................................................................................140
8.4.4. ADC AF remapping..............................................................................................................................141
8.4.5. TIMER AF remapping..........................................................................................................................141
8.4.6. USART AF remapping.........................................................................................................................143
8.4.7. I2C0 AF remapping..............................................................................................................................143
8.4.8. SPI/I2S AF remapping.........................................................................................................................144
8.4.9. CAN AF remapping..............................................................................................................................144
8.4.10. Ethernet AF remapping.......................................................................................................................145
8.4.11. CTC AF remapping...............................................................................................................................145
8.4.12. CLK pins AF remapping......................................................................................................................145
8.5. Register definition......................................................................................................147
8.5.1. Port control register 0 (GPIOx_CTL0, x=A..G)..............................................................................147
8.5.2. Port control register 1 (GPIOx_CTL1, x=A..G)..............................................................................149
8.5.3. Port input status register (GPIOx_ISTAT, x=A..G).........................................................................150
8.5.4. Port output control register (GPIOx_OCTL, x=A..G)....................................................................151
8.5.5. Port bit operate register (GPIOx_BOP, x=A..G).............................................................................151
8.5.6. Port bit clear register (GPIOx_BC, x=A..G)....................................................................................152
8.5.7. Port configuration lock register (GPIOx_LOCK, x=A..G).............................................................152
8.5.8. Port bit speed register (GPIOx_ SPD, x=A..G)..............................................................................153

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8.5.9. Event control register (AFIO_EC).....................................................................................................154
8.5.10. AFIO port configuration register 0 (AFIO_PCF0)..........................................................................154
8.5.11. EXTI sources selection register 0 (AFIO_EXTISS0)....................................................................157
8.5.12. EXTI sources selection register 1 (AFIO_EXTISS1)....................................................................159
8.5.13. EXTI sources selection register 2 (AFIO_EXTISS2)....................................................................160
8.5.14. EXTI sources selection register 3 (AFIO_EXTISS3)....................................................................161
8.5.15. AFIO port configuration register 1 (AFIO_PCF1)..........................................................................162
8.5.16. IO compensation control register (AFIO_CPSCTL)......................................................................164
9. Cyclic redundancy checks management unit (CRC)........................................... 165
9.1. Overview..................................................................................................................165
9.2. Characteristics...........................................................................................................165
9.3. Function overview .....................................................................................................166
9.4. Registerdefinition......................................................................................................167
9.4.1. Data register (CRC_DATA).................................................................................................................167
9.4.2. Free data register (CRC_FDATA).....................................................................................................167
9.4.3. Control register (CRC_CTL)...............................................................................................................168
10. Direct memory access controller (DMA) ............................................................169
10.1. Overview .............................................................................................................169
10.2. Characteristics....................................................................................................169
10.3. Block diagram.....................................................................................................170
10.4. Function overview ..............................................................................................170
10.4.1. DMA operation.......................................................................................................................................170
10.4.2. Peripheral handshake..........................................................................................................................172
10.4.3. Arbitration...............................................................................................................................................172
10.4.4. Address generation..............................................................................................................................172
10.4.5. Circular mode........................................................................................................................................173
10.4.6. Memory to memory mode...................................................................................................................173
10.4.7. Channel configuration..........................................................................................................................173
10.4.8. Interrupt...................................................................................................................................................173
10.4.9. DMA request mapping.........................................................................................................................174
10.5. Register definition ..............................................................................................178
10.5.1. Interrupt flag register (DMA_INTF)...................................................................................................178
10.5.2. Interrupt flag clear register (DMA_INTC) ........................................................................................179
10.5.3. Channel x control register (DMA_CHxCTL)...................................................................................179
10.5.4. Channel x counter register (DMA_CHxCNT).................................................................................181
10.5.5. Channel x peripheral base address register (DMA_CHxPADDR).............................................182
10.5.6. Channel x memory base address register (DMA_CHxMADDR)...............................................182
11. Debug (DBG)........................................................................................................... 184
11.1. Introduction...........................................................................................................184

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11.2. JTAG/SW function description..................................................................................184
11.2.1. Switch JTAG or SW interface.............................................................................................................184
11.2.2. Pin assignment......................................................................................................................................184
11.2.3. JTAG daisy chained structure............................................................................................................185
11.2.4. Debug reset............................................................................................................................................185
11.2.5. JEDEC-106 ID code.............................................................................................................................185
11.3. Debug hold function description...............................................................................185
11.3.1. Debug support for power saving mode............................................................................................185
11.3.2. Debug support for TIMER, I2C, WWDGT, FWDGT and CAN....................................................186
11.4. DBG registers .........................................................................................................187
11.4.1. ID code register (DBG_ID) .................................................................................................................187
11.4.2. Control register 0 (DBG_CTL0).........................................................................................................187
12. Analog-to-digital converter (ADC).......................................................................191
12.1. Overview...............................................................................................................191
12.2. Characteristics........................................................................................................191
12.3. Pins and internal signals..........................................................................................192
12.4. Functionaloverview................................................................................................193
12.4.1. Foreground calibration function.........................................................................................................193
12.4.2. ADC clock...............................................................................................................................................194
12.4.3. ADC enable............................................................................................................................................194
12.4.4. Routine sequence.................................................................................................................................194
12.4.5. Operation modes ..................................................................................................................................194
12.4.6. Conversion result threshold monitor function.................................................................................197
12.4.7. Data storagemode...............................................................................................................................197
12.4.8. Sample time configuration..................................................................................................................198
12.4.9. External trigger configuration.............................................................................................................198
12.4.10. DMA request......................................................................................................................................199
12.4.11. ADC internal channels.....................................................................................................................199
12.4.12. Programmable resolution (DRES)................................................................................................200
12.4.13. On-chip hardware oversampling...................................................................................................200
12.5. ADC sync mode ......................................................................................................202
12.5.1. Free mode..............................................................................................................................................203
12.5.2. Routine parallel mode..........................................................................................................................203
12.5.3. Routine follow-up fast mode...............................................................................................................204
12.5.4. Routine follow-up slow mode.............................................................................................................204
12.6. ADC interrupts .......................................................................................................205
12.7. ADC registers .........................................................................................................206
12.7.1. Status register (ADC_STAT)..............................................................................................................206
12.7.2. Control register 0 (ADC_CTL0).........................................................................................................207
12.7.3. Control register 1 (ADC_CTL1).........................................................................................................208

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12.7.4. Sample time register 0 (ADC_SAMPT0).........................................................................................210
12.7.5. Sample time register 1 (ADC_SAMPT1).........................................................................................211
12.7.6. Watchdog high threshold register (ADC_WDHT)..........................................................................212
12.7.7. Watchdog low threshold register (ADC_WDLT)............................................................................212
12.7.8. Routine sequence register 0 (ADC_RSQ0)....................................................................................213
12.7.9. Routine sequence register 1 (ADC_RSQ1)....................................................................................213
12.7.10. Routine sequence register 2 (ADC_RSQ2) ...............................................................................214
12.7.11. Routine data register (ADC_RDATA)...........................................................................................215
12.7.12. Oversample control register (ADC_OVSAMPCTL)..................................................................215
13. Digital-to-analog converter (DAC) .......................................................................218
13.1. Introduction...........................................................................................................218
13.2. Characteristics........................................................................................................218
13.3. Function description ...............................................................................................219
13.3.1. DAC enable............................................................................................................................................219
13.3.2. DAC output buffer.................................................................................................................................219
13.3.3. DAC data configuration.......................................................................................................................220
13.3.4. DAC trigger.............................................................................................................................................220
13.3.5. DAC workflow........................................................................................................................................220
13.3.6. DAC noise wave....................................................................................................................................220
13.3.7. DAC output calculate...........................................................................................................................221
13.3.8. DMA function..........................................................................................................................................221
13.3.9. DAC concurrent conversion...............................................................................................................222
13.4. DAC registers..........................................................................................................223
13.4.1. Control register (DAC_CTL)...............................................................................................................223
13.4.2. Software trigger register (DAC_SWT)..............................................................................................225
13.4.3. DAC0 12-bit right-aligned data holding register (DAC0_R12DH)..............................................226
13.4.4. DAC0 12-bit left-aligned data holding register (DAC0_L12DH).................................................226
13.4.5. DAC0 8-bit right-aligned data holding register (DAC0_R8DH)..................................................227
13.4.6. DAC1 12-bit right-aligned data holding register (DAC1_R12DH)..............................................227
13.4.7. DAC1 12-bit left-aligned data holding register (DAC1_L12DH).................................................228
13.4.8. DAC1 8-bit right-aligned data holding register (DAC1_R8DH)..................................................228
13.4.9. DAC concurrent mode 12-bit right-aligned data holding register (DACC_R12DH)...............229
13.4.10. DAC concurrent mode 12-bit left-aligned data holding register (DACC_L12DH)..............229
13.4.11. DAC concurrent mode 8-bit right-aligned data holding register (DACC_R8DH)...............230
13.4.12. DAC0 data output register (DAC0_DO)......................................................................................230
13.4.13. DAC1 data output register (DAC1_DO)......................................................................................231
14. Watchdog timer (WDGT) .......................................................................................232
14.1. Free watchdog timer (FWDGT)...........................................................................232
14.1.1. Overview.................................................................................................................................................232
14.1.2. Characteristics.......................................................................................................................................232
14.1.3. Function overview.................................................................................................................................232

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14.1.4. Register definition.................................................................................................................................235
14.2. Window watchdog timer (WWDGT)....................................................................238
14.2.1. Overview.................................................................................................................................................238
14.2.2. Characteristics.......................................................................................................................................238
14.2.3. Function overview.................................................................................................................................238
14.2.4. Register definition.................................................................................................................................241
15. Real-time Clock(RTC) ............................................................................................243
15.1. Overview...............................................................................................................243
15.2. Characteristics........................................................................................................243
15.3. Function overview..................................................................................................243
15.3.1. RTC reset ...............................................................................................................................................244
15.3.2. RTC reading...........................................................................................................................................244
15.3.3. RTC configuration.................................................................................................................................244
15.3.4. RTC flag assertion................................................................................................................................245
15.4. RTC Register...........................................................................................................247
15.4.1. RTC interrupt enable register(RTC_INTEN)...................................................................................247
15.4.2. RTC control register(RTC_CTL)........................................................................................................247
15.4.3. RTC prescaler high register (RTC_PSCH).....................................................................................248
15.4.4. RTC prescaler low register(RTC_PSCL).........................................................................................249
15.4.5. RTC divider high register (RTC_DIVH)............................................................................................249
15.4.6. RTC divider low register (RTC_DIVL)..............................................................................................249
15.4.7. RTC counter high register(RTC_CNTH)..........................................................................................250
15.4.8. RTC counter low register (RTC_CNTL)...........................................................................................250
15.4.9. RTC alarm high register(RTC_ALRMH)..........................................................................................251
15.4.10. RTC alarm low register (RTC_ALRML).......................................................................................251
16. Timers(TIMERx) ......................................................................................................252
16.1. Advanced timer (TIMERx, x=0, 7)..............................................................................253
16.1.1. Overview.................................................................................................................................................253
16.1.2. Characteristics.......................................................................................................................................253
16.1.3. Block diagram........................................................................................................................................254
16.1.4. Function overview.................................................................................................................................255
16.1.5. TIMERx registers(x=0, 7)....................................................................................................................281
16.2. General level0 timer (TIMERx, x= 2, 3).......................................................................307
16.2.1. Overview.................................................................................................................................................307
16.2.2. Characteristics.......................................................................................................................................307
16.2.3. Block diagram........................................................................................................................................307
16.2.4. Function overview.................................................................................................................................309
16.2.5. TIMERx registers(x=2, 3)....................................................................................................................324
16.3. General level1 timer (TIMERx, x=8, 11)......................................................................345
16.3.1. Overview.................................................................................................................................................345

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16.3.2. Characteristics.......................................................................................................................................345
16.3.3. Block diagram........................................................................................................................................346
16.3.4. Function overview.................................................................................................................................347
16.3.5. TIMERx registers(x=8, 11)..................................................................................................................358
16.4. General level2 timer (TIMERx, x=9, 10, 12, 13)............................................................370
16.4.1. Overview.................................................................................................................................................370
16.4.2. Characteristics.......................................................................................................................................370
16.4.3. Block diagram........................................................................................................................................370
16.4.4. Function overview.................................................................................................................................372
16.4.5. TIMERx registers(x=9, 10, 12, 13)....................................................................................................379
16.5. Basic timer (TIMERx, x=5, 6).....................................................................................389
16.5.1. Overview.................................................................................................................................................389
16.5.2. Characteristics.......................................................................................................................................389
16.5.3. Block diagram........................................................................................................................................389
16.5.4. Function overview.................................................................................................................................389
16.5.5. TIMERx registers(x=5, 6)....................................................................................................................393
17. Universal synchronous/asynchronous receiver /transmitter (USART) ......... 398
17.1. Overview...............................................................................................................398
17.2. Characteristics....................................................................................................398
17.3. Function overview..............................................................................................399
17.3.1. USART frame format............................................................................................................................400
17.3.2. Baud rate generation...........................................................................................................................401
17.3.3. USART transmitter................................................................................................................................401
17.3.4. USART receiver....................................................................................................................................402
17.3.5. Use DMA for data buffer access........................................................................................................404
17.3.6. Hardware flow control..........................................................................................................................405
17.3.7. Multi-processor communication.........................................................................................................406
17.3.8. LIN mode................................................................................................................................................407
17.3.9. Synchronous mode..............................................................................................................................408
17.3.10. IrDA SIR ENDEC mode..................................................................................................................409
17.3.11. Half-duplex communication mode................................................................................................410
17.3.12. Smartcard (ISO7816-3) mode.......................................................................................................410
17.3.13. USART interrupts..............................................................................................................................412
17.4. Register definition ..................................................................................................414
17.4.1. Status register 0 (USART_STAT0)...................................................................................................414
17.4.2. Data register (USART_DATA)............................................................................................................416
17.4.3. Baud rate register (USART_BAUD).................................................................................................416
17.4.4. Control register 0 (USART_CTL0)....................................................................................................417
17.4.5. Control register 1 (USART_CTL1)....................................................................................................419
17.4.6. Control register 2 (USART_CTL2)....................................................................................................420
17.4.7. Guard time and prescaler register (USART_GP)..........................................................................422

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17.4.8. Control register 3 (USART_CTL3)....................................................................................................423
17.4.9. Receiver timeout register (USART_RT)..........................................................................................424
17.4.10. Status register 1 (USART_STAT1)...............................................................................................425
18. Inter-integrated circuit interface (I2C).................................................................427
18.1. Overview .............................................................................................................427
18.2. Characteristics....................................................................................................427
18.3. Function overview ..............................................................................................427
18.3.1. SDA and SCL lines...............................................................................................................................428
18.3.2. Data validation.......................................................................................................................................429
18.3.3. START and STOP signal.....................................................................................................................429
18.3.4. Clock synchronization..........................................................................................................................429
18.3.5. Arbitration...............................................................................................................................................430
18.3.6. I2C communication flow......................................................................................................................431
18.3.7. Programming model.............................................................................................................................431
18.3.8. SCL line stretching................................................................................................................................440
18.3.9. Use DMA for data transfer..................................................................................................................441
18.3.10. Packet error checking......................................................................................................................441
18.3.11. SMBus support..................................................................................................................................442
18.3.12. Status, errors and interrupts ..........................................................................................................443
18.4. Register definition ..............................................................................................445
18.4.1. Control register 0 (I2C_CTL0) ...........................................................................................................445
18.4.2. Control register 1 (I2C_CTL1) ...........................................................................................................447
18.4.3. Slave address register 0 (I2C_SADDR0)........................................................................................448
18.4.4. Slave address register 1 (I2C_SADDR1)........................................................................................448
18.4.5. Transfer buffer register (I2C_DATA).................................................................................................449
18.4.6. Transfer status register 0 (I2C_STAT0)...........................................................................................449
18.4.7. Transfer status register 1 (I2C_STAT1)...........................................................................................452
18.4.8. Clock configure register (I2C_CKCFG)...........................................................................................453
18.4.9. Rise time register (I2C_RT)................................................................................................................454
18.4.10. Fast-mode-plus configure register (I2C_FMPCFG).................................................................454
19. Serial peripheral interface/Inter-IC sound (SPI/I2S)..........................................456
19.1. Overview...............................................................................................................456
19.2. Characteristics........................................................................................................456
19.2.1. SPI characteristics................................................................................................................................456
19.2.2. I2S characteristics ................................................................................................................................456
19.3. SPI function overview..............................................................................................457
19.3.1. SPI block diagram.................................................................................................................................457
19.3.2. SPI signal description..........................................................................................................................457
19.3.3. SPI clock timing and data format ......................................................................................................458
19.3.4. NSS function..........................................................................................................................................459

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19.3.5. SPI operation modes ...........................................................................................................................460
19.3.6. DMA function..........................................................................................................................................469
19.3.7. CRC function..........................................................................................................................................469
19.3.8. SPI interrupts.........................................................................................................................................469
19.4. I2S function overview..............................................................................................471
19.4.1. I2S block diagram.................................................................................................................................471
19.4.2. I2S signal description...........................................................................................................................471
19.4.3. I2S audio standards .............................................................................................................................472
19.4.4. I2S clock .................................................................................................................................................480
19.4.5. Operation................................................................................................................................................481
19.4.6. DMA function..........................................................................................................................................485
19.4.7. I2S interrupts..........................................................................................................................................485
19.5. Register definition ..................................................................................................487
19.5.1. Control register 0 (SPI_CTL0)...........................................................................................................487
19.5.2. Control register 1 (SPI_CTL1)...........................................................................................................489
19.5.3. Status register (SPI_STAT) ................................................................................................................490
19.5.4. Data register (SPI_DATA)...................................................................................................................491
19.5.5. CRC polynomial register (SPI_CRCPOLY)....................................................................................492
19.5.6. RX CRC register (SPI_RCRC)..........................................................................................................492
19.5.7. TX CRC register (SPI_TCRC)...........................................................................................................493
19.5.8. I2S control register (SPI_I2SCTL)....................................................................................................494
19.5.9. I2S clock prescaler register (SPI_I2SPSC)....................................................................................495
19.5.10. Quad-SPI mode control register (SPI_QCTL) of SPI0.............................................................496
20. Secure digital input/output interface (SDIO) .....................................................498
20.1. Introduction...........................................................................................................498
20.2. Main features.........................................................................................................498
20.3. SDIO bus topology ..................................................................................................498
20.4. SDIO functional description......................................................................................501
20.4.1. SDIO adapter.........................................................................................................................................501
20.4.2. AHB interface.........................................................................................................................................505
20.5. Card functional description......................................................................................507
20.5.1. Card registers ........................................................................................................................................507
20.5.2. Commands.............................................................................................................................................508
20.5.3. Responses .............................................................................................................................................519
20.5.4. Data packets format.............................................................................................................................523
20.5.5. Two status fields of the card...............................................................................................................524
20.6. Programming sequence...........................................................................................531
20.6.1. Card identification.................................................................................................................................531
20.6.2. No data commands ..............................................................................................................................533
20.6.3. Single block or multiple block write...................................................................................................534

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20.6.4. Single block or multiple block read...................................................................................................535
20.6.5. Stream write and stream read (MMC only).....................................................................................536
20.6.6. Erase.......................................................................................................................................................537
20.6.7. Bus width selection...............................................................................................................................538
20.6.8. Protection management......................................................................................................................539
20.6.9. Card Lock/Unlock operation...............................................................................................................539
20.7. Specific operations..................................................................................................541
20.7.1. SD I/O specific operations..................................................................................................................541
20.7.2. CE-ATA specific operations ................................................................................................................545
20.8. SDIO registers.........................................................................................................547
20.8.1. Power control register (SDIO_PWRCTL)........................................................................................547
20.8.2. Clock control register (SDIO_CLKCTL)...........................................................................................547
20.8.3. Command argument register (SDIO_CMDAGMT).......................................................................549
20.8.4. Command control register (SDIO_CMDCTL).................................................................................549
20.8.5. Command index response register (SDIO_RSPCMDIDX).........................................................551
20.8.6. Response register (SDIO_RESPx x=0..3)......................................................................................551
20.8.7. Data timeout register (SDIO_DATATO)...........................................................................................552
20.8.8. Data length register (SDIO_DATALEN)...........................................................................................552
20.8.9. Data control register (SDIO_DATACTL)..........................................................................................553
20.8.10. Data counter register (SDIO_DATACNT)....................................................................................554
20.8.11. Status register (SDIO_STAT).........................................................................................................555
20.8.12. Interrupt clear register (SDIO_INTC)...........................................................................................556
20.8.13. Interrupt enable register (SDIO_INTEN).....................................................................................557
20.8.14. FIFO counter register (SDIO_FIFOCNT)....................................................................................559
20.8.15. FIFO data register (SDIO_FIFO)..................................................................................................560
21. External memory controller (EXMC) ...................................................................561
21.1. Overview .............................................................................................................561
21.2. Characteristics....................................................................................................561
21.3. Function overview ..............................................................................................561
21.3.1. Block diagram........................................................................................................................................561
21.3.2. Basic regulation of EXMC access.....................................................................................................562
21.3.3. External device address mapping.....................................................................................................563
21.3.4. NOR/PSRAM controller.......................................................................................................................566
21.3.5. NAND Flash or PC Card controller...................................................................................................585
21.4. Registers definition.............................................................................................591
21.4.1. NOR/PSRAM controller registers......................................................................................................591
21.4.2. NAND Flash/PC Card controller registers.......................................................................................595
22. Controller area network (CAN).............................................................................602
22.1. Overview...............................................................................................................602
22.2. Characteristics........................................................................................................602

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22.3. Function overview..................................................................................................603
22.3.1. Working mode........................................................................................................................................603
22.3.2. Communication modes........................................................................................................................604
22.3.3. Data transmission.................................................................................................................................605
22.3.4. Data reception.......................................................................................................................................607
22.3.5. Filtering function....................................................................................................................................608
22.3.6. Time-triggered communication..........................................................................................................612
22.3.7. Communication parameters...............................................................................................................612
22.3.8. Error flags...............................................................................................................................................614
22.3.9. CAN interrupts.......................................................................................................................................614
22.4. CAN registers .........................................................................................................616
22.4.1. Control register (CAN_CTL)...............................................................................................................616
22.4.2. Status register (CAN_STAT)..............................................................................................................617
22.4.3. Transmit status register (CAN_TSTAT)...........................................................................................619
22.4.4. Receive message FIFO0 register (CAN_RFIFO0).......................................................................622
22.4.5. Receive message FIFO1 register (CAN_RFIFO1).......................................................................622
22.4.6. Interrupt enable register (CAN_INTEN)...........................................................................................623
22.4.7. Error register (CAN_ERR)..................................................................................................................625
22.4.8. Bit timing register (CAN_BT)..............................................................................................................626
22.4.9. Transmit mailbox identifier register (CAN_TMIx) (x=0..2)...........................................................627
22.4.10. Transmit mailbox property register (CAN_TMPx) (x=0..2)......................................................627
22.4.11. Transmit mailbox data0 register (CAN_TMDATA0x) (x=0..2)................................................628
22.4.12. Transmit mailbox data1 register (CAN_TMDATA1x) (x=0..2)................................................629
22.4.13. Receive FIFO mailbox identifier register (CAN_RFIFOMIx) (x=0,1)....................................629
22.4.14. Receive FIFO mailbox property register (CAN_RFIFOMPx) (x=0,1)...................................630
22.4.15. Receive FIFO mailbox data0 register (CAN_RFIFOMDATA0x) (x=0,1)..............................630
22.4.16. Receive FIFO mailbox data1 register (CAN_RFIFOMDATA1x) (x=0,1)..............................631
22.4.17. Filter control register (CAN_FCTL) (Just for CAN0).................................................................631
22.4.18. Filter mode configuration register (CAN_FMCFG) (Just for CAN0)......................................632
22.4.19. Filter scale configuration register (CAN_FSCFG) (Just for CAN0).......................................633
22.4.20. Filter associated FIFO register (CAN_FAFIFO) (Just for CAN0)...........................................633
22.4.21. Filter working register (CAN_FW) (Just for CAN0)...................................................................634
22.4.22. Filter x data y register (CAN_FxDATAy) (x=0..27, y=0,1) (Just for CAN0)..........................634
23. Universal serial bus full-speed interface (USBFS) ........................................... 635
23.1. Overview...............................................................................................................635
23.2. Characteristics........................................................................................................635
23.3. Block diagram........................................................................................................636
23.4. Signaldescription ...................................................................................................636
23.5. Function overview..................................................................................................636
23.5.1. USBFS clocks and working modes ..................................................................................................636
23.5.2. USB host function.................................................................................................................................638

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23.5.3. USB device function.............................................................................................................................640
23.5.4. OTG function overview........................................................................................................................641
23.5.5. Data FIFO...............................................................................................................................................642
23.5.6. Operation guide.....................................................................................................................................644
23.6. Interrupts..............................................................................................................649
23.7. Register definition ..................................................................................................651
23.7.1. Global control and status registers...................................................................................................651
23.7.2. Host control and status registers.......................................................................................................672
23.7.3. Device control and status registers ..................................................................................................684
23.7.4. Power and clock control register (USBFS_PWRCLKCTL).........................................................708
24. Revision history .....................................................................................................709

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List of Figures
Figure 1-1. The structure of the Cortex®-M4 processor...............................................................27
Figure 1-2. GD32F403xx series system architecture...................................................................29
Figure 2-1. Process of page erase operation..............................................................................42
Figure 2-2. Process of mass erase operation .............................................................................43
Figure 2-3. Process of word program operation .........................................................................45
Figure 3-1. Power supply overview............................................................................................59
Figure 3-2. Waveform of thePOR / PDR.....................................................................................61
Figure 3-3. Waveform of the LVD threshold................................................................................61
Figure 5-1. The system reset circuit...........................................................................................76
Figure 5-2. Clock tree ...............................................................................................................77
Figure 5-3. HXTAL clock source ................................................................................................78
Figure 5-4. HXTAL clock source in bypass mode........................................................................79
Figure 6-1. CTC overview........................................................................................................115
Figure 6-2. CTC trim counter...................................................................................................116
Figure 7-1. Block diagram of EXTI ...........................................................................................129
Figure 8-1. Basic structure ofa standard I/O port bit.................................................................135
Figure 8-2. Input configuration................................................................................................137
Figure 8-3. Output configuration.............................................................................................137
Figure 8-4. Analog configuration.............................................................................................138
Figure 8-5. Alternate function configuration.............................................................................139
Figure 9-1. Block diagram of CRC calculation unit....................................................................166
Figure 10-1. Block diagram of DMA.........................................................................................170
Figure 10-2. Handshake mechanism........................................................................................172
Figure 10-3. DMA interrupt logic..............................................................................................174
Figure 10-4. DMA0 requestmapping........................................................................................175
Figure 10-5. DMA1 requestmapping........................................................................................176
Figure 12-1. ADCmodule block diagram..................................................................................193
Figure 12-2. Single operationmode.........................................................................................194
Figure 12-3. Continuous operation mode.................................................................................195
Figure 12-4. Scan operation mode, continuous disable.............................................................196
Figure 12-5. Scan operation mode, continuous enable..............................................................196
Figure 12-6. Discontinuous operationmode.............................................................................197
Figure 12-7. 12-bit Data storage mode.....................................................................................198
Figure 12-8. 6-bit Data storage mode.......................................................................................198
Figure 12-9. 20-bit to 16-bit result truncation............................................................................201
Figure 12-10. Numerical example with 5-bits shift and rounding................................................201
Figure 12-11. ADC sync block diagram....................................................................................203
Figure 12-12. Routine parallel mode on 10 channels.................................................................204
Figure 12-13. Routine follow-up fastmode (the CTNbit of ADCs are set)...................................204
Figure 12-14. Routine follow-up slow mode..............................................................................205

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Figure 13-1. DAC block diagram..............................................................................................219
Figure 13-2. DAC LFSR algorithm............................................................................................221
Figure 13-3. DAC triangle noise wave......................................................................................221
Figure 14-1. Free watchdog block diagram...............................................................................233
Figure 14-2. Window watchdog timer block diagram.................................................................238
Figure 14-3. Window watchdog timing diagram........................................................................239
Figure 15-1. Block diagram of RTC..........................................................................................244
Figure 16-1. Advanced timer block diagram.............................................................................254
Figure 16-2. Timing chart of internal clock divided by 1............................................................255
Figure 16-3. Timing chart of PSC value change from 0 to 2.......................................................256
Figure 16-4. Timing chart of up countingmode, PSC=0/2..........................................................257
Figure 16-5. Timing chart of up countingmode, change TIMERx_CAR on the go........................258
Figure 16-6. Timing chart of down counting mode,PSC=0/2......................................................259
Figure 16-7. Timing chart of down counting mode, change TIMERx_CARon the go...................260
Figure 16-8. Timing chart of center-aligned counting................................................................261
Figure 16-9. Repetition timechart for center-aligned counter.....................................................262
Figure 16-10. Repetition timechart for up-counter.....................................................................262
Figure 16-11. Repetition timechart for down-counter ................................................................263
Figure 16-12. Channel input capture principle..........................................................................264
Figure 16-13. Output-compare under three modes....................................................................266
Figure 16-14. EAPWM timechart..............................................................................................267
Figure 16-15. CAPWM timechart..............................................................................................267
Figure 16-16. Complementary output with dead-time insertion..................................................270
Figure 16-17. Output behavior in response to a break(The break high active).............................271
Figure 16-18. Example of counter operation in encoder interface mode .....................................272
Figure 16-19. Example of encoder interface mode with CI0FE0 polarity inverted ........................272
Figure 16-20. Hall sensor is used to BLDC motor .....................................................................274
Figure 16-21. Hall sensor timing between two timers................................................................274
Figure 16-22. Restart mode.....................................................................................................275
Figure 16-23. Pause mode.......................................................................................................276
Figure 16-24. Event mode .......................................................................................................276
Figure 16-25. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60.............................277
Figure 16-26. Timer0 master/slave mode timer example............................................................278
Figure 16-27. Triggering TIMER0 with enable signal of TIMER2 .................................................279
Figure 16-28. Triggering TIMER0 and TIMER2 with TIMER2’s CI0 input ......................................280
Figure 16-29. General Level 0 timer block diagram ...................................................................308
Figure 16-30. Timing chart of internal clock divided by 1 ..........................................................309
Figure 16-31. Timing chart of PSC value change from 0 to 2......................................................310
Figure 16-32. Timing chart of up countingmode, PSC=0/2........................................................311
Figure 16-33. Timing chart of up countingmode, change TIMERx_CAR on the go. .....................312
Figure 16-34. Timing chart of down counting mode, PSC=0/2....................................................313
Figure 16-35. Down-counter timechart, change TIMERx_CAR on the go.....................................313
Figure 16-36. Timing chart of center-aligned counting mode.....................................................315
Figure 16-37. Channel input capture principle..........................................................................316

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Figure 16-38. Output-compare under three modes....................................................................318
Figure 16-39. EAPWM timechart..............................................................................................319
Figure 16-40. CAPWM timechart..............................................................................................319
Figure 16-41. Restart mode.....................................................................................................321
Figure 16-42. Pause mode.......................................................................................................321
Figure 16-43. Event mode .......................................................................................................322
Figure 16-44. Single pulse mode TIMERx_CHxCV= 0x04 TIMERx_CAR=0x60.............................323
Figure 16-45. General level1 timer block diagram.....................................................................346
Figure 16-46. Timing chart of internal clock divided by 1..........................................................347
Figure 16-47. Timing chart of PSC value change from 0 to 2......................................................348
Figure 16-48. Timing chart of up countingmode, PSC=0/2........................................................349
Figure 16-49. Timing chart of up countingmode, change TIMERx_CAR on the go. .....................349
Figure 16-50. Channels input capture principle ........................................................................350
Figure 16-51. Output-compare under three modes....................................................................352
Figure 16-52. EAPWM timechart..............................................................................................353
Figure 16-53. CAPWM timechart..............................................................................................353
Figure 16-54. Restart mode.....................................................................................................355
Figure 16-55. Pause mode.......................................................................................................355
Figure 16-56. Event mode .......................................................................................................356
Figure 16-57. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99 .....................................357
Figure 16-58. General level2 timer blockdiagram.....................................................................371
Figure 16-59. Timing chart of internal clock divided by 1 ..........................................................372
Figure 16-60. Timing chart of PSC value change from 0 to 2......................................................373
Figure 16-61. Timing chart of up countingmode, PSC=0/2........................................................374
Figure 16-62. Timing chart of up countingmode, change TIMERx_CAR on the go......................374
Figure 16-63. Channels input capture principle ........................................................................375
Figure 16-64. Output-compare under three modes....................................................................377
Figure 16-65. Basic timer block diagram..................................................................................389
Figure 16-66. Timing chart of internal clock divided by 1..........................................................390
Figure 16-67. Timing chart of PSC value change from 0 to 2......................................................390
Figure 16-68. Timing chart of up countingmode, PSC=0/2........................................................391
Figure 16-69. Timing chart of up countingmode, change TIMERx_CAR on the go......................392
Figure 16-1. USART module block diagram..............................................................................400
Figure 16-2. USART character frame (8 bits data and 1 stop bit)................................................400
Figure 16-3. USART transmit procedure...................................................................................402
Figure 16-4. Receiving a frame bit by oversampling method .....................................................403
Figure 16-5. Configuration step when using DMA for USART transmission ................................404
Figure 16-6. Configuration steps when using DMA for USART reception....................................405
Figure 16-7. Hardware flow control between two USARTs.........................................................406
Figure 16-8. Hardware flow control..........................................................................................406
Figure 16-9. Break frame occurs during idle state.....................................................................408
Figure 16-10. Break frame occurs during a frame.....................................................................408
Figure 16-11. Example of USART in synchronous mode............................................................408
Figure 16-12. 8-bit format USART synchronous waveform (CLEN=1).........................................409

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Figure 16-13. IrDA SIR ENDEC module.....................................................................................409
Figure 16-14. IrDA data modulation .........................................................................................410
Figure 16-15. ISO7816-3 frame format......................................................................................411
Figure 16-16. USART interrupt mapping diagram......................................................................413
Figure 18-1. I2C module block diagram....................................................................................428
Figure 18-2. Data validation ....................................................................................................429
Figure 18-3. START and STOP condition..................................................................................429
Figure 18-4. Clock synchronization .........................................................................................430
Figure 18-5. SDA line arbitration..............................................................................................430
Figure 18-6. I2C communication flow with 7-bit address ...........................................................431
Figure 18-7. I2C communication flow with 10-bit address (Master Transmit)...............................431
Figure 18-8. I2C communication flow with 10-bit address (Master Receive)................................431
Figure 18-9. Programming model for slave transmitting mode (10-bit address mode).................433
Figure 18-10. Programming model for slave receiving (10-bit address mode).............................434
Figure 18-11. Programming model for master transmitting mode (10-bit address mode).............436
Figure 18-12. Programming model for master receiving using Solution A (10-bit address mode).437
Figure 18-13. Programming model for master receiving mode using solution B (10-bit address
mode) .............................................................................................................................439
Figure 19-1. Block diagram of SPI ...........................................................................................457
Figure 19-2. SPI timing diagram in normalmode......................................................................458
Figure 19-3. SPI timing diagram in Quad-SPI mode (CKPL=1, CKPH=1, LF=0)............................459
Figure 19-4. A typical Full-duplex connection...........................................................................462
Figure 19-5. A typical simplex connection (Master: Receive, Slave: Transmit)............................462
Figure 19-6. A typical simplex connection (Master: Transmit only, Slave: Receive).....................462
Figure 19-7. A typical bidirectional connection.........................................................................462
Figure 19-8. Timing diagram of TImaster mode with discontinuous transfer..............................464
Figure 19-9. Timing diagram of TImaster mode with continuous transfer ..................................465
Figure 19-10. Timing diagram of TI slavemode........................................................................465
Figure 19-11. Timing diagram of NSS pulse with continuous transmit........................................466
Figure 19-12. Timing diagram of quad writeoperation in Quad-SPI mode...................................467
Figure 19-13. Timing diagram of quad read operationin Quad-SPImode...................................468
Figure 19-14. Block diagram of I2S..........................................................................................471
Figure 19-15. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0)..................472
Figure 19-16. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1)..................472
Figure 19-17. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0)..................473
Figure 19-18. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1)..................473
Figure 19-19. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0)..................473
Figure 19-20. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1)..................473
Figure 19-21. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0)..................474
Figure 19-22. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1)..................474
Figure 19-23. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0) ...............474
Figure 19-24. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1)...............474
Figure 19-25. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) ...............474
Figure 19-26. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ...............475

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Figure 19-27. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ...............475
Figure 19-28. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ...............475
Figure 19-29. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) ...............475
Figure 19-30. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) ...............475
Figure 19-31. LSBjustified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0)................476
Figure 19-32. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1)................476
Figure 19-33. LSBjustified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0)................476
Figure 19-34. LSBjustified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1)................476
Figure 19-35. PCM standard short frame synchronizationmode timing diagram (DTLEN=00,
CHLEN=0, CKPL=0).........................................................................................................477
Figure 19-36. PCM standard short frame synchronizationmode timing diagram (DTLEN=00,
CHLEN=0, CKPL=1).........................................................................................................477
Figure 19-37. PCM standard short frame synchronizationmode timing diagram (DTLEN=10,
CHLEN=1, CKPL=0).........................................................................................................477
Figure 19-38. PCM standard short frame synchronizationmode timing diagram (DTLEN=10,
CHLEN=1, CKPL=1).........................................................................................................477
Figure 19-39. PCM standard short frame synchronizationmode timing diagram (DTLEN=01,
CHLEN=1, CKPL=0).........................................................................................................477
Figure19-40. PCM standardshort frame synchronization mode timingdiagram (DTLEN=01,
CHLEN=1, CKPL=1).........................................................................................................478
Figure 19-41. PCM standard short frame synchronizationmode timing diagram (DTLEN=00,
CHLEN=1, CKPL=0).........................................................................................................478
Figure 19-42. PCM standard short frame synchronizationmode timing diagram (DTLEN=00,
CHLEN=1, CKPL=1).........................................................................................................478
Figure 19-43. PCM standard longframe synchronizationmode timing diagram (DTLEN=00,
CHLEN=0, CKPL=0).........................................................................................................478
Figure19-44. PCM standardlong frame synchronization mode timing diagram(DTLEN=00,
CHLEN=0, CKPL=1).........................................................................................................478
Figure 19-45. PCM standard longframe synchronizationmode timing diagram (DTLEN=10,
CHLEN=1, CKPL=0).........................................................................................................478
Figure 19-46. PCM standard longframe synchronizationmode timing diagram (DTLEN=10,
CHLEN=1, CKPL=1).........................................................................................................479
Figure 19-47. PCM standard longframe synchronizationmode timing diagram (DTLEN=01,
CHLEN=1, CKPL=0).........................................................................................................479
Figure 19-48. PCM standard longframe synchronizationmode timing diagram (DTLEN=01,
CHLEN=1, CKPL=1).........................................................................................................479
Figure 19-49. PCM standard longframe synchronizationmode timing diagram (DTLEN=00,
CHLEN=1, CKPL=0).........................................................................................................479
Figure 19-50. PCM standard longframe synchronizationmode timing diagram (DTLEN=00,
CHLEN=1, CKPL=1).........................................................................................................479
Figure 19-51. Block diagram of I2S clock generator..................................................................480
Figure 19-52. I2S initialization sequence..................................................................................482
Figure 19-53. I2S master reception disabling sequence............................................................484
Figure 20-1. SDIO “no response” and “no data” operations ......................................................499