GigaDevice Semiconductor GD32W51 Series User manual

GigaDevice Semiconductor Inc.
GD32W51x
Arm®Cortex®-M3332-bit MCU
User Manual
Revision 1.0
( Nov 2021 )

GD32W51x User Manual
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Table of Contents
Table of Contents.................................................................................................................2
List of Figures ....................................................................................................................24
List of Tables ......................................................................................................................32
1. System and memory architecture ............................................................................37
1.1. Arm Cortex-M33 processor......................................................................................37
1.2. System architecture.................................................................................................38
1.3. TrustZone® overview................................................................................................40
1.3.1. TrustZone® security attribution..................................................................................40
1.3.2. Peripheral classification...........................................................................................42
1.4. Memory map.............................................................................................................43
1.4.1. On-chip SRAM memory ..........................................................................................47
1.4.2. SRAM1 Write protection..........................................................................................47
1.4.3. SRAM1 security protection ......................................................................................48
1.4.4. SRAM1 Erase........................................................................................................48
1.4.5. On-chip flash memory overview................................................................................48
1.5. Boot configuration...................................................................................................48
1.6. System configuration controller (SYSCFG).............................................................51
1.6.1. SYSCFG main features...........................................................................................51
1.6.2. SYSCFG TrustZone security and privilege .................................................................51
1.6.3. SYSCFG registers..................................................................................................52
1.7. Device electronic signature .....................................................................................64
1.7.1. Memory density information.....................................................................................64
1.7.2. Unique device ID (96 bits) .......................................................................................65
2. Flash memory controller (FMC) ................................................................................67
2.1. Overview...................................................................................................................67
2.2. Characteristics.........................................................................................................67
2.3. Systemoverview......................................................................................................67
2.4. Function overview....................................................................................................68
2.4.1. Flash memory architecture ......................................................................................68
2.4.2. Read operations ....................................................................................................69
2.4.3. Unlock the FMC_CTL/FMC_SECCTL register ............................................................70
2.4.4. Page erase ...........................................................................................................71
2.4.5. Mass erase...........................................................................................................72
2.4.6. Main flash programming..........................................................................................74
2.4.7. Option bytes..........................................................................................................75

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2.4.8. TrustZone security protection...................................................................................77
2.4.9. Security protection .................................................................................................78
2.4.10. Write protection......................................................................................................82
2.4.11. Flash privileged and unprivileged mode.....................................................................82
2.4.12. FLASH interrupts ...................................................................................................82
2.5. Register definition....................................................................................................84
2.5.1. Unlock key register (FMC_KEY)...............................................................................84
2.5.2. Option byte unlock key register (FMC_OBKEY) ..........................................................84
2.5.3. Status register (FMC_STAT) ....................................................................................85
2.5.4. Control register (FMC_CTL).....................................................................................85
2.5.5. Address register (FMC_ADDR) ................................................................................87
2.5.6. Option byte status register (FMC_OBSTAT) ...............................................................88
2.5.7. Secure Unlock key register (FMC_SECKEY)..............................................................88
2.5.8. Secure status register (FMC_SECSTAT)....................................................................89
2.5.9. Secure Control register (FMC_SECCTL) ...................................................................90
2.5.10. Secure Address register (FMC_SECADDR) ...............................................................91
2.5.11. Option byte register (FMC_OBR)..............................................................................92
2.5.12. Option byte user register (FMC_OBUSER).................................................................93
2.5.13. Secure mark configuration register 0 (FMC_SECMCFG0)............................................93
2.5.14. Secure dedicated mark protection register 0 (FMC_DMP0)...........................................94
2.5.15. Option byte write protection area register 0 (FMC_OBWRP0) .......................................94
2.5.16. Secure mark configuration register 1 (FMC_SECMCFG1)............................................95
2.5.17. Secure dedicated mark protection register 1 (FMC_DMP1)...........................................96
2.5.18. Option byte write protection area register 1 (FMC_OBWRP1) .......................................96
2.5.19. Secure mark configuration register 2(FMC_SECMCFG2).............................................97
2.5.20. Secure mark configuration register 3 (FMC_SECMCFG3)............................................98
2.5.21. NO-RTDEC region register x (FMC_NODECx, x=0,1,2,3).............................................98
2.5.22. Offset region register (FMC_OFRG)..........................................................................99
2.5.23. Offset value register (FMC_OFVR) ...........................................................................99
2.5.24. Secure dedicated mark protection control register (FMC_DMPCTL).............................100
2.5.25. Privilege configuration register (FMC_PRIVCFG)......................................................101
2.5.26. Product ID register (FMC_PID)...............................................................................101
3. Electronic fuse (EFUSE)...........................................................................................102
3.1. Overview.................................................................................................................102
3.2. Characteristics.......................................................................................................102
3.3. Block diagram........................................................................................................102
3.4. Function overview..................................................................................................103
3.4.1. EFUSE architecture..............................................................................................103
3.4.2. EFUSE macro description .....................................................................................103
3.4.3. Read operation....................................................................................................107
3.4.4. Program operation ...............................................................................................107

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3.5. Register definition..................................................................................................108
3.5.1. Control and status register (EFUSE_CS) .................................................................108
3.5.2. Address register (EFUSE_ADDR)...........................................................................109
3.5.3. Control register (EFUSE_CTL)...............................................................................110
3.5.4. Trustzone control register(EFUSE_TZCTL) .............................................................. 111
3.5.5. Flash protection control register (EFUSE_FP_CTL)...................................................112
3.5.6. User control register (EFUSE_USER_CTL)..............................................................112
3.5.7. MCU initialization data register (EFUSE_MCU_INIT_DATA)........................................113
3.5.8. Firmware AES key register (EFUSE_AES_KEY).......................................................114
3.5.9. RoTPK key register (EFUSE_ROTPK_KEY) ............................................................114
3.5.10. Debug password register (EFUSE_DP)...................................................................114
3.5.11. IAK key or GSSA register (EFUSE_IAK_GSSA)........................................................115
3.5.12. Product UID register (EFUSE_PUID) ......................................................................115
3.5.13. HUK key register (EFUSE_HUK_KEY)....................................................................116
3.5.14. RF data register (EFUSE_RF_DATA)......................................................................116
3.5.15. User data register (EFUSE_USER_DATA)...............................................................116
3.5.16. EFUSE Pre-TrustZone enable register (EFUSE_PRE_TZEN) .....................................117
3.5.17. TrustZone boot address register (EFUSE_TZ_BOOT_ADDR).....................................117
3.5.18. No-TrustZone boot address register (EFUSE_NTZ_BOOT_ADDR)..............................118
4. Instruction cache (ICACHE)..................................................................................... 119
4.1. Introduction............................................................................................................119
4.2. Characteristics.......................................................................................................119
4.3. Function overview..................................................................................................119
4.3.1. ICACHE initialization.............................................................................................120
4.3.2. Paired master cache.............................................................................................120
4.3.3. ICACHE TAG memory ..........................................................................................121
4.3.4. Address remapping ..............................................................................................121
4.3.5. Cacheable and uncacheable access .......................................................................123
4.3.6. ICACHE performance monitoring............................................................................124
4.3.7. ICACHE interrupts................................................................................................124
4.4. Register definition..................................................................................................126
4.4.1. Control register (ICACHE_CTL)..............................................................................126
4.4.2. Status register (ICACHE_STAT) .............................................................................127
4.4.3. Interrupt enable register (ICACHE_INTEN) ..............................................................127
4.4.4. Flag clear register (ICACHE_FC)............................................................................128
4.4.5. Hit monitor counter register (ICACHE_HMC)............................................................128
4.4.6. Miss monitor counter register (ICACHE_MMC).........................................................129
4.4.7. Configuration register (ICACHE_CFGx)...................................................................129
5. Power management unit (PMU) ..............................................................................131
5.1. Overview.................................................................................................................131
5.2. Characteristics.......................................................................................................131

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5.3. Function overview..................................................................................................132
5.3.1. Battery backup domain .........................................................................................132
5.3.2. VDD / VDDA power domain...................................................................................133
5.3.3. 1.2V power domain ..............................................................................................135
5.3.4. Power saving modes ............................................................................................136
5.3.5. Security description..............................................................................................141
5.4. Register definition..................................................................................................143
5.4.1. Control register 0 (PMU_CTL0) ..............................................................................143
5.4.2. Control and status register 0 (PMU_CS0) ................................................................145
5.4.3. Control register 1 (PMU_CTL1) ..............................................................................147
5.4.4. Control and status register 1 (PMU_CS1) ................................................................148
5.4.5. RF Control register (PMU_RFCTL) .........................................................................148
5.4.6. Secure configuration register (PMU_SECCFG).........................................................149
5.4.7. Privilege configuration register (PMU_PRICFG)........................................................150
6. Reset and clock unit (RCU) .....................................................................................152
6.1. Reset control unit (RCTL) ......................................................................................152
6.1.1. Overview ............................................................................................................152
6.1.2. Function overview ................................................................................................152
6.2. Clock control unit (CCTL)......................................................................................153
6.2.1. Overview ............................................................................................................153
6.2.2. Characteristics.....................................................................................................155
6.2.3. Function overview ................................................................................................156
6.3. RCU security protection.........................................................................................159
6.4. RCU privilege protection........................................................................................161
6.5. Register definition..................................................................................................163
6.5.1. Control register (RCU_CTL)...................................................................................163
6.5.2. PLL register (RCU_PLL)........................................................................................166
6.5.3. Clock configuration register 0 (RCU_CFG0).............................................................167
6.5.4. Clock interrupt register (RCU_INT) .........................................................................170
6.5.5. AHB1 reset register (RCU_AHB1RST) ....................................................................173
6.5.6. AHB2 reset register (RCU_AHB2RST) ....................................................................174
6.5.7. AHB3 reset register (RCU_AHB3RST) ....................................................................175
6.5.8. APB1 reset register (RCU_APB1RST).....................................................................176
6.5.9. APB2 reset register (RCU_APB2RST).....................................................................178
6.5.10. AHB1 enable register (RCU_AHB1EN)....................................................................179
6.5.11. AHB2 enable register (RCU_AHB2EN)....................................................................182
6.5.12. AHB3 enable register (RCU_AHB3EN)....................................................................183
6.5.13. APB1 enable register (RCU_APB1EN)....................................................................183
6.5.14. APB2 enable register (RCU_APB2EN)....................................................................185
6.5.15. AHB1 sleep mode enable register (RCU_AHB1SPEN)...............................................187
6.5.16. AHB2 sleep mode enable register (RCU_AHB2SPEN)...............................................189

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6.5.17. AHB3 sleep mode enable register (RCU_AHB3SPEN)...............................................190
6.5.18. APB1 sleep mode enable register (RCU_APB1SPEN)...............................................190
6.5.19. APB2 sleep mode enable register (RCU_APB2SPEN)...............................................192
6.5.20. Backup domain control register (RCU_BDCTL).........................................................194
6.5.21. Reset source/clock register (RCU_RSTSCK)............................................................195
6.5.22. PLL clock spread spectrum control register (RCU_PLLSSCTL) ...................................197
6.5.23. PLL clock configuration register (RCU_PLLCFG) ......................................................198
6.5.24. Clock configuration register 1 (RCU_CFG1).............................................................199
6.5.25. Additional clock control register (RCU_ADDCTL) ......................................................202
6.5.26. Secure protection configuration register (RCU_SECP_CFG).......................................203
6.5.27. Secure protection status register (RCU_SECP_STAT) ...............................................205
6.5.28. AHB1 secure protection status register (RCU_AHB1SECP_STAT) ..............................206
6.5.29. AHB2 secure protection status register (RCU_AHB2SECP_STAT) ..............................209
6.5.30. AHB3 secure protection status register (RCU_AHB3SECP_STAT) ..............................210
6.5.31. APB1 secure protection status register (RCU_APB1SECP_STAT) ...............................210
6.5.32. APB2 secure protection status register (RCU_APB2SECP_STAT) ...............................212
6.5.33. Voltage key register (RCU_VKEY)..........................................................................214
6.5.34. Deep-sleep mode voltage register (RCU_DSV).........................................................214
7. Interrupt/event controller (EXTI).............................................................................216
7.1. Overview.................................................................................................................216
7.2. Characteristics.......................................................................................................216
7.3. Interrupts function overview..................................................................................216
7.4. External interrupt and event (EXTI) block diagram...............................................220
7.5. External interrupt and Event function overview....................................................220
7.6. EXTI event protection.............................................................................................222
7.7. EXTI security protection ........................................................................................223
7.8. EXTI privilege protection .......................................................................................223
7.9. Register definition..................................................................................................224
7.9.1. Interrupt enable register (EXTI_INTEN) ...................................................................224
7.9.2. Event enable register (EXTI_EVEN)........................................................................224
7.9.3. Rising edge trigger enable register (EXTI_RTEN)......................................................225
7.9.4. Falling edge trigger enable register (EXTI_FTEN) .....................................................226
7.9.5. Software interrupt event register (EXTI_SWIEV).......................................................226
7.9.6. Pending register (EXTI_PD)...................................................................................227
7.9.7. Security configuration register (EXTI_SECCFG) .......................................................228
7.9.8. Privilege configuration register (EXTI_PRIVCFG)......................................................228
7.9.9. Lock register (EXTI_LOCK) ...................................................................................229
8. General-purpose and alternate-function I/Os (GPIO and AFIO).........................230
8.1. Overview.................................................................................................................230

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8.2. Characteristics .......................................................................................................230
8.3. Function overview..................................................................................................230
8.3.1. GPIO pin configuration..........................................................................................232
8.3.2. External interrupt/event lines..................................................................................233
8.3.3. Alternate functions (AF).........................................................................................233
8.3.4. Additional functions ..............................................................................................233
8.3.5. Input configuration................................................................................................233
8.3.6. Output configuration.............................................................................................233
8.3.7. Analog configuration.............................................................................................234
8.3.8. Alternate function (AF) configuration .......................................................................235
8.3.9. GPIO locking function...........................................................................................235
8.3.10. GPIO single cycle toggle function ...........................................................................236
8.4. TrustZone GPIO security........................................................................................236
8.5. Register definition..................................................................................................237
8.5.1. Port control register (GPIOx_CTL, x=A..C)...............................................................237
8.5.2. Port output mode register (GPIOx_OMODE, x=A..C).................................................239
8.5.3. Port output speed register (GPIOx_OSPD, x=A..C) ...................................................241
8.5.4. Port pull-up/pull-down register (GPIOx_PUD, x=A..C)................................................243
8.5.5. Port input status register (GPIOx_ISTAT, x=A..C)......................................................245
8.5.6. Port output control register (GPIOx_OCTL, x=A..C)...................................................245
8.5.7. Port bit operate register (GPIOx_BOP, x=A..C) .........................................................246
8.5.8. Port configuration lock register (GPIOx_LOCK, x=A..C) .............................................246
8.5.9. Alternate function selected register 0 (GPIOx_AFSEL0, x=A..C)..................................247
8.5.10. Alternate function selected register 1 (GPIOx_AFSEL1, x=A..C)..................................248
8.5.11. Bit clear register (GPIOx_BC, x=A..C).....................................................................250
8.5.12. Port bit toggle register (GPIOx_TG, x=A..C).............................................................250
8.5.13. GPIO secure configuration register (GPIOx_SCFG) (x=A…C).....................................251
9. TrustZone protection controller union (TZPCU)...................................................252
9.1. Overview.................................................................................................................252
9.2. Characteristics.......................................................................................................252
9.3. Function overview..................................................................................................252
9.3.1. Block diagram......................................................................................................252
9.3.2. Illegal access definition.........................................................................................254
9.3.3. TrustZone® security privilege controller (TZSPC)......................................................255
9.3.4. TrustZone® block based memory protection controller (TZBMPC)...............................256
9.3.5. TrustZone® illegal access controller (TZIAC)............................................................256
9.3.6. SPC/GSSA debug................................................................................................257
9.4. TZSPC Register definition .....................................................................................258
9.4.1. TZSPC control register (TZPCU_TZSPC_CTL).........................................................258
9.4.2. TZSPC secure access mode configuration register 0 (TZPCU_TZSPC_SAM_CFG0) .....258
9.4.3. TZSPC secure access mode configuration register 1 (TZPCU_TZSPC_SAM_CFG1) .....261

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9.4.4. TZSPC secure access mode configuration register 2 (TZPCU_TZSPC_SAM_CFG2) .....263
9.4.5. TZSPC privilege access mode configuration register 0 (TZPCU_TZSPC_PAM_CFG0)...264
9.4.6. TZSPC privilege access mode configuration register 1 (TZPCU_TZSPC_PAM_CFG1)...266
9.4.7. TZSPC privilege access mode configuration register 2 (TZPCU_TZSPC_PAM_CFG2)...269
9.4.8. TZSPC external memory x non-secure mark register 0
(TZPCU_TZSPC_TZMMPCx_NSM0)...................................................................................270
9.4.9. TZSPC external memory x non-secure mark register 1
(TZPCU_TZSPC_TZMMPCx_NSM1)...................................................................................271
9.4.10. TZSPC external memory x non-secure mark register 2
(TZPCU_TZSPC_TZMMPCx_NSM2)...................................................................................272
9.4.11. TZSPC external memory x non-secure mark register 3
(TZPCU_TZSPC_TZMMPCx_NSM3)...................................................................................273
9.4.12. TZSPC debug configuration register (TZPCU_TZSPC_DBG_CFG) .............................274
9.5. TZBMPC0 registers definition................................................................................275
9.5.1. TZBMPC0 control register (TZPCU_TZBMPC0_CTL)................................................275
9.5.2. TZBMPC0 vector register y (TZPCU_TZBMPC0_VECy) ............................................276
9.5.3. TZBMPC0 lock register 0 (TZPCU_TZBMPC0_LOCK0).............................................276
9.6. TZBMPC1 registers definition................................................................................277
9.6.1. TZBMPC1 control register (TZPCU_TZBMPC1_CTL)................................................277
9.6.2. TZBMPC1 vector register y (TZPCU_TZBMPC1_VECy) ............................................278
9.6.3. TZBMPC1 lock register 0 (TZPCU_TZBMPC1_LOCK0).............................................279
9.7. TZBMPC2 registers definition................................................................................279
9.7.1. TZBMPC2 control register (TZPCU_TZBMPC2_CTL)................................................279
9.7.2. TZBMPC2 vector register y (TZPCU_TZBMPC2_VECy) ............................................280
9.7.3. TZBMPC2 lock register 0 (TZPCU_TZBMPC2_LOCK0).............................................281
9.8. TZBMPC3 registers definition................................................................................281
9.8.1. TZBMPC3 control register (TZPCU_TZBMPC3_CTL)................................................282
9.8.2. TZBMPC3 vector register y (TZPCU_TZBMPC3_VECy) ............................................282
9.8.3. TZBMPC3 lock register 0 (TZPCU_TZBMPC3_LOCK0).............................................283
9.9. TZIAC Register definition.......................................................................................284
9.9.1. TZIAC interrupt enable register 0 (TZPCU_TZIAC_INTEN0) .......................................284
9.9.2. TZIAC interrupt enable register 1 (TZPCU_TZIAC_INTEN1) .......................................286
9.9.3. TZIAC interrupt enable register 2 (TZPCU_TZIAC_INTEN2) .......................................289
9.9.4. TZIAC status register 0 (TZPCU_TZIAC_STAT0) ......................................................291
9.9.5. TZIAC status register 1 (TZPCU_TZIAC_STAT1) ......................................................293
9.9.6. TZIAC status register 2 (TZPCU_TZIAC_STAT2) ......................................................296
9.9.7. TZIAC flag clear register 0 (TZPCU_TZIAC_STATC0)................................................298
9.9.8. TZIAC flag clear register 1 (TZPCU_TZIAC_STATC1)................................................300
9.9.9. TZIAC flag clear register 2 (TZPCU_TZIAC_STATC2)................................................303
10. CRC calculation unit (CRC) ..................................................................................306
10.1. Overview .............................................................................................................306

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10.2. Characteristics....................................................................................................306
10.3. Function overview ..............................................................................................307
10.4. Register definition ..............................................................................................308
10.4.1. Data register (CRC_DATA)....................................................................................308
10.4.2. Free data register (CRC_FDATA) ...........................................................................308
10.4.3. Control register (CRC_CTL)...................................................................................309
11. True random number generator (TRNG) ............................................................310
11.1. Overview .............................................................................................................310
11.2. Characteristics....................................................................................................310
11.3. Function overview ..............................................................................................310
11.3.1. Operation flow .....................................................................................................311
11.3.2. Error flags...........................................................................................................311
11.4. Register definition ..............................................................................................312
11.4.1. Control register (TRNG_CTL).................................................................................312
11.4.2. Status register (TRNG_STAT) ................................................................................312
11.4.3. Data register (TRNG_DATA)..................................................................................313
12. Direct memory access controller (DMA) ............................................................315
12.1. Overview.............................................................................................................315
12.2. Characteristics....................................................................................................315
12.3. Block diagram.....................................................................................................316
12.4. Function overview..............................................................................................317
12.4.1. Secure & priviledge ..............................................................................................318
12.4.2. Peripheral handshake...........................................................................................319
12.4.3. Data process.......................................................................................................321
12.4.4. Address generation ..............................................................................................327
12.4.5. Circular mode......................................................................................................327
12.4.6. Switch-buffer mode...............................................................................................328
12.4.7. Transfer flow controller..........................................................................................328
12.4.8. Transfer operation................................................................................................329
12.4.9. Transfer finish......................................................................................................330
12.4.10. Channel configuration...........................................................................................331
12.5. Interrupts.............................................................................................................332
12.5.1. Flag ...................................................................................................................333
12.5.2. Exception............................................................................................................334
12.5.3. Error ..................................................................................................................335
12.6. Register definition ..............................................................................................337
12.6.1. Interrupt flag register 0 (DMA_INTF0)......................................................................337
12.6.2. Interrupt flag register 1 (DMA_INTF1)......................................................................338

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12.6.3. Interrupt flag clear register 0 (DMA_INTC0)..............................................................339
12.6.4. Interrupt flag clear register 1 (DMA_INTC1)..............................................................339
12.6.5. Channel x control register (DMA_CHxCTL) ..............................................................340
12.6.6. Channel x counter register (DMA_CHxCNT).............................................................344
12.6.7. Channel x peripheral base address register (DMA_CHxPADDR) .................................344
12.6.8. Channel x memory 0 base address register (DMA_CHxM0ADDR)...............................345
12.6.9. Channel x memory 1 base address register (DMA_CHxM1ADDR)...............................346
12.6.10. Channel x FIFO control register (DMA_CHxFCTL) ....................................................346
12.6.11. Security status register (DMA_SSTAT) ....................................................................347
12.6.12. Security status clear register (DMA_SSC)................................................................348
12.6.13. Channel x security control register (DMA_CHxSCTL) ................................................349
13. Debug (DBG)...........................................................................................................351
13.1. Overview.............................................................................................................351
13.2. JTAG/SW function description...........................................................................351
13.2.1. Switch JTAG or SW interface.................................................................................351
13.2.2. Pin assignment ....................................................................................................351
13.2.3. JTAG daisy chained structure.................................................................................352
13.2.4. Debug reset ........................................................................................................352
13.2.5. JEDEC-106 ID code.............................................................................................352
13.3. Debug hold function description........................................................................352
13.3.1. Debug support for power saving mode ....................................................................352
13.3.2. Debug support for TIMER, I2C, WWDGT, FWDGT and RTC.......................................353
13.4. DBG registers......................................................................................................354
13.4.1. ID code register (DBG_ID).....................................................................................354
13.4.2. Control register 0 (DBG_CTL0) ..............................................................................354
13.4.3. Control register 1 (DBG_CTL1) ..............................................................................355
13.4.4. Control register 2 (DBG_CTL2) ..............................................................................357
14. Analog to digital converter (ADC) .......................................................................358
14.1. Overview .............................................................................................................358
14.2. Characteristics....................................................................................................358
14.3. Pins and internal signals ....................................................................................359
14.4. Function overview ..............................................................................................360
14.4.1. ADC clock...........................................................................................................360
14.4.2. ADCON switch.....................................................................................................360
14.4.3. Regular and inserted channel groups ......................................................................360
14.4.4. Conversion modes ...............................................................................................361
14.4.5. Inserted channel management ...............................................................................365
14.4.6. Analog watchdog .................................................................................................366
14.4.7. Data alignment ....................................................................................................366
14.4.8. Programmable sampling time.................................................................................367

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14.4.9. External trigger....................................................................................................367
14.4.10. DMA request .......................................................................................................369
14.4.11. Overflow detection ...............................................................................................369
14.4.12. Temperature sensor, internal reference voltage VREFINT and external battery voltage VBAT
369
14.4.13. On-chip hardware oversampling.............................................................................370
14.4.14. ADC interrupts.....................................................................................................372
14.5. Register definition ..............................................................................................373
14.5.1. Status register (ADC_STAT) ..................................................................................373
14.5.2. Control register 0 (ADC_CTL0) ..............................................................................374
14.5.3. Control register 1 (ADC_CTL1) ..............................................................................376
14.5.4. Sample time register 0 (ADC_SAMPT0) ..................................................................378
14.5.5. Sample time register 1 (ADC_SAMPT1) ..................................................................379
14.5.6. Inserted channel data offset register x (ADC_IOFFx) (x=0..3)......................................380
14.5.7. Watchdog high threshold register (ADC_WDHT).......................................................380
14.5.8. Watchdog low threshold register (ADC_WDLT).........................................................380
14.5.9. Regular sequence register 0 (ADC_RSQ0) ..............................................................381
14.5.10. Regular sequence register 1 (ADC_RSQ1) ..............................................................381
14.5.11. Regular sequence register 2 (ADC_RSQ2) ..............................................................382
14.5.12. Inserted sequence register (ADC_ISQ)....................................................................383
14.5.13. Inserted data register x (ADC_IDATAx) (x= 0..3) .......................................................383
14.5.14. Regular data register (ADC_RDATA).......................................................................384
14.5.15. Oversampling control register (ADC_OVSAMPCTL)..................................................384
14.5.16. Commom control register (ADC_CCTL)...................................................................386
15. Watchdog timer (WDGT) .......................................................................................387
15.1. Free watchdog timer (FWDGT)...........................................................................387
15.1.1. Overview ............................................................................................................387
15.1.2. Characteristics.....................................................................................................387
15.1.3. Function overview ................................................................................................387
15.1.4. Register definition ................................................................................................390
15.2. Window watchdog timer (WWDGT)....................................................................393
15.2.1. Overview ............................................................................................................393
15.2.2. Characteristics.....................................................................................................393
15.2.3. Function overview ................................................................................................393
15.2.4. Register definition ................................................................................................396
16. Real time clock (RTC)............................................................................................398
16.1. Overview.............................................................................................................398
16.2. Characteristics....................................................................................................398
16.3. Function overview..............................................................................................399
16.3.1. Block diagram......................................................................................................399
16.3.2. Clock source and prescalers..................................................................................400

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16.3.3. Shadow registers introduction................................................................................400
16.3.4. Configurable and field maskable alarm ....................................................................400
16.3.5. Configurable periodic auto-wakeup counter..............................................................401
16.3.6. RTC initialization and configuration.........................................................................401
16.3.7. Calendar reading .................................................................................................403
16.3.8. Resetting the RTC................................................................................................404
16.3.9. RTC shift function.................................................................................................404
16.3.10. RTC reference clock detection ...............................................................................405
16.3.11. RTC coarse digital calibration.................................................................................406
16.3.12. RTC smooth digital calibration................................................................................406
16.3.13. Time-stamp function.............................................................................................408
16.3.14. Tamper detection .................................................................................................409
16.3.15. Calibration clock output.........................................................................................410
16.3.16. Alarm output........................................................................................................410
16.3.17. RTC security protection.........................................................................................410
16.3.18. RTC privilege protection........................................................................................413
16.3.19. RTC backup registers protection.............................................................................416
16.3.20. RTC power saving mode management....................................................................417
16.3.21. RTC interrupts .....................................................................................................417
16.4. Register definition ..............................................................................................419
16.4.1. Time register (RTC_TIME).....................................................................................419
16.4.2. Date register (RTC_DATE) ....................................................................................419
16.4.3. Control register (RTC_CTL) ...................................................................................420
16.4.4. Initialization control and status register (RTC_ICSR)..................................................423
16.4.5. Prescaler register (RTC_PSC) ...............................................................................424
16.4.6. Wakeup timer register (RTC_WUT).........................................................................425
16.4.7. Coarse calibration register (RTC_COSC).................................................................425
16.4.8. Alarm 0 time and date register (RTC_ALRM0TD)......................................................426
16.4.9. Alarm 1 time and date register (RTC_ALRM1TD)......................................................427
16.4.10. Write protection key register (RTC_WPK) ................................................................429
16.4.11. Sub second register (RTC_SS) ..............................................................................429
16.4.12. Shift function control register (RTC_SHIFTCTL)........................................................429
16.4.13. Time of time stamp register (RTC_TTS)...................................................................430
16.4.14. Date of time stamp register (RTC_DTS)...................................................................431
16.4.15. Sub second of time stamp register (RTC_SSTS).......................................................432
16.4.16. High resolution frequency compensation register (RTC_HRFC)...................................432
16.4.17. Tamper register (RTC_TAMP)................................................................................433
16.4.18. Alarm 0 sub second register (RTC_ALRM0SS).........................................................435
16.4.19. Alarm 1 sub second register (RTC_ALRM1SS).........................................................436
16.4.20. Privilege protection mode control register (RTC_PPM_CTL) .......................................437
16.4.21. Secure protection mode control register (RTC_SPM_CTL) .........................................439
16.4.22. Status register (RTC_STAT)...................................................................................440
16.4.23. Non-secure masked interrupt status register (RTC_NSMI_STAT) ................................441

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16.4.24. Secure masked interrupt status register (RTC_SMI_STAT).........................................442
16.4.25. Status flag clear register (RTC_STATC)...................................................................443
16.4.26. Backup registers (RTC_BKPx) (x=0..19)..................................................................444
17. Timer (TIMERx).......................................................................................................446
17.1. Advanced timer (TIMERx, x=0) ...........................................................................447
17.1.1. Overview ............................................................................................................447
17.1.2. Characteristics.....................................................................................................447
17.1.3. Block diagram......................................................................................................448
17.1.4. Function overview ................................................................................................448
17.1.5. TIMERx registers(x=0)..........................................................................................477
17.2. General level0 timer (TIMERx, x=1, 2, 3, 4).........................................................505
17.2.1. Overview ............................................................................................................505
17.2.2. Characteristics.....................................................................................................505
17.2.3. Block diagram......................................................................................................505
17.2.4. Function overview ................................................................................................506
17.2.5. TIMERx registers(x=1, 2, 3, 4)................................................................................523
17.3. General level4 timer (TIMERx, x=15,16)..............................................................549
17.3.1. Overview ............................................................................................................549
17.3.2. Characteristics.....................................................................................................549
17.3.3. Block diagram......................................................................................................549
17.3.4. Function overview ................................................................................................550
17.3.5. TIMERx registers(x=15, 16)...................................................................................564
17.4. Basic timer (TIMERx, x=5)...................................................................................580
17.4.1. Overview ............................................................................................................580
17.4.2. Characteristics.....................................................................................................580
17.4.3. Block diagram......................................................................................................580
17.4.4. Function overview ................................................................................................580
17.4.5. TIMERx registers(x=5)..........................................................................................584
18. Universal synchronous/asynchronous receiver /transmitter (USART).........589
18.1. Overview.............................................................................................................589
18.2. Characteristics....................................................................................................589
18.3. Function overview..............................................................................................591
18.3.1. USART frame format ............................................................................................591
18.3.2. Baud rate generation............................................................................................592
18.3.3. USART transmitter ...............................................................................................593
18.3.4. USART receiver ...................................................................................................594
18.3.5. Use DMA for data buffer access .............................................................................595
18.3.6. Hardware flow control...........................................................................................597
18.3.7. Multi-processor communication..............................................................................598
18.3.8. LIN mode............................................................................................................599

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18.3.9. Synchronous mode ..............................................................................................600
18.3.10. IrDA SIR ENDEC mode.........................................................................................601
18.3.11. Half-duplex communication mode...........................................................................602
18.3.12. Smartcard (ISO7816-3) mode................................................................................602
18.3.13. Auto baudrate detection........................................................................................604
18.3.14. ModBus communication........................................................................................605
18.3.15. Receive FIFO......................................................................................................605
18.3.16. Wakeup from Deep-sleep mode .............................................................................606
18.3.17. USART interrupts .................................................................................................606
18.4. Register definition ..............................................................................................608
18.4.1. Control register 0 (USART_CTL0)...........................................................................608
18.4.2. Control register 1 (USART_CTL1)...........................................................................610
18.4.3. Control register 2 (USART_CTL2)...........................................................................613
18.4.4. Baud rate generator register (USART_BAUD) ..........................................................616
18.4.5. Prescaler and guard time configuration register (USART_GP).....................................616
18.4.6. Receiver timeout register (USART_RT) ...................................................................617
18.4.7. Command register (USART_CMD) .........................................................................618
18.4.8. Status register (USART_STAT) ..............................................................................619
18.4.9. Interrupt status clear register (USART_INTC) ...........................................................623
18.4.10. Receive data register (USART_RDATA) ..................................................................624
18.4.11. Transmit data register (USART_TDATA) ..................................................................625
18.4.12. USART coherence control register (USART_CHC)....................................................625
18.4.13. USART receive FIFO control and status register (USART_RFCS) ...............................626
19. Inter-integrated circuit interface (I2C).................................................................628
19.1. Overview .............................................................................................................628
19.2. Characteristics....................................................................................................628
19.3. Function overview ..............................................................................................628
19.3.1. Clock requirements ..............................................................................................629
19.3.2. I2C communication flow ........................................................................................630
19.3.3. Noise filter...........................................................................................................633
19.3.4. I2C timings..........................................................................................................633
19.3.5. Software reset.....................................................................................................635
19.3.6. Data transfer .......................................................................................................635
19.3.7. I2C slave mode....................................................................................................638
19.3.8. I2C master mode .................................................................................................643
19.3.9. SMBus support ....................................................................................................648
19.3.10. SMBus mode.......................................................................................................651
19.3.11. Wakeup from Deep-sleep mode .............................................................................653
19.3.12. Use DMA for data transfer .....................................................................................653
19.3.13. I2C error and interrupts .........................................................................................654
19.3.14. I2C debug mode ..................................................................................................654

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19.4. Register definition ..............................................................................................655
19.4.1. Control register 0 (I2C_CTL0) ................................................................................655
19.4.2. Control register 1 (I2C_CTL1) ................................................................................657
19.4.3. Slave address register 0 (I2C_SADDR0) .................................................................659
19.4.4. Slave address register 1 (I2C_SADDR1) .................................................................660
19.4.5. Timing register (I2C_TIMING) ................................................................................661
19.4.6. Timeout register (I2C_TIMEOUT) ...........................................................................662
19.4.7. Status register (I2C_STAT) ....................................................................................663
19.4.8. Status clear register (I2C_STATC) ..........................................................................666
19.4.9. PEC register (I2C_PEC)........................................................................................667
19.4.10. Receive data register (I2C_RDATA)........................................................................667
19.4.11. Transmit data register (I2C_TDATA)........................................................................668
19.4.12. Control register 2 (I2C_CTL2) ................................................................................668
20. Serial peripheral interface/Inter-IC sound (SPI/I2S)..........................................670
20.1. Overview .............................................................................................................670
20.2. Characteristics....................................................................................................670
20.2.1. SPI characteristics ...............................................................................................670
20.2.2. I2S characteristics................................................................................................670
20.3. SPI block diagram...............................................................................................671
20.4. SPI signal description.........................................................................................671
20.4.1. Normal configuration (Not Quad-SPI Mode).............................................................671
20.4.2. Quad-SPI configuration.........................................................................................672
20.5. SPI function overview.........................................................................................672
20.5.1. SPI clock timing and data format ............................................................................672
20.5.2. NSS function.......................................................................................................673
20.5.3. SPI operating modes ............................................................................................674
20.5.4. DMA function.......................................................................................................682
20.5.5. CRC function.......................................................................................................682
20.6. SPI interrupts......................................................................................................683
20.6.1. Status flags.........................................................................................................683
20.6.2. Error flags...........................................................................................................683
20.7. I2S block diagram ...............................................................................................684
20.8. I2S signal description .........................................................................................685
20.9. I2S function overview .........................................................................................685
20.9.1. I2S audio standards..............................................................................................685
20.9.2. I2S clock.............................................................................................................693
20.9.3. Operation............................................................................................................694
20.9.4. DMA function.......................................................................................................697
20.10. I2S interrupts ......................................................................................................698
20.10.1. Status flags .........................................................................................................698

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20.10.2. Error flags...........................................................................................................698
20.11. Register definition ..............................................................................................700
20.11.1. Control register 0 (SPI_CTL0) ................................................................................700
20.11.2. Control register 1 (SPI_CTL1) ................................................................................702
20.11.3. Status register (SPI_STAT)....................................................................................703
20.11.4. Data register (SPI_DATA)......................................................................................704
20.11.5. CRC polynomial register (SPI_CRCPOLY)...............................................................705
20.11.6. RX CRC register (SPI_RCRC) ...............................................................................705
20.11.7. TX CRC register (SPI_TCRC) ................................................................................706
20.11.8. I2S control register (SPI_I2SCTL)...........................................................................707
20.11.9. I2S clock prescaler register (SPI_I2SPSC)...............................................................708
20.11.10.Quad-SPI mode control register (SPI_QCTL) of SPI0 ................................................709
21. Serial/Quad Parallel Interface (SQPI) .................................................................. 711
21.1. Overview.............................................................................................................711
21.2. Characteristics....................................................................................................711
21.3. Function overview..............................................................................................711
21.3.1. SQPI mode definition............................................................................................711
21.3.2. SQPI controller sampling polarity............................................................................712
21.3.3. SQPI controller special command...........................................................................713
21.3.4. SQPI controller read ID command ..........................................................................713
21.3.5. SQPI controller output clock configuration................................................................714
21.3.6. SQPI controller initialization...................................................................................714
21.3.7. Read ID command flow.........................................................................................714
21.3.8. Read/Write operation flow .....................................................................................714
21.3.9. SQPI controller mode timing ..................................................................................714
21.4. Register definition ..............................................................................................716
21.4.1. SQPI Initial Register (SQPI_INIT) ...........................................................................717
21.4.2. SQPI Read Command Register (SQPI_RCMD) ........................................................717
21.4.3. SQPI Write Command Register (SQPI_WCMD)........................................................718
21.4.4. SQPI ID Low Register (SQPI_IDL)..........................................................................719
21.4.5. SQPI ID High Register (SQPI_IDH).........................................................................719
22. Quad-SPI interface (QSPI) ....................................................................................721
22.1. Overview.............................................................................................................721
22.2. Characteristics....................................................................................................721
22.3. Function overview ..............................................................................................721
22.3.1. QSPI block diagram..............................................................................................721
22.3.2. QSPI command format..........................................................................................723
22.3.3. QSPI signal line modes.........................................................................................724
22.3.4. CSN and SCK behavior.........................................................................................725

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22.4. Operating modes................................................................................................726
22.4.1. Indirect mode ......................................................................................................726
22.4.2. Status polling mode..............................................................................................727
22.4.3. Memory map mode ..............................................................................................727
22.4.4. FMC mode..........................................................................................................728
22.5. QSPI configuration.............................................................................................729
22.5.1. Flash configuration...............................................................................................729
22.5.2. QSPI IP configuration ...........................................................................................729
22.6. Securitydescription............................................................................................729
22.7. Send instruction only once.................................................................................730
22.8. Busy....................................................................................................................730
22.9. Error management..............................................................................................730
22.10. QSPI interrupts...................................................................................................731
22.11. Register definition ..............................................................................................732
22.11.1. Control register (QSPI_CTL) ..................................................................................732
22.11.2. Device configuration register (QSPI_DCFG).............................................................734
22.11.3. Status register (QSPI_STAT)..................................................................................735
22.11.4. Status clear register (QSPI_STATC)........................................................................737
22.11.5. Data length register (QSPI_DTLEN)........................................................................738
22.11.6. Transfer configuration register (QSPI_TCFG) ...........................................................738
22.11.7. Address register (QSPI_ADDR)..............................................................................740
22.11.8. Alternate bytes register (QSPI_ALTE)......................................................................741
22.11.9. Data register (QSPI_DATA) ...................................................................................741
22.11.10.Secure Status register (QSPI_STAT_SEC)...............................................................742
22.11.11.Secure Status clear register (QSPI_STATC_SEC).....................................................743
22.11.12.Secure Data length register (QSPI_DTLEN_SEC).....................................................744
22.11.13.Secure Transfer configuration register (QSPI_TCFG_SEC) ........................................745
22.11.14.Secure Address register (QSPI_ADDR_SEC)...........................................................747
22.11.15.Secure Alternate bytes register (QSPI_ALTE_SEC)...................................................747
22.11.16.Secure Data register (QSPI_DATA_SEC).................................................................748
22.11.17.Status mask register (QSPI_STATMK).....................................................................748
22.11.18.Status match register (QSPI_ STATMATCH) ............................................................749
22.11.19.Interval register (QSPI_INTERVAL).........................................................................749
22.11.20.Timeout register (QSPI_TMOUT)............................................................................750
22.11.21.FIFO flush register (QSPI_FLUSH).........................................................................750
22.11.22.Wait cnt for indirect wire mode register (QSPI_WTCNT).............................................751
22.11.23.Timeout for staus polling mode register (QSPI_SPTMOUT)........................................751
22.11.24.FMC mode security configuration register (QSPI_FMC_SECCFG)...............................751
22.11.25.Control register in FMC mode (QSPI_CTLF) ............................................................752
22.11.26.Transfer configuration register in FMC mode (QSPI_TCFGF)......................................753
22.11.27.Alternate bytes register in FMC mode (QSPI_ALTEF)................................................755

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22.11.28.Complete bytes counter register (QSPI_BYTE_CNT).................................................756
22.11.29.Privilege configuration register (QSPI_PRIVCFG) .....................................................756
23. Secure digital input/output interface (SDIO) .....................................................758
23.1. Introduction.........................................................................................................758
23.2. Main features ......................................................................................................758
23.3. SDIO bus topology..............................................................................................758
23.4. SDIO functional description ...............................................................................761
23.4.1. SDIO adapter ......................................................................................................761
23.4.2. APB2 interface.....................................................................................................765
23.5. Card functional description................................................................................766
23.5.1. Card registers......................................................................................................766
23.5.2. Commands .........................................................................................................768
23.5.3. Responses..........................................................................................................779
23.5.4. Data packets format .............................................................................................783
23.5.5. Two status fields of the card...................................................................................784
23.6. Programming sequence .....................................................................................792
23.6.1. Card identification ................................................................................................792
23.6.2. No data commands ..............................................................................................794
23.6.3. Single block or multiple block write..........................................................................794
23.6.4. Single block or multiple block read..........................................................................795
23.6.5. Stream write and stream read (MMC only)...............................................................796
23.6.6. Erase.................................................................................................................798
23.6.7. Bus width selection...............................................................................................799
23.6.8. Protection management........................................................................................799
23.6.9. Card Lock/Unlock operation...................................................................................799
23.7. Specific operations.............................................................................................802
23.7.1. SD I/O specific operations .....................................................................................802
23.7.2. CE-ATA specific operations....................................................................................805
23.8. SDIO registers.....................................................................................................807
23.8.1. Power control register (SDIO_PWRCTL) .................................................................807
23.8.2. Clock control register (SDIO_CLKCTL)....................................................................807
23.8.3. Command argument register (SDIO_CMDAGMT) .....................................................809
23.8.4. Command control register (SDIO_CMDCTL) ............................................................809
23.8.5. Command index response register (SDIO_RSPCMDIDX)...........................................811
23.8.6. Response register (SDIO_RESPx x=0..3)................................................................811
23.8.7. Data timeout register (SDIO_DATATO)....................................................................812
23.8.8. Data length register (SDIO_DATALEN)....................................................................812
23.8.9. Data control register (SDIO_DATACTL) ...................................................................813
23.8.10. Data counter register (SDIO_DATACNT)..................................................................814
23.8.11. Status register (SDIO_STAT) .................................................................................815

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23.8.12. Interrupt clear register (SDIO_INTC) .......................................................................816
23.8.13. Interrupt enable register (SDIO_INTEN) ..................................................................818
23.8.14. FIFO counter register (SDIO_FIFOCNT)..................................................................819
23.8.15. FIFO data register (SDIO_FIFO).............................................................................820
24. Universal serial bus full-speed interface (USBFS) ...........................................821
24.1. Overview.............................................................................................................821
24.2. Characteristics....................................................................................................821
24.3. Block diagram.....................................................................................................822
24.4. Signal description...............................................................................................822
24.5. Function overview..............................................................................................822
24.5.1. USBFS clocks and working modes .........................................................................822
24.5.2. USB host function ................................................................................................824
24.5.3. USB device function.............................................................................................826
24.5.4. OTG function overview..........................................................................................827
24.5.5. Data FIFO...........................................................................................................828
24.5.6. Operation guide...................................................................................................831
24.6. Interrupts.............................................................................................................835
24.7. Register definition ..............................................................................................837
24.7.1. Global control and status registers..........................................................................837
24.7.2. Host control and status registers.............................................................................858
24.7.3. Device control and status registers .........................................................................870
24.7.4. Power and clock control register (USBFS_PWRCLKCTL)...........................................894
25. Digital camera interface (DCI) ..............................................................................895
25.1. Overview .............................................................................................................895
25.2. Characteristics....................................................................................................895
25.3. Block diagram.....................................................................................................895
25.4. Signal description...............................................................................................896
25.5. Function overview ..............................................................................................896
25.5.1. DCI hardware synchronization mode.......................................................................896
25.5.2. Embedded synchronization mode...........................................................................897
25.5.3. Capture data using snapshot or continuous capture modes ........................................897
25.5.4. Window function ..................................................................................................898
25.5.5. Pixel formats, data padding and DMA......................................................................898
25.6. Interrupts.............................................................................................................899
25.7. Register definition ..............................................................................................900
25.7.1. Control register (DCI_CTL) ....................................................................................900
25.7.2. Status register0 (DCI_STAT0) ................................................................................901
25.7.3. Status register1 (DCI_STAT1) ................................................................................902

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25.7.4. Interrupt enable register (DCI_INTEN).....................................................................902
25.7.5. Interrupt flag register (DCI_INTF)............................................................................903
25.7.6. Interrupt flag clear register (DCI_INTC)....................................................................904
25.7.7. Synchronization codes register (DCI_SC) ................................................................904
25.7.8. Synchronization codes unmask register (DCI_SCUMSK) ...........................................905
25.7.9. Cropping window start position register (DCI_CWSPOS)............................................905
25.7.10. Cropping window size register (DCI_CWSZ) ............................................................906
25.7.11. DATA register (DCI_DATA) ....................................................................................907
26. Touch sensing interface (TSI) ..............................................................................908
26.1. Overview.............................................................................................................908
26.2. Characteristics....................................................................................................908
26.3. Function Overview..............................................................................................908
26.3.1. TSI block diagram................................................................................................908
26.3.2. Touch sensing technique overview..........................................................................908
26.3.3. Charge transfer sequence.....................................................................................909
26.3.4. Charge transfer sequence FSM..............................................................................911
26.3.5. Clock and duration time of states............................................................................913
26.3.6. PIN mode control of TSI........................................................................................914
26.3.7. Analog switch (ASW) and I/O hysteresis mode .........................................................914
26.3.8. TSI operation flow................................................................................................915
26.3.9. TSI flags and interrupts .........................................................................................915
26.3.10. TSI GPIOs ..........................................................................................................915
26.4. Registers definition.............................................................................................916
26.4.1. Control register0 (TSI_CTL0) .................................................................................916
26.4.2. Interrupt enable register(TSI_INTEN) ......................................................................918
26.4.3. Interrupt flag clear register (TSI_INTC) ....................................................................919
26.4.4. Interrupt flag register (TSI_INTF) ............................................................................919
26.4.5. Pin hysteresis mode register(TSI_PHM) ..................................................................920
26.4.6. Analog switch register(TSI_ASW)...........................................................................920
26.4.7. Sample configuration register(TSI_SAMPCFG).........................................................921
26.4.8. Channel configuration register(TSI_CHCFG)............................................................921
26.4.9. Group control register(TSI_GCTL) ..........................................................................922
26.4.10. Group x cycle number registers(TSI_GxCYCN)(x = 0..2)............................................923
26.4.11. Control register1 (TSI_CTL1) .................................................................................923
27. Cryptographic Acceleration Unit (CAU) .............................................................925
27.1. Overview.............................................................................................................925
27.2. Characteristics....................................................................................................925
27.3. CAU data type and initializationvectors............................................................926
27.3.1. Data type............................................................................................................926
27.3.2. Initialization vectors ..............................................................................................927