GigaDevice Semiconductor GD32F20 Series User manual

GigaDevice Semiconductor Inc.
GD32F20x
ARM®Cortex™-M3 32-bit MCU
User Manual
Revision 2.2
( Oct. 2019 )

GD32F20x User Manual
2
Table of Contents
Table of Contents.................................................................................................................... 2
List of Figures ....................................................................................................................... 20
List of Tables......................................................................................................................... 28
1. System and memory architecture ........................................................................... 32
1.1. ARM Cortex-M3 processor.................................................................................................. 32
1.2. System architecture ........................................................................................................... 33
1.3. Memory map ..................................................................................................................... 34
1.3.1. Bit-banding.........................................................................................................................................38
1.3.2. On-chip SRAM memory...................................................................................................................39
1.3.3. On-chip Flash memory.....................................................................................................................39
1.4. Boot configuration ............................................................................................................. 39
1.5. Device electronic signature................................................................................................. 40
1.5.1. Memory size information..................................................................................................................41
1.5.2. Unique device ID (96 bits)...............................................................................................................41
1.6. System configuration registers ............................................................................................ 42
2. Flash memory controller (FMC)............................................................................... 44
2.1. Overview ........................................................................................................................... 44
2.2. Characteristics ................................................................................................................... 44
2.3. Function overview.............................................................................................................. 44
2.3.1. Flash memory architecture..............................................................................................................44
2.3.2. Read operations................................................................................................................................45
2.3.3. Unlock the FMC_CTLx registers ....................................................................................................45
2.3.4. Page erase ........................................................................................................................................46
2.3.5. Mass erase........................................................................................................................................47
2.3.6. Main flash programming..................................................................................................................49
2.3.7. Option bytes Erase...........................................................................................................................50
2.3.8. Option bytes modify..........................................................................................................................51
2.3.9. Option bytes description..................................................................................................................51
2.3.10. Page erase/program protection......................................................................................................53
2.3.11. Security protection............................................................................................................................53
2.4. Register definition.............................................................................................................. 53
2.4.1. Wait state register (FMC_WS)........................................................................................................53
2.4.2. Unlock key register 0(FMC_KEY0)................................................................................................54
2.4.3. Option byte unlock key register (FMC_OBKEY)..........................................................................54
2.4.4. Status register 0 (FMC_STAT0)......................................................................................................55

GD32F20x User Manual
3
2.4.5. Control register 0(FMC_CTL0).......................................................................................................56
2.4.6. Address register 0 (FMC_ADDR0).................................................................................................57
2.4.7. Option byte status register (FMC_OBSTAT).................................................................................57
2.4.8. Erase/Program Protection register (FMC_WP)............................................................................58
2.4.9. Unlock key register 1(FMC_KEY1)................................................................................................58
2.4.10. Status register 1 (FMC_STAT1)......................................................................................................59
2.4.11. Control register 1(FMC_CTL1).......................................................................................................60
2.4.12. Address register 1 (FMC_ADDR1).................................................................................................61
2.4.13. Wait state enable register (FMC_WSEN) .....................................................................................61
2.4.14. Product ID register (FMC_PID) ......................................................................................................62
3. Power management unit (PMU)............................................................................... 63
3.1. Overview ........................................................................................................................... 63
3.2. Characteristics ................................................................................................................... 63
3.3. Function overview.............................................................................................................. 63
3.3.1. Battery backup domain....................................................................................................................64
3.3.2. VDD/VDDA power domain...................................................................................................................65
3.3.3. 1.2V power domain...........................................................................................................................67
3.3.4. Power saving modes........................................................................................................................67
3.4. Register definition.............................................................................................................. 70
3.4.1. Control register (PMU_CTL) ...........................................................................................................70
3.4.2. Control and status register (PMU_CS)..........................................................................................71
4. Backup registers (BKP) ............................................................................................ 73
4.1. Overview ........................................................................................................................... 73
4.2. Characteristics ................................................................................................................... 73
4.3. Function overview.............................................................................................................. 73
4.3.1. RTC clock calibration .......................................................................................................................73
4.3.2. Tamper0 detection............................................................................................................................74
4.3.3. Tamper1 detection............................................................................................................................74
16.1.1. Waveform detection..........................................................................................................................74
4.4. Register definition.............................................................................................................. 75
4.4.1. Backup data register x (BKP_DATAx) (x= 0..41) .........................................................................75
4.4.2. RTC signal output control register (BKP_OCTL).........................................................................75
4.4.3. Tamper pin control register0 (BKP_TPCTL0)...............................................................................76
4.4.4. Tamper control and status register (BKP_TPCS) ........................................................................76
4.4.5. Tamper pin control register1 (BKP_TPCTL1)...............................................................................78
5. Reset and clock unit (RCU) ...................................................................................... 80
5.1. Reset control unit (RCTL) .................................................................................................... 80
5.1.1. Overview............................................................................................................................................80
5.1.2. Function overview.............................................................................................................................80

GD32F20x User Manual
4
5.2. Clock control unit (CCTL)..................................................................................................... 81
5.2.1. Overview............................................................................................................................................81
5.2.2. Characteristics...................................................................................................................................83
5.2.3. Function overview.............................................................................................................................83
5.3. Register definition.............................................................................................................. 88
5.3.1. Control register (RCU_CTL)............................................................................................................88
5.3.2. Configuration register 0 (RCU_CFG0) ..........................................................................................90
5.3.3. Interrupt register (RCU_INT)...........................................................................................................93
5.3.4. APB2 reset register (RCU_APB2RST)..........................................................................................96
5.3.5. APB1 reset register (RCU_APB1RST)..........................................................................................99
5.3.6. AHB1 enable register (RCU_AHB1EN).......................................................................................101
5.3.7. APB2 enable register (RCU_APB2EN).......................................................................................103
5.3.8. APB1 enable register (RCU_APB1EN).......................................................................................106
5.3.9. Backup domain control register (RCU_BDCTL) ........................................................................109
5.3.10. Reset source/clock register (RCU_RSTSCK) ............................................................................110
5.3.11. AHB1 reset register (RCU_AHB1RST).......................................................................................112
5.3.12. Configuration register 1 (RCU_CFG1) ........................................................................................112
5.3.13. Deep-sleep mode voltage register (RCU_DSV) ........................................................................114
5.3.14. AHB2 enable register (RCU_AHB2EN).......................................................................................115
5.3.15. APB2 additional enable register (RCU_ADDAPB2EN).............................................................116
5.3.16. APB1 additional enable register (RCU_ADDAPB1EN).............................................................117
5.3.17. AHB2 reset register (RCU_AHB2RST) .......................................................................................117
5.3.18. APB2 additional reset register (RCU_ADDAPB2RST) .............................................................118
5.3.19. APB1 additional reset register (RCU_ADDAPB1RST) .............................................................119
5.3.20. Configuration register 2 (RCU_ CFG2) .......................................................................................120
5.3.21. PLLT control register (RCU_PLLTCTL).......................................................................................121
5.3.22. PLLT interrupt register (RCU_PLLTINT) .....................................................................................122
5.3.23. PLLT configuration register (RCU_PLLTCFG) ...........................................................................122
6. Interrupt/event controller(EXTI)............................................................................. 125
6.1. Overview ......................................................................................................................... 125
6.2. Characteristics ................................................................................................................. 125
6.3. Interrupts function overview............................................................................................ 125
6.4. External interrupt and event (EXTI) block diagram ............................................................ 129
6.5. External Interrupt and Event function overview................................................................ 129
6.6. Register definition............................................................................................................ 131
6.6.1. Interrupt enable register (EXTI_INTEN)......................................................................................131
6.6.2. Event enable register (EXTI_EVEN)............................................................................................131
6.6.3. Rising edge trigger enable register (EXTI_RTEN).....................................................................132
6.6.4. Falling edge trigger enable register (EXTI_FTEN) ....................................................................132
6.6.5. Software interrupt event register (EXTI_SWIEV).......................................................................132
6.6.6. Pending register (EXTI_PD)..........................................................................................................133

GD32F20x User Manual
5
7. General-purpose and alternate-function I/Os (GPIO and AFIO)........................ 134
7.1. Overview ......................................................................................................................... 134
7.2. Characteristics ................................................................................................................. 134
7.3. Function overview............................................................................................................ 134
7.3.1. GPIO pin configuration...................................................................................................................136
7.3.2. External interrupt/event lines ........................................................................................................136
7.3.3. Alternate functions (AF).................................................................................................................136
7.3.4. Input configuration..........................................................................................................................136
7.3.5. Output configuration.......................................................................................................................137
7.3.6. Analog configuration.......................................................................................................................138
7.3.7. Alternate function (AF) configuration...........................................................................................138
7.3.8. IO pin function selection ................................................................................................................139
7.3.9. GPIO locking function ....................................................................................................................139
7.4. Remapping function I/O and debug configuration............................................................. 140
7.4.1. Introduction......................................................................................................................................140
7.4.2. Main features...................................................................................................................................140
7.4.3. JTAG/SWD alternate function remapping...................................................................................140
7.4.4. ADC AF remapping.........................................................................................................................141
7.4.5. TIMER AF remapping.....................................................................................................................142
7.4.6. USART AF remapping....................................................................................................................144
7.4.7. I2C AF remapping...........................................................................................................................145
7.4.8. SPI AF remapping...........................................................................................................................146
7.4.9. CAN AF remapping.........................................................................................................................146
7.4.10. Ethernet AF remapping..................................................................................................................147
7.4.11. DCI AF remapping..........................................................................................................................148
7.4.12. TLI AF remapping ...........................................................................................................................148
7.4.13. CLK pins AF remapping.................................................................................................................149
7.5. Register definition............................................................................................................ 151
7.5.1. Port control register 0 (GPIOx_CTL0, x=A..I).............................................................................151
7.5.2. Port control register 1 (GPIOx_CTL1, x=A..I).............................................................................153
7.5.3. Port input status register (GPIOx_ISTAT, x=A..I).......................................................................154
7.5.4. Port output control register (GPIOx_OCTL, x=A..I)...................................................................155
7.5.5. Port bit operate register (GPIOx_BOP, x=A..I)...........................................................................155
7.5.6. Port bit clear register (GPIOx_BC, x=A..I) ..................................................................................156
7.5.7. Port configuration lock register (GPIOx_LOCK, x=A..I)............................................................156
7.5.8. Event control register (AFIO_EC).................................................................................................157
7.5.9. AFIO port configuration register 0 (AFIO_PCF0).......................................................................158
7.5.10. EXTI sources selection register 0 (AFIO_EXTISS0).................................................................162
7.5.11. EXTI sources selection register 1 (AFIO_EXTISS1).................................................................163
7.5.12. EXTI sources selection register 2 (AFIO_EXTISS2).................................................................165
7.5.13. EXTI sources selection register 3 (AFIO_EXTISS3).................................................................166
7.5.14. AFIO port configuration register 1 (AFIO_PCF1).......................................................................167

GD32F20x User Manual
6
7.5.15. AFIO port configuration register 2 (AFIO_PCF2).......................................................................169
7.5.16. AFIO port configuration register 3 (AFIO_PCF3).......................................................................171
7.5.17. AFIO port configuration register 4 (AFIO_PCF4).......................................................................175
7.5.18. AFIO port configuration register 5 (AFIO_PCF5).......................................................................178
8. CRC calculation unit (CRC).................................................................................... 183
8.1. Overview ......................................................................................................................... 183
8.2. Characteristics ................................................................................................................. 183
8.3. Function overview............................................................................................................ 184
8.4. Register definition............................................................................................................ 185
8.4.1. Data register (CRC_DATA) ...........................................................................................................185
8.4.2. Free data register (CRC_FDATA) ................................................................................................185
8.4.3. Control register (CRC_CTL)..........................................................................................................186
9. True random number generator (TRNG)............................................................... 187
9.1. Overview ......................................................................................................................... 187
9.2. Characteristics............................................................................................................. 187
9.3. Function overview........................................................................................................ 187
9.3.1. Operation flow.................................................................................................................................188
9.3.2. Error flags ........................................................................................................................................188
9.4. Register definition........................................................................................................ 189
9.4.1. Control register (TRNG_CTL).......................................................................................................189
9.4.2. Status register (TRNG_STAT) ......................................................................................................189
9.4.3. Data register (TRNG_DATA).........................................................................................................190
10. Cryptographic Acceleration Unit (CAU) ............................................................ 192
10.1. Overview...................................................................................................................... 192
10.2. Characteristics.............................................................................................................. 192
10.3. CAU data type and initialization vectors ........................................................................ 193
10.3.1. Data type..........................................................................................................................................193
10.3.2. Initialization vectors........................................................................................................................194
10.4. Cryptographic acceleration processor............................................................................ 194
10.4.1. DES/TDES cryptographic acceleration processor.....................................................................195
10.4.2. AES cryptographic acceleration processor.................................................................................199
10.5. Operating modes.......................................................................................................... 203
10.6. CAU DMA interface....................................................................................................... 204
10.7. CAU interrupts.............................................................................................................. 205
10.8. CAU suspended mode................................................................................................... 205
10.9. Register definition ........................................................................................................ 207
10.9.1. CAU control register (CAU_CTL).................................................................................................207

GD32F20x User Manual
7
10.9.2. CAU Status register 0 (CAU_STAT0) ..........................................................................................208
10.9.3. CAU data input register (CAU_DI) ...............................................................................................209
10.9.4. CAU data output register (CAU_DO)...........................................................................................210
10.9.5. CAU DMA enable register (CAU_DMAEN).................................................................................210
10.9.6. CAU interrupt enable register (CAU_INTEN).............................................................................211
10.9.7. CAU Status register 1 (CAU_STAT1) ..........................................................................................211
10.9.8. CAU interrupt flag register (CAU_INTF)......................................................................................212
10.9.9. CAU key registers (CAU_KEY0..3(H/L)).....................................................................................212
10.9.10. CAU Initial vector registers (CAU_IV0..1(H/L))......................................................................215
11. Hash Acceleration Unit (HAU)............................................................................. 217
11.1. Overview...................................................................................................................... 217
11.2. Characteristics.............................................................................................................. 217
11.3. HAU data type.............................................................................................................. 217
11.4. HAU core...................................................................................................................... 219
11.4.1. Automatic data padding.................................................................................................................219
11.4.2. Digest computing............................................................................................................................220
11.4.3. Hash mode ......................................................................................................................................221
11.4.4. HMAC mode....................................................................................................................................221
11.5. HAU interrupt............................................................................................................... 221
11.6. Register definition ........................................................................................................ 223
11.6.1. HAU control register (HAU_CTL).................................................................................................223
11.6.2. HAU data input register (HAU_DI)...............................................................................................224
11.6.3. HAU configuration register (HAU_CFG) .....................................................................................225
11.6.4. HAU data output register (HAU_DO0..7) ....................................................................................226
11.6.5. HAU interrupt enable register (HAU_INTEN).............................................................................228
11.6.6. HAU status and interrupt flag register (HAU_STAT)..................................................................228
12. Direct memory access controller (DMA) ........................................................... 230
12.1. Overview.................................................................................................................... 230
12.2. Characteristics.......................................................................................................... 230
12.3. Block diagram........................................................................................................... 231
12.4. Function overview.................................................................................................... 231
12.4.1. DMA operation.................................................................................................................................231
12.4.2. Peripheral handshake....................................................................................................................233
12.4.3. Arbitration.........................................................................................................................................234
12.4.4. Address generation ........................................................................................................................234
12.4.5. Circular mode..................................................................................................................................234
12.4.6. Memory to memory mode..............................................................................................................235
12.4.7. Channel configuration....................................................................................................................235
12.4.8. Interrupt............................................................................................................................................235
12.4.9. DMA request mapping ...................................................................................................................236

GD32F20x User Manual
8
12.5. Register definition.................................................................................................... 240
12.5.1. Interrupt flag register (DMA_INTF)...............................................................................................240
12.5.2. Interrupt flag clear register (DMA_INTC) ....................................................................................240
12.5.3. Channel x control register (DMA_CHxCTL)................................................................................241
12.5.4. Channel x counter register (DMA_CHxCNT)..............................................................................243
12.5.5. Channel x peripheral base address register (DMA_CHxPADDR)...........................................244
12.5.6. Channel x memory base address register (DMA_CHxMADDR).............................................244
12.5.7. DMA additional configuration register (DMA_ACFG)................................................................245
13. Debug (DBG) ......................................................................................................... 246
13.1. Overview...................................................................................................................... 246
13.2. JTAG/SW characteristics ............................................................................................... 246
13.2.1. Switch JTAG or SW interface........................................................................................................246
13.2.2. Pin assignment................................................................................................................................246
13.2.3. JTAG daisy chained structure.......................................................................................................247
13.2.4. Debug reset.....................................................................................................................................247
13.2.5. JEDEC-106 ID code.......................................................................................................................247
13.3. Debug hold function overview ...................................................................................... 247
13.3.1. Debug support for power saving mode .......................................................................................247
13.3.2. Debug support for TIMER, I2C, WWDGT, FWDGT and CAN..................................................248
13.4. Register definition ........................................................................................................ 249
13.4.1. ID code register (DBG_ID)............................................................................................................249
13.4.2. Control register (DBG_CTL)..........................................................................................................249
14. Analog-to-digital converter (ADC)...................................................................... 253
14.1. Overview...................................................................................................................... 253
14.2. Characteristics.............................................................................................................. 253
14.3. Pins and internal signals ............................................................................................... 254
14.4. Function overview ........................................................................................................ 255
14.4.1. Calibration (CLB) ............................................................................................................................255
14.4.2. ADC clock........................................................................................................................................256
14.4.3. ADCON switch ................................................................................................................................256
14.4.4. Regular and inserted channel groups..........................................................................................256
14.4.5. Conversion modes..........................................................................................................................256
14.4.6. Inserted channel management.....................................................................................................261
14.4.7. Analog watchdog ............................................................................................................................262
14.4.8. Data alignment................................................................................................................................262
14.4.9. Programmable sample time ..........................................................................................................264
14.4.10. External trigger............................................................................................................................264
14.4.11. DMA request................................................................................................................................265
14.4.12. Temperature sensor, and internal reference voltage VREFINT................................................266
14.4.13. Programmable resolution (DRES) - fast conversion mode ..................................................266
14.4.14. On-chip hardware oversampling ..............................................................................................267

GD32F20x User Manual
9
14.5. ADC sync mode............................................................................................................. 268
14.5.1. Free mode........................................................................................................................................270
14.5.2. Regular parallel mode....................................................................................................................270
14.5.3. Inserted parallel mode ...................................................................................................................271
14.5.4. Follow-up fast mode.......................................................................................................................271
14.5.5. Follow-up slow mode .....................................................................................................................272
14.5.6. Trigger rotation mode.....................................................................................................................273
14.5.7. Combined regular parallel & inserted parallel mode .................................................................274
14.5.8. Combined regular parallel & trigger rotation mode....................................................................274
14.5.9. Combined inserted parallel & follow-up mode............................................................................275
14.6. ADC interrupts.............................................................................................................. 275
14.7. Register definition ........................................................................................................ 276
14.7.1. Status register (ADC_STAT).........................................................................................................276
14.7.2. Control register 0 (ADC_CTL0)....................................................................................................277
14.7.3. Control register 1 (ADC_CTL1)....................................................................................................279
14.7.4. Sample time register 0 (ADC_SAMPT0).....................................................................................281
14.7.5. Sample time register 1 (ADC_SAMPT1).....................................................................................282
14.7.6. Inserted channel data offset register x (ADC_IOFFx) (x=0..3) ................................................283
14.7.7. Watchdog high threshold register (ADC_WDHT) ......................................................................284
14.7.8. Watchdog low threshold register (ADC_WDLT).........................................................................284
14.7.9. Regular sequence register 0 (ADC_RSQ0)................................................................................285
14.7.10. Regular sequence register 1 (ADC_RSQ1)............................................................................285
14.7.11. Regular sequence register 2 (ADC_RSQ2)............................................................................286
14.7.12. Inserted sequence register (ADC_ISQ) ..................................................................................286
14.7.13. Inserted data register x (ADC_IDATAx) (x= 0..3)...................................................................287
14.7.14. Regular data register (ADC_RDATA) ......................................................................................288
14.7.15. Oversample control register (ADC_OVSAMPCTL)...............................................................288
15. Digital-to-analog converter (DAC)...................................................................... 291
15.1. Overview.................................................................................................................... 291
15.2. Characteristics.......................................................................................................... 291
15.3. Function overview.................................................................................................... 292
15.3.1. DAC enable .....................................................................................................................................292
15.3.2. DAC output buffer...........................................................................................................................292
15.3.3. DAC data configuration..................................................................................................................293
15.3.4. DAC trigger......................................................................................................................................293
15.3.5. DAC conversion..............................................................................................................................293
15.3.6. DAC noise wave .............................................................................................................................293
15.3.7. DAC output voltage ........................................................................................................................294
15.3.8. DMA request....................................................................................................................................295
15.3.9. DAC concurrent conversion..........................................................................................................295
15.4. Register definition.................................................................................................... 296
15.4.1. Control register (DAC_CTL)..........................................................................................................296

GD32F20x User Manual
10
15.4.2. Software trigger register (DAC_SWT).........................................................................................298
15.4.3. DAC0 12-bit right-aligned data holding register (DAC0_R12DH)............................................299
15.4.4. DAC0 12-bit left-aligned data holding register (DAC0_L12DH)...............................................299
15.4.5. DAC0 8-bit right-aligned data holding register (DAC0_R8DH)................................................300
15.4.6. DAC1 12-bit right-aligned data holding register (DAC1_R12DH)............................................300
15.4.7. DAC1 12-bit left-aligned data holding register (DAC1_L12DH)...............................................301
15.4.8. DAC1 8-bit right-aligned data holding register (DAC1_R8DH)................................................301
15.4.9. DAC concurrent mode 12-bit right-aligned data holding register (DACC_R12DH) ..............302
15.4.10. DAC concurrent mode 12-bit left-aligned data holding register (DACC_L12DH).............302
15.4.11. DAC concurrent mode 8-bit right-aligned data holding register (DACC_R8DH) ..............303
15.4.12. DAC0 data output register (DAC0_DO) ..................................................................................303
15.4.13. DAC1 data output register (DAC1_DO) ..................................................................................304
16. Watchdog timer (WDGT)...................................................................................... 305
16.1. Free watchdog timer (FWDGT) ...................................................................................... 305
16.1.1. Overview..........................................................................................................................................305
16.1.2. Charateristics...................................................................................................................................305
16.1.3. Function overview...........................................................................................................................305
16.1.4. Register definition...........................................................................................................................308
16.2. Window watchdog timer (WWDGT) .............................................................................. 311
16.2.1. Overview..........................................................................................................................................311
16.2.2. Charateristics...................................................................................................................................311
16.2.3. Function overview...........................................................................................................................311
16.2.4. Register definition...........................................................................................................................314
17. Real-time Clock(RTC)........................................................................................... 316
17.1. Overview...................................................................................................................... 316
17.2. Characteristics.............................................................................................................. 316
17.3. Function overview ........................................................................................................ 316
17.3.1. RTC reset.........................................................................................................................................317
17.3.2. RTC reading ....................................................................................................................................317
17.3.3. RTC configuration...........................................................................................................................318
17.3.4. RTC flag assertion..........................................................................................................................318
17.4. Register definition ........................................................................................................ 320
17.4.1. RTC interrupt enable register(RTC_INTEN)...............................................................................320
17.4.2. RTC control register(RTC_CTL)...................................................................................................320
17.4.3. RTC prescaler high register (RTC_PSCH) .................................................................................321
17.4.4. RTC prescaler low register(RTC_PSCL).....................................................................................322
17.4.5. RTC divider high register (RTC_DIVH) .......................................................................................322
17.4.6. RTC divider low register (RTC_DIVL)..........................................................................................322
17.4.7. RTC counter high register(RTC_CNTH) .....................................................................................323
17.4.8. RTC counter low register (RTC_CNTL).......................................................................................323
17.4.9. RTC alarm high register(RTC_ALRMH)......................................................................................324