GigaDevice Semiconductor GD32F20 Series User manual

GigaDevice Semiconductor Inc.
GD32F20x
ARM®Cortex™-M3 32-bit MCU
User Manual
Revision 2.2
( Oct. 2019 )

GD32F20x User Manual
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Table of Contents
Table of Contents.................................................................................................................... 2
List of Figures ....................................................................................................................... 20
List of Tables......................................................................................................................... 28
1. System and memory architecture ........................................................................... 32
1.1. ARM Cortex-M3 processor.................................................................................................. 32
1.2. System architecture ........................................................................................................... 33
1.3. Memory map ..................................................................................................................... 34
1.3.1. Bit-banding.........................................................................................................................................38
1.3.2. On-chip SRAM memory...................................................................................................................39
1.3.3. On-chip Flash memory.....................................................................................................................39
1.4. Boot configuration ............................................................................................................. 39
1.5. Device electronic signature................................................................................................. 40
1.5.1. Memory size information..................................................................................................................41
1.5.2. Unique device ID (96 bits)...............................................................................................................41
1.6. System configuration registers ............................................................................................ 42
2. Flash memory controller (FMC)............................................................................... 44
2.1. Overview ........................................................................................................................... 44
2.2. Characteristics ................................................................................................................... 44
2.3. Function overview.............................................................................................................. 44
2.3.1. Flash memory architecture..............................................................................................................44
2.3.2. Read operations................................................................................................................................45
2.3.3. Unlock the FMC_CTLx registers ....................................................................................................45
2.3.4. Page erase ........................................................................................................................................46
2.3.5. Mass erase........................................................................................................................................47
2.3.6. Main flash programming..................................................................................................................49
2.3.7. Option bytes Erase...........................................................................................................................50
2.3.8. Option bytes modify..........................................................................................................................51
2.3.9. Option bytes description..................................................................................................................51
2.3.10. Page erase/program protection......................................................................................................53
2.3.11. Security protection............................................................................................................................53
2.4. Register definition.............................................................................................................. 53
2.4.1. Wait state register (FMC_WS)........................................................................................................53
2.4.2. Unlock key register 0(FMC_KEY0)................................................................................................54
2.4.3. Option byte unlock key register (FMC_OBKEY)..........................................................................54
2.4.4. Status register 0 (FMC_STAT0)......................................................................................................55

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2.4.5. Control register 0(FMC_CTL0).......................................................................................................56
2.4.6. Address register 0 (FMC_ADDR0).................................................................................................57
2.4.7. Option byte status register (FMC_OBSTAT).................................................................................57
2.4.8. Erase/Program Protection register (FMC_WP)............................................................................58
2.4.9. Unlock key register 1(FMC_KEY1)................................................................................................58
2.4.10. Status register 1 (FMC_STAT1)......................................................................................................59
2.4.11. Control register 1(FMC_CTL1).......................................................................................................60
2.4.12. Address register 1 (FMC_ADDR1).................................................................................................61
2.4.13. Wait state enable register (FMC_WSEN) .....................................................................................61
2.4.14. Product ID register (FMC_PID) ......................................................................................................62
3. Power management unit (PMU)............................................................................... 63
3.1. Overview ........................................................................................................................... 63
3.2. Characteristics ................................................................................................................... 63
3.3. Function overview.............................................................................................................. 63
3.3.1. Battery backup domain....................................................................................................................64
3.3.2. VDD/VDDA power domain...................................................................................................................65
3.3.3. 1.2V power domain...........................................................................................................................67
3.3.4. Power saving modes........................................................................................................................67
3.4. Register definition.............................................................................................................. 70
3.4.1. Control register (PMU_CTL) ...........................................................................................................70
3.4.2. Control and status register (PMU_CS)..........................................................................................71
4. Backup registers (BKP) ............................................................................................ 73
4.1. Overview ........................................................................................................................... 73
4.2. Characteristics ................................................................................................................... 73
4.3. Function overview.............................................................................................................. 73
4.3.1. RTC clock calibration .......................................................................................................................73
4.3.2. Tamper0 detection............................................................................................................................74
4.3.3. Tamper1 detection............................................................................................................................74
16.1.1. Waveform detection..........................................................................................................................74
4.4. Register definition.............................................................................................................. 75
4.4.1. Backup data register x (BKP_DATAx) (x= 0..41) .........................................................................75
4.4.2. RTC signal output control register (BKP_OCTL).........................................................................75
4.4.3. Tamper pin control register0 (BKP_TPCTL0)...............................................................................76
4.4.4. Tamper control and status register (BKP_TPCS) ........................................................................76
4.4.5. Tamper pin control register1 (BKP_TPCTL1)...............................................................................78
5. Reset and clock unit (RCU) ...................................................................................... 80
5.1. Reset control unit (RCTL) .................................................................................................... 80
5.1.1. Overview............................................................................................................................................80
5.1.2. Function overview.............................................................................................................................80

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5.2. Clock control unit (CCTL)..................................................................................................... 81
5.2.1. Overview............................................................................................................................................81
5.2.2. Characteristics...................................................................................................................................83
5.2.3. Function overview.............................................................................................................................83
5.3. Register definition.............................................................................................................. 88
5.3.1. Control register (RCU_CTL)............................................................................................................88
5.3.2. Configuration register 0 (RCU_CFG0) ..........................................................................................90
5.3.3. Interrupt register (RCU_INT)...........................................................................................................93
5.3.4. APB2 reset register (RCU_APB2RST)..........................................................................................96
5.3.5. APB1 reset register (RCU_APB1RST)..........................................................................................99
5.3.6. AHB1 enable register (RCU_AHB1EN).......................................................................................101
5.3.7. APB2 enable register (RCU_APB2EN).......................................................................................103
5.3.8. APB1 enable register (RCU_APB1EN).......................................................................................106
5.3.9. Backup domain control register (RCU_BDCTL) ........................................................................109
5.3.10. Reset source/clock register (RCU_RSTSCK) ............................................................................110
5.3.11. AHB1 reset register (RCU_AHB1RST).......................................................................................112
5.3.12. Configuration register 1 (RCU_CFG1) ........................................................................................112
5.3.13. Deep-sleep mode voltage register (RCU_DSV) ........................................................................114
5.3.14. AHB2 enable register (RCU_AHB2EN).......................................................................................115
5.3.15. APB2 additional enable register (RCU_ADDAPB2EN).............................................................116
5.3.16. APB1 additional enable register (RCU_ADDAPB1EN).............................................................117
5.3.17. AHB2 reset register (RCU_AHB2RST) .......................................................................................117
5.3.18. APB2 additional reset register (RCU_ADDAPB2RST) .............................................................118
5.3.19. APB1 additional reset register (RCU_ADDAPB1RST) .............................................................119
5.3.20. Configuration register 2 (RCU_ CFG2) .......................................................................................120
5.3.21. PLLT control register (RCU_PLLTCTL).......................................................................................121
5.3.22. PLLT interrupt register (RCU_PLLTINT) .....................................................................................122
5.3.23. PLLT configuration register (RCU_PLLTCFG) ...........................................................................122
6. Interrupt/event controller(EXTI)............................................................................. 125
6.1. Overview ......................................................................................................................... 125
6.2. Characteristics ................................................................................................................. 125
6.3. Interrupts function overview............................................................................................ 125
6.4. External interrupt and event (EXTI) block diagram ............................................................ 129
6.5. External Interrupt and Event function overview................................................................ 129
6.6. Register definition............................................................................................................ 131
6.6.1. Interrupt enable register (EXTI_INTEN)......................................................................................131
6.6.2. Event enable register (EXTI_EVEN)............................................................................................131
6.6.3. Rising edge trigger enable register (EXTI_RTEN).....................................................................132
6.6.4. Falling edge trigger enable register (EXTI_FTEN) ....................................................................132
6.6.5. Software interrupt event register (EXTI_SWIEV).......................................................................132
6.6.6. Pending register (EXTI_PD)..........................................................................................................133

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7. General-purpose and alternate-function I/Os (GPIO and AFIO)........................ 134
7.1. Overview ......................................................................................................................... 134
7.2. Characteristics ................................................................................................................. 134
7.3. Function overview............................................................................................................ 134
7.3.1. GPIO pin configuration...................................................................................................................136
7.3.2. External interrupt/event lines ........................................................................................................136
7.3.3. Alternate functions (AF).................................................................................................................136
7.3.4. Input configuration..........................................................................................................................136
7.3.5. Output configuration.......................................................................................................................137
7.3.6. Analog configuration.......................................................................................................................138
7.3.7. Alternate function (AF) configuration...........................................................................................138
7.3.8. IO pin function selection ................................................................................................................139
7.3.9. GPIO locking function ....................................................................................................................139
7.4. Remapping function I/O and debug configuration............................................................. 140
7.4.1. Introduction......................................................................................................................................140
7.4.2. Main features...................................................................................................................................140
7.4.3. JTAG/SWD alternate function remapping...................................................................................140
7.4.4. ADC AF remapping.........................................................................................................................141
7.4.5. TIMER AF remapping.....................................................................................................................142
7.4.6. USART AF remapping....................................................................................................................144
7.4.7. I2C AF remapping...........................................................................................................................145
7.4.8. SPI AF remapping...........................................................................................................................146
7.4.9. CAN AF remapping.........................................................................................................................146
7.4.10. Ethernet AF remapping..................................................................................................................147
7.4.11. DCI AF remapping..........................................................................................................................148
7.4.12. TLI AF remapping ...........................................................................................................................148
7.4.13. CLK pins AF remapping.................................................................................................................149
7.5. Register definition............................................................................................................ 151
7.5.1. Port control register 0 (GPIOx_CTL0, x=A..I).............................................................................151
7.5.2. Port control register 1 (GPIOx_CTL1, x=A..I).............................................................................153
7.5.3. Port input status register (GPIOx_ISTAT, x=A..I).......................................................................154
7.5.4. Port output control register (GPIOx_OCTL, x=A..I)...................................................................155
7.5.5. Port bit operate register (GPIOx_BOP, x=A..I)...........................................................................155
7.5.6. Port bit clear register (GPIOx_BC, x=A..I) ..................................................................................156
7.5.7. Port configuration lock register (GPIOx_LOCK, x=A..I)............................................................156
7.5.8. Event control register (AFIO_EC).................................................................................................157
7.5.9. AFIO port configuration register 0 (AFIO_PCF0).......................................................................158
7.5.10. EXTI sources selection register 0 (AFIO_EXTISS0).................................................................162
7.5.11. EXTI sources selection register 1 (AFIO_EXTISS1).................................................................163
7.5.12. EXTI sources selection register 2 (AFIO_EXTISS2).................................................................165
7.5.13. EXTI sources selection register 3 (AFIO_EXTISS3).................................................................166
7.5.14. AFIO port configuration register 1 (AFIO_PCF1).......................................................................167

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7.5.15. AFIO port configuration register 2 (AFIO_PCF2).......................................................................169
7.5.16. AFIO port configuration register 3 (AFIO_PCF3).......................................................................171
7.5.17. AFIO port configuration register 4 (AFIO_PCF4).......................................................................175
7.5.18. AFIO port configuration register 5 (AFIO_PCF5).......................................................................178
8. CRC calculation unit (CRC).................................................................................... 183
8.1. Overview ......................................................................................................................... 183
8.2. Characteristics ................................................................................................................. 183
8.3. Function overview............................................................................................................ 184
8.4. Register definition............................................................................................................ 185
8.4.1. Data register (CRC_DATA) ...........................................................................................................185
8.4.2. Free data register (CRC_FDATA) ................................................................................................185
8.4.3. Control register (CRC_CTL)..........................................................................................................186
9. True random number generator (TRNG)............................................................... 187
9.1. Overview ......................................................................................................................... 187
9.2. Characteristics............................................................................................................. 187
9.3. Function overview........................................................................................................ 187
9.3.1. Operation flow.................................................................................................................................188
9.3.2. Error flags ........................................................................................................................................188
9.4. Register definition........................................................................................................ 189
9.4.1. Control register (TRNG_CTL).......................................................................................................189
9.4.2. Status register (TRNG_STAT) ......................................................................................................189
9.4.3. Data register (TRNG_DATA).........................................................................................................190
10. Cryptographic Acceleration Unit (CAU) ............................................................ 192
10.1. Overview...................................................................................................................... 192
10.2. Characteristics.............................................................................................................. 192
10.3. CAU data type and initialization vectors ........................................................................ 193
10.3.1. Data type..........................................................................................................................................193
10.3.2. Initialization vectors........................................................................................................................194
10.4. Cryptographic acceleration processor............................................................................ 194
10.4.1. DES/TDES cryptographic acceleration processor.....................................................................195
10.4.2. AES cryptographic acceleration processor.................................................................................199
10.5. Operating modes.......................................................................................................... 203
10.6. CAU DMA interface....................................................................................................... 204
10.7. CAU interrupts.............................................................................................................. 205
10.8. CAU suspended mode................................................................................................... 205
10.9. Register definition ........................................................................................................ 207
10.9.1. CAU control register (CAU_CTL).................................................................................................207

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10.9.2. CAU Status register 0 (CAU_STAT0) ..........................................................................................208
10.9.3. CAU data input register (CAU_DI) ...............................................................................................209
10.9.4. CAU data output register (CAU_DO)...........................................................................................210
10.9.5. CAU DMA enable register (CAU_DMAEN).................................................................................210
10.9.6. CAU interrupt enable register (CAU_INTEN).............................................................................211
10.9.7. CAU Status register 1 (CAU_STAT1) ..........................................................................................211
10.9.8. CAU interrupt flag register (CAU_INTF)......................................................................................212
10.9.9. CAU key registers (CAU_KEY0..3(H/L)).....................................................................................212
10.9.10. CAU Initial vector registers (CAU_IV0..1(H/L))......................................................................215
11. Hash Acceleration Unit (HAU)............................................................................. 217
11.1. Overview...................................................................................................................... 217
11.2. Characteristics.............................................................................................................. 217
11.3. HAU data type.............................................................................................................. 217
11.4. HAU core...................................................................................................................... 219
11.4.1. Automatic data padding.................................................................................................................219
11.4.2. Digest computing............................................................................................................................220
11.4.3. Hash mode ......................................................................................................................................221
11.4.4. HMAC mode....................................................................................................................................221
11.5. HAU interrupt............................................................................................................... 221
11.6. Register definition ........................................................................................................ 223
11.6.1. HAU control register (HAU_CTL).................................................................................................223
11.6.2. HAU data input register (HAU_DI)...............................................................................................224
11.6.3. HAU configuration register (HAU_CFG) .....................................................................................225
11.6.4. HAU data output register (HAU_DO0..7) ....................................................................................226
11.6.5. HAU interrupt enable register (HAU_INTEN).............................................................................228
11.6.6. HAU status and interrupt flag register (HAU_STAT)..................................................................228
12. Direct memory access controller (DMA) ........................................................... 230
12.1. Overview.................................................................................................................... 230
12.2. Characteristics.......................................................................................................... 230
12.3. Block diagram........................................................................................................... 231
12.4. Function overview.................................................................................................... 231
12.4.1. DMA operation.................................................................................................................................231
12.4.2. Peripheral handshake....................................................................................................................233
12.4.3. Arbitration.........................................................................................................................................234
12.4.4. Address generation ........................................................................................................................234
12.4.5. Circular mode..................................................................................................................................234
12.4.6. Memory to memory mode..............................................................................................................235
12.4.7. Channel configuration....................................................................................................................235
12.4.8. Interrupt............................................................................................................................................235
12.4.9. DMA request mapping ...................................................................................................................236

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12.5. Register definition.................................................................................................... 240
12.5.1. Interrupt flag register (DMA_INTF)...............................................................................................240
12.5.2. Interrupt flag clear register (DMA_INTC) ....................................................................................240
12.5.3. Channel x control register (DMA_CHxCTL)................................................................................241
12.5.4. Channel x counter register (DMA_CHxCNT)..............................................................................243
12.5.5. Channel x peripheral base address register (DMA_CHxPADDR)...........................................244
12.5.6. Channel x memory base address register (DMA_CHxMADDR).............................................244
12.5.7. DMA additional configuration register (DMA_ACFG)................................................................245
13. Debug (DBG) ......................................................................................................... 246
13.1. Overview...................................................................................................................... 246
13.2. JTAG/SW characteristics ............................................................................................... 246
13.2.1. Switch JTAG or SW interface........................................................................................................246
13.2.2. Pin assignment................................................................................................................................246
13.2.3. JTAG daisy chained structure.......................................................................................................247
13.2.4. Debug reset.....................................................................................................................................247
13.2.5. JEDEC-106 ID code.......................................................................................................................247
13.3. Debug hold function overview ...................................................................................... 247
13.3.1. Debug support for power saving mode .......................................................................................247
13.3.2. Debug support for TIMER, I2C, WWDGT, FWDGT and CAN..................................................248
13.4. Register definition ........................................................................................................ 249
13.4.1. ID code register (DBG_ID)............................................................................................................249
13.4.2. Control register (DBG_CTL)..........................................................................................................249
14. Analog-to-digital converter (ADC)...................................................................... 253
14.1. Overview...................................................................................................................... 253
14.2. Characteristics.............................................................................................................. 253
14.3. Pins and internal signals ............................................................................................... 254
14.4. Function overview ........................................................................................................ 255
14.4.1. Calibration (CLB) ............................................................................................................................255
14.4.2. ADC clock........................................................................................................................................256
14.4.3. ADCON switch ................................................................................................................................256
14.4.4. Regular and inserted channel groups..........................................................................................256
14.4.5. Conversion modes..........................................................................................................................256
14.4.6. Inserted channel management.....................................................................................................261
14.4.7. Analog watchdog ............................................................................................................................262
14.4.8. Data alignment................................................................................................................................262
14.4.9. Programmable sample time ..........................................................................................................264
14.4.10. External trigger............................................................................................................................264
14.4.11. DMA request................................................................................................................................265
14.4.12. Temperature sensor, and internal reference voltage VREFINT................................................266
14.4.13. Programmable resolution (DRES) - fast conversion mode ..................................................266
14.4.14. On-chip hardware oversampling ..............................................................................................267

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14.5. ADC sync mode............................................................................................................. 268
14.5.1. Free mode........................................................................................................................................270
14.5.2. Regular parallel mode....................................................................................................................270
14.5.3. Inserted parallel mode ...................................................................................................................271
14.5.4. Follow-up fast mode.......................................................................................................................271
14.5.5. Follow-up slow mode .....................................................................................................................272
14.5.6. Trigger rotation mode.....................................................................................................................273
14.5.7. Combined regular parallel & inserted parallel mode .................................................................274
14.5.8. Combined regular parallel & trigger rotation mode....................................................................274
14.5.9. Combined inserted parallel & follow-up mode............................................................................275
14.6. ADC interrupts.............................................................................................................. 275
14.7. Register definition ........................................................................................................ 276
14.7.1. Status register (ADC_STAT).........................................................................................................276
14.7.2. Control register 0 (ADC_CTL0)....................................................................................................277
14.7.3. Control register 1 (ADC_CTL1)....................................................................................................279
14.7.4. Sample time register 0 (ADC_SAMPT0).....................................................................................281
14.7.5. Sample time register 1 (ADC_SAMPT1).....................................................................................282
14.7.6. Inserted channel data offset register x (ADC_IOFFx) (x=0..3) ................................................283
14.7.7. Watchdog high threshold register (ADC_WDHT) ......................................................................284
14.7.8. Watchdog low threshold register (ADC_WDLT).........................................................................284
14.7.9. Regular sequence register 0 (ADC_RSQ0)................................................................................285
14.7.10. Regular sequence register 1 (ADC_RSQ1)............................................................................285
14.7.11. Regular sequence register 2 (ADC_RSQ2)............................................................................286
14.7.12. Inserted sequence register (ADC_ISQ) ..................................................................................286
14.7.13. Inserted data register x (ADC_IDATAx) (x= 0..3)...................................................................287
14.7.14. Regular data register (ADC_RDATA) ......................................................................................288
14.7.15. Oversample control register (ADC_OVSAMPCTL)...............................................................288
15. Digital-to-analog converter (DAC)...................................................................... 291
15.1. Overview.................................................................................................................... 291
15.2. Characteristics.......................................................................................................... 291
15.3. Function overview.................................................................................................... 292
15.3.1. DAC enable .....................................................................................................................................292
15.3.2. DAC output buffer...........................................................................................................................292
15.3.3. DAC data configuration..................................................................................................................293
15.3.4. DAC trigger......................................................................................................................................293
15.3.5. DAC conversion..............................................................................................................................293
15.3.6. DAC noise wave .............................................................................................................................293
15.3.7. DAC output voltage ........................................................................................................................294
15.3.8. DMA request....................................................................................................................................295
15.3.9. DAC concurrent conversion..........................................................................................................295
15.4. Register definition.................................................................................................... 296
15.4.1. Control register (DAC_CTL)..........................................................................................................296

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15.4.2. Software trigger register (DAC_SWT).........................................................................................298
15.4.3. DAC0 12-bit right-aligned data holding register (DAC0_R12DH)............................................299
15.4.4. DAC0 12-bit left-aligned data holding register (DAC0_L12DH)...............................................299
15.4.5. DAC0 8-bit right-aligned data holding register (DAC0_R8DH)................................................300
15.4.6. DAC1 12-bit right-aligned data holding register (DAC1_R12DH)............................................300
15.4.7. DAC1 12-bit left-aligned data holding register (DAC1_L12DH)...............................................301
15.4.8. DAC1 8-bit right-aligned data holding register (DAC1_R8DH)................................................301
15.4.9. DAC concurrent mode 12-bit right-aligned data holding register (DACC_R12DH) ..............302
15.4.10. DAC concurrent mode 12-bit left-aligned data holding register (DACC_L12DH).............302
15.4.11. DAC concurrent mode 8-bit right-aligned data holding register (DACC_R8DH) ..............303
15.4.12. DAC0 data output register (DAC0_DO) ..................................................................................303
15.4.13. DAC1 data output register (DAC1_DO) ..................................................................................304
16. Watchdog timer (WDGT)...................................................................................... 305
16.1. Free watchdog timer (FWDGT) ...................................................................................... 305
16.1.1. Overview..........................................................................................................................................305
16.1.2. Charateristics...................................................................................................................................305
16.1.3. Function overview...........................................................................................................................305
16.1.4. Register definition...........................................................................................................................308
16.2. Window watchdog timer (WWDGT) .............................................................................. 311
16.2.1. Overview..........................................................................................................................................311
16.2.2. Charateristics...................................................................................................................................311
16.2.3. Function overview...........................................................................................................................311
16.2.4. Register definition...........................................................................................................................314
17. Real-time Clock(RTC)........................................................................................... 316
17.1. Overview...................................................................................................................... 316
17.2. Characteristics.............................................................................................................. 316
17.3. Function overview ........................................................................................................ 316
17.3.1. RTC reset.........................................................................................................................................317
17.3.2. RTC reading ....................................................................................................................................317
17.3.3. RTC configuration...........................................................................................................................318
17.3.4. RTC flag assertion..........................................................................................................................318
17.4. Register definition ........................................................................................................ 320
17.4.1. RTC interrupt enable register(RTC_INTEN)...............................................................................320
17.4.2. RTC control register(RTC_CTL)...................................................................................................320
17.4.3. RTC prescaler high register (RTC_PSCH) .................................................................................321
17.4.4. RTC prescaler low register(RTC_PSCL).....................................................................................322
17.4.5. RTC divider high register (RTC_DIVH) .......................................................................................322
17.4.6. RTC divider low register (RTC_DIVL)..........................................................................................322
17.4.7. RTC counter high register(RTC_CNTH) .....................................................................................323
17.4.8. RTC counter low register (RTC_CNTL).......................................................................................323
17.4.9. RTC alarm high register(RTC_ALRMH)......................................................................................324

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17.4.10. RTC alarm low register (RTC_ALRML)...................................................................................324
18. TIMER..................................................................................................................... 326
18.1. Advanced timer (TIMERx, x=0, 7)................................................................................... 327
18.1.1. Overview..........................................................................................................................................327
18.1.2. Characteristics.................................................................................................................................327
18.1.3. Block diagram..................................................................................................................................328
18.1.4. Function overview...........................................................................................................................330
18.1.5. Register definition...........................................................................................................................359
18.2. General level0 timer (TIMERx, x=1, 2, 3, 4) .................................................................... 386
18.2.1. Overview..........................................................................................................................................386
18.2.2. Characteristics.................................................................................................................................386
18.2.3. Block diagram..................................................................................................................................386
18.2.4. Function overview...........................................................................................................................388
18.2.5. Register definition...........................................................................................................................404
18.3. General level1 timer (TIMERx, x=8, 11).......................................................................... 426
18.3.1. Overview..........................................................................................................................................426
18.3.2. Characteristics.................................................................................................................................426
18.3.3. Block diagram..................................................................................................................................427
18.3.4. Function overview...........................................................................................................................427
18.3.5. Register definition...........................................................................................................................442
18.4. General level2 timer (TIMERx, x=9, 10, 12, 13)............................................................... 455
18.4.1. Overview..........................................................................................................................................455
18.4.2. Characteristics.................................................................................................................................455
18.4.3. Block diagram..................................................................................................................................455
18.4.4. Function overview...........................................................................................................................456
18.4.5. Register definition...........................................................................................................................467
18.5. Basic timer (TIMERx, x=5, 6).......................................................................................... 478
18.5.1. Overview..........................................................................................................................................478
18.5.2. Characteristics.................................................................................................................................478
18.5.3. Block diagram..................................................................................................................................478
18.5.4. Function overview...........................................................................................................................479
18.5.5. Register definition...........................................................................................................................483
19. Universal synchronous/asynchronous receiver /transmitter (USART) ........ 488
19.1. Overview...................................................................................................................... 488
19.2. Characteristics.......................................................................................................... 488
19.3. Function overview ........................................................................................................ 489
19.3.1. USART frame format......................................................................................................................490
19.3.2. Baud rate generation......................................................................................................................491
19.3.3. USART transmitter..........................................................................................................................491
19.3.4. USART receiver..............................................................................................................................492
19.3.5. Use DMA for data buffer access...................................................................................................494

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19.3.6. Hardware flow control ....................................................................................................................495
19.3.7. Multi-processor communication....................................................................................................496
19.3.8. LIN mode..........................................................................................................................................497
19.3.9. Synchronous mode.........................................................................................................................498
19.3.10. IrDA SIR ENDEC mode.............................................................................................................499
19.3.11. Half-duplex communication mode............................................................................................500
19.3.12. Smartcard (ISO7816-3) mode..................................................................................................500
19.3.13. USART interrupts........................................................................................................................502
19.4. Register definition.................................................................................................... 503
19.4.1. Status register 0 (USART_STAT0)...............................................................................................504
19.4.2. Data register (USART_DATA).......................................................................................................506
19.4.3. Baud rate register (USART_BAUD).............................................................................................506
19.4.4. Control register 0 (USART_CTL0) ...............................................................................................507
19.4.5. Control register 1 (USART_CTL1) ...............................................................................................509
19.4.6. Control register 2 (USART_CTL2) ...............................................................................................510
19.4.7. Guard time and prescaler register (USART_GP).......................................................................512
19.4.8. Control register 3 (USART_CTL3) ...............................................................................................513
19.4.9. Receiver timeout register (USART_RT)......................................................................................515
19.4.10. Status register 1 (USART_STAT1)...........................................................................................515
20. Inter-integrated circuit interface (I2C) ............................................................... 517
20.1. Overview...................................................................................................................... 517
20.2. Characteristics.............................................................................................................. 517
20.3. Function overview ........................................................................................................ 517
20.3.1. SDA and SCL lines .........................................................................................................................518
20.3.2. Data validation.................................................................................................................................519
20.3.3. START and STOP condition..........................................................................................................519
20.3.4. Clock synchronization....................................................................................................................519
20.3.5. Arbitration.........................................................................................................................................520
20.3.6. I2C communication flow.................................................................................................................521
20.3.7. Programming model.......................................................................................................................521
20.3.8. Use DMA for data transfer.............................................................................................................531
20.3.9. Packet error checking ....................................................................................................................532
20.3.10. SMBus support ...........................................................................................................................532
20.3.11. Status, errors and interrupts .....................................................................................................534
20.4. Register definition ........................................................................................................ 535
20.4.1. Control register 0 (I2C_CTL0).......................................................................................................535
20.4.2. Control register 1 (I2C_CTL1).......................................................................................................537
20.4.3. Slave address register 0 (I2C_SADDR0)....................................................................................538
20.4.4. Slave address register 1 (I2C_SADDR1)....................................................................................538
20.4.5. Transfer buffer register (I2C_DATA).............................................................................................539
20.4.6. Transfer status register 0 (I2C_STAT0).......................................................................................539
20.4.7. Transfer status register 1 (I2C_STAT1).......................................................................................541

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20.4.8. Clock configure register (I2C_CKCFG).......................................................................................542
20.4.9. Rise time register (I2C_RT)...........................................................................................................543
21. Serial peripheral interface/Inter-IC sound (SPI/I2S)......................................... 544
21.1. Overview...................................................................................................................... 544
21.2. Characteristics.............................................................................................................. 544
21.2.1. SPI characteristics..........................................................................................................................544
21.2.2. I2S characteristics ..........................................................................................................................544
21.3. SPI block diagram ......................................................................................................... 545
21.4. SPI signal description .................................................................................................... 545
21.4.1. Normal configuration (Not Quad-SPI Mode)...............................................................................545
21.4.2. Quad-SPI configuration..................................................................................................................546
21.5. SPI function overview ................................................................................................... 546
21.5.1. SPI clock timing and data format..................................................................................................546
21.5.2. NSS function....................................................................................................................................547
21.5.3. SPI operation modes......................................................................................................................548
21.5.4. DMA function...................................................................................................................................555
21.5.5. CRC function...................................................................................................................................555
21.6. SPI interrupts ............................................................................................................... 555
21.6.1. Status flags......................................................................................................................................555
21.6.2. Error conditions...............................................................................................................................556
21.7. I2S block diagram ......................................................................................................... 557
21.8. I2S signal description .................................................................................................... 557
21.9. I2S function overview ................................................................................................... 558
21.9.1. I2S audio standards .......................................................................................................................558
21.9.2. I2S clock...........................................................................................................................................566
21.9.3. Operation .........................................................................................................................................567
21.9.4. DMA function...................................................................................................................................570
21.10. I2S interrupts................................................................................................................ 570
21.10.1. Status flags..................................................................................................................................570
21.10.2. Error conditions...........................................................................................................................570
21.11. Register definition ........................................................................................................ 572
21.11.1. Control register 0 (SPI_CTL0)..................................................................................................572
21.11.2. Control register 1 (SPI_CTL1)..................................................................................................574
21.11.3. Status register (SPI_STAT).......................................................................................................575
21.11.4. Data register (SPI_DATA)..........................................................................................................576
21.11.5. CRC polynomial register (SPI_CRCPOLY) ............................................................................577
21.11.6. RX CRC register (SPI_RCRC).................................................................................................577
21.11.7. TX CRC register (SPI_TCRC)..................................................................................................578
21.11.8. I2S control register (SPI_I2SCTL) ...........................................................................................578
21.11.9. I2S clock prescaler register (SPI_I2SPSC) ............................................................................580

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21.11.10. Quad-SPI mode control register (SPI_QCTL) of SPI0..........................................................581
22. Digital camera interface(DCI).............................................................................. 582
22.1. Overview...................................................................................................................... 582
22.2. Characteristics.............................................................................................................. 582
22.3. Block diagram............................................................................................................... 582
22.4. Signal description ......................................................................................................... 583
22.5. Function overview ........................................................................................................ 583
22.5.1. DCI hardware synchronization mode...........................................................................................583
22.5.2. Embedded synchronization mode................................................................................................584
22.5.3. Capture data using snapshot or continuous capture modes....................................................584
22.5.4. Window function..............................................................................................................................585
22.5.5. Pixel formats, data padding and DMA.........................................................................................585
22.6. Interrupts..................................................................................................................... 586
22.7. Register definition ........................................................................................................ 587
22.7.1. Control register (DCI_CTL) ...........................................................................................................587
22.7.2. Status register0 (DCI_STAT0) ......................................................................................................588
22.7.3. Status register1 (DCI_STAT1) ......................................................................................................589
22.7.4. Interrupt enable register (DCI_INTEN)........................................................................................589
22.7.5. Interrupt flag register (DCI_INTF).................................................................................................590
22.7.6. Interrupt flag clear register (DCI_INTC) ......................................................................................591
22.7.7. Synchronization codes register (DCI_SC) ..................................................................................591
22.7.8. Synchronization codes unmask register (DCI_SCUMSK)........................................................592
22.7.9. Cropping window start position register (DCI_CWSPOS)........................................................592
22.7.10. Cropping window size register (DCI_CWSZ).........................................................................593
22.7.11. DATA register (DCI_DATA)........................................................................................................593
23. TFT-LCD interface (TLI)........................................................................................ 595
23.1. Overview...................................................................................................................... 595
23.2. Characteristics.............................................................................................................. 595
23.3. Block diagram............................................................................................................... 595
23.4. Signal description ......................................................................................................... 596
23.5. Function overview ........................................................................................................ 596
23.5.1. LCD display timing..........................................................................................................................596
23.5.2. Pixel DMA function .........................................................................................................................597
23.5.3. Pixel formats....................................................................................................................................598
23.5.4. Layer window and blending function............................................................................................598
23.5.5. Layer configuration reload.............................................................................................................599
23.5.6. Dithering function............................................................................................................................600
23.5.7. Interrupt............................................................................................................................................600
23.6. Register definition ........................................................................................................ 601

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23.6.1. Synchronous pulse size register (TLI_SPSZ) ............................................................................601
23.6.2. Back-porch size register (TLI_BPSZ)..........................................................................................601
23.6.3. Active size register (TLI_ASZ)......................................................................................................602
23.6.4. Total size register (TLI_TSZ).........................................................................................................602
23.6.5. Control register (TLI_CTL) ............................................................................................................603
23.6.6. Reload layer register (TLI_RL) .....................................................................................................604
23.6.7. Background color register (TLI_BGC).........................................................................................605
23.6.8. Interrupt enable register (TLI_INTEN).........................................................................................605
23.6.9. Interrupt flag register (TLI_INTF)..................................................................................................606
23.6.10. Interrupt flag clear register (TLI_INTC) ...................................................................................607
23.6.11. Line mark register (TLI_LM)......................................................................................................607
23.6.12. Current pixel position register (TLI_CPPOS) .........................................................................608
23.6.13. Status register (TLI_STAT)........................................................................................................608
23.6.14. Layer x control register (TLI_LxCTL).......................................................................................609
23.6.15. Layer x horizontal position parameters register (TLI_LxHPOS)..........................................610
23.6.16. Layer x vertical position parameters register (TLI_LxVPOS)...............................................610
23.6.17. Layer x color key register (TLI_LxCKEY)................................................................................611
23.6.18. Layer x packeted pixel format register (TLI_LxPPF).............................................................611
23.6.19. Layer x specified alpha register (TLI_LxSA) ..........................................................................612
23.6.20. Layer x default color register (TLI_LxDC)...............................................................................612
23.6.21. Layer x blending register (TLI_LxBLEND)..............................................................................613
23.6.22. Layer x frame base address register (TLI_LxFBADDR).......................................................614
23.6.23. Layer x frame line length register (TLI_LxFLLEN).................................................................614
23.6.24. Layer x frame total line number register (TLI_LxFTLN)........................................................615
23.6.25. Layer x look up table register (TLI_LxLUT)............................................................................615
24. Secure digital input/output interface (SDIO)..................................................... 617
24.1. Overview...................................................................................................................... 617
24.2. Characteristics.............................................................................................................. 617
24.3. SDIO bus topology ........................................................................................................ 617
24.4. SDIO function overview ................................................................................................ 620
24.4.1. SDIO adapter ..................................................................................................................................620
24.4.2. AHB interface ..................................................................................................................................624
24.5. Card function overview................................................................................................. 625
24.5.1. Card registers..................................................................................................................................625
24.5.2. Commands ......................................................................................................................................627
24.5.3. Responses.......................................................................................................................................639
24.5.4. Data packets format.......................................................................................................................642
24.5.5. Two status fields of the card..........................................................................................................644
24.6. Programming sequence ................................................................................................ 651
24.6.1. Card identification...........................................................................................................................651
24.6.2. No data commands ........................................................................................................................653
24.6.3. Single block or multiple block write..............................................................................................653

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24.6.4. Single block or multiple block read...............................................................................................654
24.6.5. Stream write and stream read (MMC only).................................................................................655
24.6.6. Erase ................................................................................................................................................657
24.6.7. Bus width selection.........................................................................................................................658
24.6.8. Protection management.................................................................................................................658
24.6.9. Card Lock/Unlock operation..........................................................................................................659
24.7. Specific operations ....................................................................................................... 661
24.7.1. SD I/O specific operations.............................................................................................................661
24.7.2. CE-ATA specific operations...........................................................................................................664
24.8. Register definition ........................................................................................................ 666
24.8.1. Power control register (SDIO_PWRCTL)....................................................................................666
24.8.2. Clock control register (SDIO_CLKCTL).......................................................................................666
24.8.3. Command argument register (SDIO_CMDAGMT)....................................................................668
24.8.4. Command control register (SDIO_CMDCTL).............................................................................668
24.8.5. Command index response register (SDIO_RSPCMDIDX).......................................................670
24.8.6. Response register (SDIO_RESPx x=0..3)..................................................................................670
24.8.7. Data timeout register (SDIO_DATATO).......................................................................................671
24.8.8. Data length register (SDIO_DATALEN).......................................................................................671
24.8.9. Data control register (SDIO_DATACTL)......................................................................................672
24.8.10. Data counter register (SDIO_DATACNT)................................................................................672
24.8.11. Status register (SDIO_STAT)....................................................................................................674
24.8.12. Interrupt clear register (SDIO_INTC).......................................................................................675
24.8.13. Interrupt enable register (SDIO_INTEN).................................................................................676
24.8.14. FIFO counter register (SDIO_FIFOCNT)................................................................................678
24.8.15. FIFO data register (SDIO_FIFO)..............................................................................................679
25. External memory controller (EXMC).................................................................. 680
25.1. Overview...................................................................................................................... 680
25.2. Characteristics.............................................................................................................. 680
25.3. Function overview ........................................................................................................ 681
25.3.1. Block diagram..................................................................................................................................681
25.3.2. Basic regulation of EXMC access................................................................................................681
25.3.3. External device address mapping................................................................................................682
25.3.4. NOR/PSRAM controller .................................................................................................................686
25.3.5. NAND flash or PC card controller.................................................................................................707
25.3.6. SDRAM controller...........................................................................................................................713
25.4. Register definition ........................................................................................................ 725
25.4.1. NOR/PSRAM controller registers.................................................................................................725
25.4.2. NAND flash/PC card controller registers.....................................................................................729
25.4.3. SDRAM controller registers...........................................................................................................735
25.4.4. SQPI-PSRAM controller registers................................................................................................742
26. Controller area network (CAN) ........................................................................... 747

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26.1. Overview...................................................................................................................... 747
26.2. Characteristics.............................................................................................................. 747
26.3. Function overview ........................................................................................................ 748
26.3.1. Working mode.................................................................................................................................748
26.3.2. Communication modes..................................................................................................................749
26.3.3. Data transmission...........................................................................................................................750
26.3.4. Data reception.................................................................................................................................752
26.3.5. Filtering function..............................................................................................................................753
26.3.6. Time-triggered communication .....................................................................................................756
26.3.7. Communication parameters..........................................................................................................757
26.3.8. Error flags ........................................................................................................................................759
26.3.9. CAN interrupts.................................................................................................................................759
26.4. Register definition ........................................................................................................ 761
26.4.1. Control register (CAN_CTL)..........................................................................................................761
26.4.2. Status register (CAN_STAT) .........................................................................................................762
26.4.3. Transmit status register (CAN_TSTAT).......................................................................................764
26.4.4. Receive message FIFO0 register (CAN_RFIFO0)....................................................................767
26.4.5. Receive message FIFO1 register (CAN_RFIFO1)....................................................................767
26.4.6. Interrupt enable register (CAN_INTEN) ......................................................................................768
26.4.7. Error register (CAN_ERR).............................................................................................................770
26.4.8. Bit timing register (CAN_BT).........................................................................................................771
26.4.9. Transmit mailbox identifier register (CAN_TMIx) (x=0..2) ........................................................772
26.4.10. Transmit mailbox property register (CAN_TMPx) (x=0..2)...................................................772
26.4.11. Transmit mailbox data0 register (CAN_TMDATA0x) (x=0..2)..............................................773
26.4.12. Transmit mailbox data1 register (CAN_TMDATA1x) (x=0..2)..............................................774
26.4.13. Receive FIFO mailbox identifier register (CAN_RFIFOMIx) (x=0,1)...................................774
26.4.14. Receive FIFO mailbox property register (CAN_RFIFOMPx) (x=0,1)..................................775
26.4.15. Receive FIFO mailbox data0 register (CAN_RFIFOMDATA0x) (x=0,1).............................775
26.4.16. Receive FIFO mailbox data1 register (CAN_RFIFOMDATA1x) (x=0,1).............................776
26.4.17. Filter control register (CAN_FCTL)..........................................................................................776
26.4.18. Filter mode configuration register (CAN_FMCFG)................................................................777
26.4.19. Filter scale configuration register (CAN_FSCFG) .................................................................777
26.4.20. Filter associated FIFO register (CAN_FAFIFO).....................................................................778
26.4.21. Filter working register (CAN_FW)............................................................................................778
26.4.22. Filter x data y register (CAN_FxDATAy) (x=0..27, y=0,1).....................................................779
27. Ethernet (ENET).................................................................................................... 780
27.1. Overview.................................................................................................................... 780
27.2. Characteristics.......................................................................................................... 780
27.2.1. Block diagram..................................................................................................................................781
27.2.2. MAC 802.3 Ethernet packet description......................................................................................782
27.2.3. Ethernet signal description............................................................................................................783
27.3. Function overview.................................................................................................... 785

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27.3.1. Interface configuration ...................................................................................................................785
27.3.2. MAC function overview..................................................................................................................789
27.3.3. MAC statistics counters: MSC ......................................................................................................800
27.3.4. Wake up management: WUM.......................................................................................................801
27.3.5. Precision time protocol: PTP.........................................................................................................804
27.3.6. DMA controller description ............................................................................................................808
27.3.7. Example for a typical configuration flow of Ethernet .................................................................828
27.3.8. Ethernet interrupts..........................................................................................................................829
27.4. Register definition.................................................................................................... 832
27.4.1. MAC configuration register (ENET_MAC_CFG)........................................................................832
27.4.2. MAC frame filter register (ENET_MAC_FRMF).........................................................................834
27.4.3. MAC hash list high register (ENET_MAC_HLH)........................................................................836
27.4.4. MAC hash list low register (ENET_MAC_HLL)..........................................................................836
27.4.5. MAC PHY control register (ENET_MAC_PHY_CTL)................................................................837
27.4.6. MAC MII data register (ENET_MAC_PHY_DATA)....................................................................838
27.4.7. MAC flow control register (ENET_MAC_FCTL).........................................................................838
27.4.8. MAC flow control threshold register (ENET_MAC_FCTH).......................................................839
27.4.9. MAC VLAN tag register (ENET_MAC_VLT)...............................................................................840
27.4.10. MAC remote wakeup frame filter register (ENET_MAC_RWFF) ........................................841
27.4.11. MAC wakeup management register (ENET_MAC_WUM)...................................................842
27.4.12. MAC interrupt flag register (ENET_MAC_INTF)....................................................................843
27.4.13. MAC interrupt mask register (ENET_MAC_INTMSK)...........................................................844
27.4.14. MAC address 0 high register (ENET_MAC_ADDR0H) ........................................................844
27.4.15. MAC address 0 low register (ENET_MAC_ADDR0L)...........................................................845
27.4.16. MAC address 1 high register (ENET_MAC_ADDR1H) ........................................................845
27.4.17. MAC address 1 low register (ENET_MAC_ADDR1L)...........................................................846
27.4.18. MAC address 2 high register (ENET_MAC_ADDR2H) ........................................................847
27.4.19. MAC address 2 low register (ENET_MAC_ADDR2L)...........................................................847
27.4.20. MAC address 3 high register (ENET_MAC_ADDR3H) ........................................................848
27.4.21. MAC address 3 low register (ENET_MAC_ADDR3L)...........................................................849
27.4.22. MSC control register (ENET_MSC_CTL) ...............................................................................849
27.4.23. MSC receive interrupt flag register (ENET_MSC_RINTF)...................................................850
27.4.24. MSC transmit interrupt flag register (ENET_MSC_TINTF) ..................................................850
27.4.25. MSC receive interrupt mask register (ENET_MSC_RINTMSK)..........................................851
27.4.26. MSC transmit interrupt mask register (ENET_MSC_TINTMSK).........................................852
27.4.27. MSC transmitted good frames after a single collision counter register
(ENET_MSC_SCCNT) ...................................................................................................................................853
27.4.28. MSC transmitted good frames after more than a single collision counter register
(ENET_MSC_MSCCNT)................................................................................................................................853
27.4.29. MSC transmitted good frames counter register (ENET_MSC_TGFCNT)..........................854
27.4.30. MSC received frames with CRC error counter register (ENET_MSC_RFCECNT)..........854
27.4.31. MSC received frames with alignment error counter register (ENET_MSC_RFAECNT)..854
27.4.32. MSC received good unicast frames counter register (ENET_MSC_RGUFCNT).............855
27.4.33. PTP time stamp control register (ENET_PTP_TSCTL)........................................................855

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27.4.34. PTP subsecond increment register (ENET_PTP_SSINC)...................................................856
27.4.35. PTP time stamp high register (ENET_PTP_TSH).................................................................857
27.4.36. PTP time stamp low register (ENET_PTP_TSL)...................................................................857
27.4.37. PTP time stamp update high register (ENET_PTP_TSUH).................................................858
27.4.38. PTP time stamp update low register (ENET_PTP_TSUL)...................................................858
27.4.39. PTP time stamp addend register (ENET_PTP_TSADDEND) .............................................859
27.4.40. PTP expected time high register (ENET_PTP_ETH)............................................................859
27.4.41. PTP expected time low register (ENET_PTP_ETL)..............................................................860
27.4.42. DMA bus control register (ENET_DMA_BCTL) .....................................................................860
27.4.43. DMA transmit poll enable register (ENET_DMA_TPEN)......................................................862
27.4.44. DMA receive poll enable register (ENET_DMA_RPEN).......................................................862
27.4.45. DMA receive descriptor table address register (ENET_DMA_RDTADDR)........................863
27.4.46. DMA transmit descriptor table address register (ENET_DMA_TDTADDR).......................863
27.4.47. DMA status register (ENET_DMA_STAT)...............................................................................864
27.4.48. DMA control register (ENET_DMA_CTL)................................................................................867
27.4.49. DMA interrupt enable register (ENET_DMA_INTEN) ...........................................................870
27.4.50. DMA missed frame and buffer overflow counter register (ENET_DMA_MFBOCNT) ......872
27.4.51. DMA current transmit descriptor address register (ENET_DMA_CTDADDR) ..................873
27.4.52. DMA current receive descriptor address register (ENET_DMA_CRDADDR)...................873
27.4.53. DMA current transmit buffer address register (ENET_DMA_CTBADDR)..........................874
27.4.54. DMA current receive buffer address register (ENET_DMA_CRBADDR)...........................874
28. Universal serial bus full-speed interface (USBFS) .......................................... 875
28.1. Overview...................................................................................................................... 875
28.2. Characteristics.............................................................................................................. 875
28.3. Block diagram............................................................................................................... 876
28.4. Signal description ......................................................................................................... 876
28.5. Function overview ........................................................................................................ 876
28.5.1. USBFS clocks and working modes..............................................................................................876
28.5.2. USB host function...........................................................................................................................878
28.5.3. USB device function.......................................................................................................................880
28.5.4. OTG function overview ..................................................................................................................881
28.5.5. Data FIFO........................................................................................................................................882
28.5.6. Operation guide...............................................................................................................................884
28.6. Interrupts..................................................................................................................... 889
28.7. Register definition ........................................................................................................ 891
28.7.1. Global control and status registers...............................................................................................891
28.7.2. Host control and status registers..................................................................................................912
28.7.3. Device control and status registers..............................................................................................924
28.7.4. Power and clock control register (USBFS_PWRCLKCTL).......................................................947
29. Revision history.................................................................................................... 949

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List of Figures
Figure 1-1. Cortex™-M3 block diagram........................................................................................................ 33
Figure 1-2. GD32F20x Connectivity line series system architecture...................................................... 34
Figure 2-1. Process of page erase operation .............................................................................................. 47
Figure 2-2. Process of mass erase operation ............................................................................................. 48
Figure 2-3. Process of word program operation ........................................................................................ 50
Figure 3-1. Power supply overview............................................................................................................... 64
Figure 3-2. Waveform of the POR/PDR......................................................................................................... 66
Figure 3-3. Waveform of the LVD threshold ................................................................................................ 66
Figure 5-1. The system reset circuit ............................................................................................................. 81
Figure 5-2. Clock tree ...................................................................................................................................... 82
Figure 5-3. HXTAL clock source .................................................................................................................... 84
Figure 6-1. Block diagram of EXTI .............................................................................................................. 129
Figure 7-1. The basic structure of a standard I/O and five-volt tolerant I/O Port................................ 135
Figure 7-2. Input configuration .................................................................................................................... 137
Figure 7-3. Output configuration................................................................................................................. 137
Figure 7-4. Analog configuration................................................................................................................. 138
Figure 7-5. Alternate function configuration............................................................................................. 139
Figure 8-1. Block diagram of CRC calculation unit.................................................................................. 183
Figure 9-1. TRNG block diagram ................................................................................................................. 187
Figure 10-1. DATAM No swapping and Half-word swapping ................................................................. 193
Figure 10-2. DATAM Byte swapping and Bit swapping........................................................................... 194
Figure 10-3. CAU diagram............................................................................................................................. 195
Figure 10-4. DES/TDES ECB encryption .................................................................................................... 196
Figure 10-5. DES/TDES ECB decryption .................................................................................................... 197
Figure 10-6. DES/TDES CBC encryption.................................................................................................... 198
Figure 10-7. DES/TDES CBC decryption.................................................................................................... 199
Figure 10-8. AES ECB encryption ............................................................................................................... 200
Figure 10-9. AES ECB decryption ............................................................................................................... 200
Figure 10-10. AES CBC encryption............................................................................................................. 201
Figure 10-11. AES CBC decryption............................................................................................................. 202
Figure 10-12. Counter block structure........................................................................................................ 202
Figure 10-13. AES CTR encryption/decryption......................................................................................... 202
Figure 11-1. DATAM No swapping and Half-word swapping ................................................................. 218
Figure 11-2. DATAM Byte swapping and Bit swapping........................................................................... 218
Figure 11-3. HAU block diagram.................................................................................................................. 219
Figure 12-1. Block diagram of DMA............................................................................................................ 231
Figure 12-2. Handshake mechanism .......................................................................................................... 234
Figure 12-3. DMA interrupt logic ................................................................................................................. 236
Figure 12-4. DMA0 request mapping .......................................................................................................... 237
Figure 12-5. DMA1 request mapping .......................................................................................................... 238
Figure 14-1. ADC module block diagram................................................................................................... 255