GigaDevice Semiconductor GD32F3x0 User manual

GigaDevice Semiconductor Inc.
GD32F3x0
Arm®Cortex®-M4 32-bit MCU
User Manual
Revision 2.6
(Jun. 2022)

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Table of Contents
Table of Contents...........................................................................................................2
List of Figures ..............................................................................................................15
List of Table..................................................................................................................21
1. System and memory architecture ........................................................................23
1.1. Arm®Cortex®-M4 processor......................................................................................... 23
1.2. System architecture....................................................................................................... 24
1.3. Memory map................................................................................................................... 25
1.3.1. Bit-banding............................................................................................................................ 28
1.3.2. On-chip SRAM memory........................................................................................................ 28
1.3.3. On-chip Flash memory ......................................................................................................... 29
1.4. Boot configuration......................................................................................................... 29
1.5. I / O compensation cell.................................................................................................. 30
1.6. System configuration registers (SYSCFG)................................................................. 31
1.6.1. System configuration register 0 (SYSCFG_CFG0) .............................................................. 31
1.6.2. EXTI sources selection register 0 (SYSCFG_EXTISS0)...................................................... 32
1.6.3. EXTI sources selection register 1 (SYSCFG_EXTISS1)...................................................... 33
1.6.4. EXTI sources selection register 2 (SYSCFG_EXTISS2)...................................................... 34
1.6.5. EXTI sources selection register 3 (SYSCFG_EXTISS3)...................................................... 36
1.6.6. System configuration register 2 (SYSCFG_CFG2) .............................................................. 37
1.6.7. I / O compensation control register (SYSCFG_CPSCTL).................................................... 38
1.7. Device electronic signature.......................................................................................... 39
1.7.1. Memory density information.................................................................................................. 39
1.7.2. Unique device ID (96 bits) .................................................................................................... 39
2. Flash memory controller (FMC)............................................................................41
2.1. Overview ......................................................................................................................... 41
2.2. Characteristics............................................................................................................... 41
2.3. Function overview.......................................................................................................... 41
2.3.1. Flash memory architecture ................................................................................................... 41
2.3.2. Read operations ................................................................................................................... 42
2.3.3. Unlock the FMC_CTL register .............................................................................................. 42
2.3.4. Page erase............................................................................................................................ 42
2.3.5. Mass erase ........................................................................................................................... 43
2.3.6. Main flash programming ....................................................................................................... 45
2.3.7. Option byte erase ................................................................................................................. 46
2.3.8. Option byte programming ..................................................................................................... 47

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2.3.9. Option byte description......................................................................................................... 47
2.3.10. Page erase/Program protection............................................................................................ 48
2.3.11. Security protection................................................................................................................ 49
2.4. Register definition.......................................................................................................... 50
2.4.1. Wait state register (FMC_WS).............................................................................................. 50
2.4.2. Unlock key register (FMC_KEY)........................................................................................... 50
2.4.3. Option byte unlock key register (FMC_OBKEY)................................................................... 51
2.4.4. Status register (FMC_STAT)................................................................................................. 51
2.4.5. Control register (FMC_CTL)................................................................................................. 52
2.4.6. Address register (FMC_ADDR) ............................................................................................ 53
2.4.7. Option byte status register (FMC_OBSTAT)......................................................................... 54
2.4.8. Write protection register (FMC_WP)..................................................................................... 54
2.4.9. Wait state enable register (FMC_WSEN)............................................................................. 55
2.4.10. Product ID register (FMC_PID)............................................................................................. 55
3. Power management unit (PMU)............................................................................57
3.1. Overview ......................................................................................................................... 57
3.2. Characteristics............................................................................................................... 57
3.3. Function overview.......................................................................................................... 57
3.3.1. Backup domain..................................................................................................................... 58
3.3.2. VDD / VDDA power domain...................................................................................................... 59
3.3.3. 1.2V power domain............................................................................................................... 61
3.3.4. Power saving modes ............................................................................................................ 61
3.4. Register definition.......................................................................................................... 65
3.4.1. Control register (PMU_CTL)................................................................................................. 65
3.4.2. Control and status register (PMU_CS)................................................................................. 67
4. Reset and clock unit (RCU)...................................................................................70
4.1. Reset control unit (RCTL) ............................................................................................. 70
4.1.1. Overview............................................................................................................................... 70
4.1.2. Function overview................................................................................................................. 70
4.2. Clock control unit (CCTL) ............................................................................................. 71
4.2.1. Overview............................................................................................................................... 71
4.2.2. Characteristics...................................................................................................................... 73
4.2.3. Function overview................................................................................................................. 73
4.3. Register definition.......................................................................................................... 78
4.3.1. Control register0 (RCU_CTL0)............................................................................................. 78
4.3.2. Configuration register 0 (RCU_CFG0) ................................................................................. 79
4.3.3. Interrupt register (RCU_INT) ................................................................................................ 83
4.3.4. APB2 reset register (RCU_APB2RST)................................................................................. 86
4.3.5. APB1 reset register (RCU_APB1RST)................................................................................. 87
4.3.6. AHB enable register (RCU_AHBEN).................................................................................... 89

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4.3.7. APB2 enable register (RCU_APB2EN) ................................................................................ 91
4.3.8. APB1 enable register (RCU_APB1EN) ................................................................................ 92
4.3.9. Backup domain control register (RCU_BDCTL)................................................................... 94
4.3.10. Reset source /clock register (RCU_RSTSCK) ..................................................................... 96
4.3.11. AHB reset register (RCU_AHBRST)..................................................................................... 97
4.3.12. Configuration register 1 (RCU_CFG1) ................................................................................. 99
4.3.13. Configuration register 2 (RCU_CFG2) ............................................................................... 100
4.3.14. Control register 1 (RCU_CTL1).......................................................................................... 101
4.3.15. Additional clock control register (RCU_ADDCTL) .............................................................. 101
4.3.16. Additional clock interrupt register (RCU_ADDINT)............................................................. 102
4.3.17. APB1 additional enable register (RCU_ADDAPB1EN)...................................................... 103
4.3.18. APB1 additional reset register (RCU_ADDAPB1RST)....................................................... 104
4.3.19. Voltage key register (RCU_VKEY) ..................................................................................... 104
4.3.20. Deep-sleep mode voltage register (RCU_DSV)................................................................. 105
5. Clock trim controller (CTC).................................................................................106
5.1. Overview ....................................................................................................................... 106
5.2. Characteristics............................................................................................................. 106
5.3. Function overview........................................................................................................ 106
5.3.1. REF sync pulse generator .................................................................................................. 107
5.3.2. CTC trim counter................................................................................................................. 107
5.3.3. Frequency evaluation and automatically trim process........................................................ 108
5.3.4. Software program guide ..................................................................................................... 109
5.4. Register definition........................................................................................................ 110
5.4.1. Control register 0 (CTC_CTL0)............................................................................................110
5.4.2. Control register 1 (CTC_CTL1)............................................................................................111
5.4.3. Status register (CTC_STAT)................................................................................................112
5.4.4. Interrupt clear register (CTC_INTC) ....................................................................................114
6. Interrupt/event controller (EXTI)......................................................................... 116
6.1. Overview ....................................................................................................................... 116
6.2. Characteristics............................................................................................................. 116
6.3. Interrupts function overview ...................................................................................... 116
6.4. External interrupt and event (EXTI) block diagram.................................................. 119
6.5. External interrupt and Event function overview ...................................................... 119
6.6. Register definition........................................................................................................ 121
6.6.1. Interrupt enable register (EXTI_INTEN) ............................................................................. 121
6.6.2. Event enable register (EXTI_EVEN) .................................................................................. 121
6.6.3. Rising edge trigger enable register (EXTI_RTEN) ............................................................. 122
6.6.4. Falling edge trigger enable register (EXTI_FTEN)............................................................. 122
6.6.5. Software interrupt event register (EXTI_SWIEV) ............................................................... 123

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6.6.6. Pending register (EXTI_PD) ............................................................................................... 123
7. General-purpose and alternate-function I/Os (GPIO)........................................125
7.1. Overview ....................................................................................................................... 125
7.2. Characteristics............................................................................................................. 125
7.3. Function overview........................................................................................................ 125
7.3.1. GPIO pin configuration ....................................................................................................... 126
7.3.2. Alternate functions (AF)...................................................................................................... 127
7.3.3. Additional functions............................................................................................................. 127
7.3.4. Input configuration .............................................................................................................. 127
7.3.5. Output configuration ........................................................................................................... 128
7.3.6. Analog configuration........................................................................................................... 128
7.3.7. Alternate function (AF) configuration.................................................................................. 129
7.3.8. GPIO locking function......................................................................................................... 130
7.3.9. GPIO single cycle toggle function....................................................................................... 130
7.3.10. GPIO very high speed drive capability ............................................................................... 130
7.4. Register definition........................................................................................................ 131
7.4.1. Port control register (GPIOx_CTL, x=A..D,F)..................................................................... 131
7.4.2. Port output mode register (GPIOx_OMODE, x=A..D,F)..................................................... 132
7.4.3. Port output speed register 0 (GPIOx_OSPD0, x=A..D,F)................................................... 134
7.4.4. Port pull-up/down register (GPIOx_PUD, x=A..D,F)........................................................... 136
7.4.5. Port input status register (GPIOx_ISTAT, x=A..D,F)........................................................... 137
7.4.6. Port output control register (GPIOx_OCTL, x=A..D,F) ....................................................... 138
7.4.7. Port bit operate register (GPIOx_BOP, x=A..D,F)............................................................... 138
7.4.8. Port configuration lock register (GPIOx_LOCK, x=A,B) ..................................................... 139
7.4.9. Alternate function selected register 0 (GPIOx_AFSEL0, x=A,B,C).................................... 140
7.4.10. Alternate function selected register 1 (GPIOx_AFSEL1, x=A,B,C).................................... 141
7.4.11. Bit clear register (GPIOx_BC, x=A..D,F) ............................................................................ 142
7.4.12. Port bit toggle register (GPIOx_TG, x=A..D,F)................................................................... 142
7.4.13. Port output speed register 1 (GPIOx_OSPD1, x=A..D,F)................................................... 143
8. Cyclic redundancy checks management unit (CRC) ........................................144
8.1. Overview ....................................................................................................................... 144
8.2. Characteristics............................................................................................................. 144
8.3. Function overview........................................................................................................ 145
8.4. Register definition........................................................................................................ 146
8.4.1. Data register (CRC_DATA)................................................................................................. 146
8.4.2. Free data register (CRC_FDATA)....................................................................................... 146
8.4.3. Control register (CRC_CTL)............................................................................................... 147
8.4.4. Initialization data register (CRC_IDATA)............................................................................. 147
8.4.5. Polynomial register (CRC_POLY)....................................................................................... 148

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9. Direct memory access controller (DMA)............................................................149
9.1. Overview ....................................................................................................................... 149
9.2. Characteristics............................................................................................................. 149
9.3. Block diagram .............................................................................................................. 150
9.4. Function overview........................................................................................................ 150
9.4.1. DMA operation.................................................................................................................... 150
9.4.2. Peripheral handshake......................................................................................................... 152
9.4.3. Arbitration............................................................................................................................ 152
9.4.4. Address generation............................................................................................................. 153
9.4.5. Circular mode...................................................................................................................... 153
9.4.6. Memory to memory mode................................................................................................... 153
9.4.7. Channel configuration......................................................................................................... 153
9.4.8. Interrupt............................................................................................................................... 154
9.4.9. DMA request mapping ........................................................................................................ 155
9.5. Register definition........................................................................................................ 158
9.5.1. Interrupt flag register (DMA_INTF)..................................................................................... 158
9.5.2. Interrupt flag clear register (DMA_INTC)............................................................................ 158
9.5.3. Channel x control register (DMA_CHxCTL) ....................................................................... 159
9.5.4. Channel x counter register (DMA_CHxCNT)...................................................................... 161
9.5.5. Channel x peripheral base address register (DMA_CHxPADDR)...................................... 162
9.5.6. Channel x memory base address register (DMA_CHxMADDR)........................................ 162
10. Debug (DBG).....................................................................................................164
10.1. Overview.................................................................................................................... 164
10.2. Serial Wire Debug port overview............................................................................ 164
10.2.1. Pin assignment ................................................................................................................... 164
10.2.2. JEDEC-106 ID code ........................................................................................................... 164
10.3. Debug hold function overview................................................................................ 165
10.3.1. Debug support for power saving mode............................................................................... 165
10.3.2. Debug support for TIMER, I2C, RTC, WWDGT and FWDGT............................................ 165
10.4. Register definition.................................................................................................... 166
10.4.1. ID code register (DBG_ID).................................................................................................. 166
10.4.2. Control register 0 (DBG_CTL0).......................................................................................... 166
10.4.3. Control register 1 (DBG_CTL1).......................................................................................... 168
11. Analog to digital converter (ADC) ...................................................................170
11.1. Overview.................................................................................................................... 170
11.2. Characteristics.......................................................................................................... 170
11.3. Pins and internal signals......................................................................................... 171
11.4. Function overview.................................................................................................... 172

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11.4.1. Foreground calibration function.......................................................................................... 172
11.4.2. Dual clock domain architecture........................................................................................... 173
11.4.3. ADCON enable................................................................................................................... 173
11.4.4. Routine sequence............................................................................................................... 173
11.4.5. Operation modes ................................................................................................................ 173
11.4.6. Conversion result threshold monitor function..................................................................... 176
11.4.7. Data storage mode ............................................................................................................. 176
11.4.8. Sample time configuration.................................................................................................. 177
11.4.9. External trigger configuration.............................................................................................. 178
11.4.10. DMA request ....................................................................................................................... 178
11.4.11. ADC internal channels........................................................................................................ 178
11.4.12. ADC interrupts .................................................................................................................... 179
11.4.13. Programmable resolution (DRES)...................................................................................... 179
11.4.14. On-chip hardware oversampling......................................................................................... 180
11.5. Register definition.................................................................................................... 183
11.5.1. Status register (ADC_STAT)............................................................................................... 183
11.5.2. Control register 0 (ADC_CTL0) .......................................................................................... 183
11.5.3. Control register 1 (ADC_CTL1) .......................................................................................... 185
11.5.4. Sampling time register 0 (ADC_SAMPT0) ......................................................................... 187
11.5.5. Sampling time register 1 (ADC_SAMPT1) ......................................................................... 187
11.5.6. Watchdog high threshold register (ADC_WDHT)............................................................... 188
11.5.7. Watchdog low threshold register (ADC_WDLT) ................................................................. 189
11.5.8. Routine sequence register0(ADC_RSQ0).......................................................................... 189
11.5.9. Routine sequence register1(ADC_RSQ1).......................................................................... 190
11.5.10. Routine sequence register 2 (ADC_RSQ2)........................................................................ 190
11.5.11. Routine data register (ADC_RDATA).................................................................................. 191
11.5.12. Oversampling control register (ADC_OVSAMPCTL) ......................................................... 191
12. Digital-to-analog converter (DAC)...................................................................194
12.1. Overview.................................................................................................................... 194
12.2. Characteristic............................................................................................................ 194
12.3. Function overview.................................................................................................... 195
12.3.1. DAC enable......................................................................................................................... 195
12.3.2. DAC output buffer............................................................................................................... 195
12.3.3. DAC data configuration....................................................................................................... 195
12.3.4. DAC trigger......................................................................................................................... 195
12.3.5. DAC workflow ..................................................................................................................... 196
12.3.6. DAC noise wave ................................................................................................................. 196
12.3.7. DAC output calculate.......................................................................................................... 197
12.3.8. DMA function....................................................................................................................... 197
12.4. Registers definition.................................................................................................. 198
12.4.1. Control register (DAC_CTL) ............................................................................................... 198

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12.4.2. Software trigger register (DAC_SWT) ................................................................................ 199
12.4.3. DAC 12-bit right-aligned data holding register(DAC_R12DH)............................................ 200
12.4.4. DAC 12-bit left-aligned data holding register(DAC_L12DH) .............................................. 200
12.4.5. DAC 8-bit right-aligned data holding register (DAC_R8DH)............................................... 201
12.4.6. DAC data output register (DAC_DO).................................................................................. 201
12.4.7. DAC Status register (DAC_STAT)...................................................................................... 201
13. Comparator (CMP)............................................................................................203
13.1. Overview.................................................................................................................... 203
13.2. Characteristic............................................................................................................ 203
13.3. Function overview.................................................................................................... 203
13.3.1. CMP clock and reset........................................................................................................... 204
13.3.2. CMP I/O configure .............................................................................................................. 204
13.3.3. CMP operating mode.......................................................................................................... 205
13.3.4. CMP hysteresis................................................................................................................... 205
13.3.5. CMP register write protection ............................................................................................. 205
13.4. CMP registers............................................................................................................ 206
13.4.1. Control/status register (CMP_CS)...................................................................................... 206
14. Watchdog timer (WDGT) ..................................................................................210
14.1. Free watchdog timer (FWDGT) ............................................................................... 210
14.1.1. Overview............................................................................................................................. 210
14.1.2. Characteristics.................................................................................................................... 210
14.1.3. Function overview............................................................................................................... 210
14.1.4. Register definition............................................................................................................... 213
14.2. Window watchdog timer (WWDGT)........................................................................ 217
14.2.1. Overview............................................................................................................................. 217
14.2.2. Characteristics.................................................................................................................... 217
14.2.3. Function overview............................................................................................................... 217
14.2.4. Register definition............................................................................................................... 220
15. Real-time clock (RTC).......................................................................................222
15.1. Overview.................................................................................................................... 222
15.2. Characteristics.......................................................................................................... 222
15.3. Function overview.................................................................................................... 223
15.3.1. Block diagram..................................................................................................................... 223
15.3.2. Clock source and prescalers .............................................................................................. 223
15.3.3. Shadow registers introduction ............................................................................................ 224
15.3.4. Configurable and field maskable alarm .............................................................................. 224
15.3.5. RTC initialization and configuration .................................................................................... 225
15.3.6. Calendar reading ................................................................................................................ 226
15.3.7. Resetting the RTC .............................................................................................................. 227

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15.3.8. RTC shift function ............................................................................................................... 227
15.3.9. RTC reference clock detection ........................................................................................... 228
15.3.10. RTC smooth digital calibration............................................................................................ 229
15.3.11. Time-stamp function ........................................................................................................... 231
15.3.12. Tamper detection ................................................................................................................ 231
15.3.13. Calibration clock output ...................................................................................................... 232
15.3.14. Alarm output........................................................................................................................ 232
15.3.15. RTC power saving mode management.............................................................................. 233
15.3.16. RTC interrupts..................................................................................................................... 233
15.4. Register definition.................................................................................................... 234
15.4.1. Time register (RTC_TIME).................................................................................................. 234
15.4.2. Date register (RTC_DATE)................................................................................................. 234
15.4.3. Control register (RTC_CTL)................................................................................................ 235
15.4.4. Status register (RTC_STAT) ............................................................................................... 237
15.4.5. Prescaler register (RTC_PSC) ........................................................................................... 239
15.4.6. Alarm 0 time and date register (RTC_ALRM0TD).............................................................. 239
15.4.7. Write protection key register (RTC_WPK).......................................................................... 241
15.4.8. Sub second register (RTC_SS) .......................................................................................... 241
15.4.9. Shift function control register (RTC_SHIFTCTL)................................................................ 241
15.4.10. Time of time stamp register (RTC_TTS)............................................................................. 242
15.4.11. Date of time stamp register (RTC_DTS)............................................................................. 243
15.4.12. Sub second of time stamp register (RTC_SSTS)............................................................... 243
15.4.13. High resolution frequency compensation register (RTC_HRFC) ....................................... 244
15.4.14. Tamper register (RTC_TAMP) ............................................................................................ 245
15.4.15. Alarm 0 sub second register (RTC_ALRM0SS) ................................................................. 247
15.4.16. Backup registers (RTC_BKPx) (x = 0..4)............................................................................ 248
16. Timer (TIMERx) .................................................................................................250
16.1. Advanced timer (TIMERx ,x=0)................................................................................ 251
16.1.1. Overview............................................................................................................................. 251
16.1.2. Characteristics.................................................................................................................... 251
16.1.3. Block diagram..................................................................................................................... 252
16.1.4. Function overview............................................................................................................... 253
16.1.5. Register definition............................................................................................................... 279
16.2. General level0 timer (TIMERx, x=1, 2).................................................................... 306
16.2.1. Overview............................................................................................................................. 306
16.2.2. Characteristics.................................................................................................................... 306
16.2.3. Block diagram..................................................................................................................... 307
16.2.4. Function overview............................................................................................................... 308
16.2.5. Register definition............................................................................................................... 323
16.3. General level2 timer (TIMERx, x=13)...................................................................... 348
16.3.1. Overview............................................................................................................................. 348
16.3.2. Characteristics.................................................................................................................... 348

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16.3.3. Block diagram..................................................................................................................... 348
16.3.4. Function overview............................................................................................................... 349
16.3.5. Register definition............................................................................................................... 356
16.4. General level3 timer (TIMERx, x=14)...................................................................... 366
16.4.1. Overview............................................................................................................................. 366
16.4.2. Characteristics.................................................................................................................... 366
16.4.3. Block diagram..................................................................................................................... 367
16.4.4. Function overview............................................................................................................... 368
16.4.5. Register definition............................................................................................................... 383
16.5. General level4 timer (TIMERx, x=15,16)................................................................. 403
16.5.1. Overview............................................................................................................................. 403
16.5.2. Characteristics.................................................................................................................... 403
16.5.3. Block diagram..................................................................................................................... 404
16.5.4. Function overview............................................................................................................... 405
16.5.5. Register definition............................................................................................................... 418
16.6. Basic timer (TIMERx, x=5) ....................................................................................... 434
16.6.1. Overview............................................................................................................................. 434
16.6.2. Characteristics.................................................................................................................... 434
16.6.3. Block diagram..................................................................................................................... 434
16.6.4. Function overview............................................................................................................... 434
16.6.5. Register definition............................................................................................................... 439
17. Infrared ray port (IFRP) ....................................................................................444
17.1. Overview.................................................................................................................... 444
17.2. Characteristics.......................................................................................................... 444
17.3. Function overview.................................................................................................... 444
18. Universal synchronous / asynchronous receiver / transmitter (USART).....446
18.1. Overview.................................................................................................................... 446
18.2. Characteristics.......................................................................................................... 446
18.3. Function overview.................................................................................................... 448
18.3.1. USART frame format .......................................................................................................... 448
18.3.2. Baud rate generation .......................................................................................................... 449
18.3.3. USART transmitter.............................................................................................................. 450
18.3.4. USART receiver.................................................................................................................. 451
18.3.5. Use DMA for data buffer access......................................................................................... 452
18.3.6. Hardware flow control......................................................................................................... 454
18.3.7. Multi-processor communication.......................................................................................... 455
18.3.8. LIN mode ............................................................................................................................ 456
18.3.9. Synchronous mode............................................................................................................. 457
18.3.10. IrDA SIR ENDEC mode ...................................................................................................... 458
18.3.11. Half-duplex communication mode ...................................................................................... 459

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18.3.12. Smartcard (ISO7816-3) mode ............................................................................................ 459
18.3.13. ModBus communication ..................................................................................................... 461
18.3.14. Receive FIFO...................................................................................................................... 462
18.3.15. Wakeup from deep-sleep mode.......................................................................................... 462
18.3.16. USART interrupts................................................................................................................ 463
18.4. Register definition.................................................................................................... 465
18.4.1. Control register 0 (USART_CTL0)...................................................................................... 465
18.4.2. Control register 1 (USART_CTL1)...................................................................................... 467
18.4.3. Control register 2 (USART_CTL2)...................................................................................... 470
18.4.4. Baud rate generator register (USART_BAUD)................................................................... 472
18.4.5. Prescaler and guard time configuration register (USART_GP).......................................... 473
18.4.6. Receiver timeout register (USART_RT) ............................................................................. 474
18.4.7. Command register (USART_CMD) .................................................................................... 475
18.4.8. Status register (USART_STAT) .......................................................................................... 475
18.4.9. Interrupt status clear register (USART_INTC).................................................................... 479
18.4.10. Receive data register (USART_RDATA) ............................................................................ 480
18.4.11. Transmit data register (USART_TDATA)............................................................................ 481
18.4.12. USART receive FIFO control and status register (USART_RFCS).................................... 481
19. Inter-integrated circuit interface (I2C).............................................................483
19.1. Overview.................................................................................................................... 483
19.2. Characteristics.......................................................................................................... 483
19.3. Function overview.................................................................................................... 483
19.3.1. SDA and SCL lines ............................................................................................................. 484
19.3.2. Data validation.................................................................................................................... 485
19.3.3. START and STOP signal .................................................................................................... 485
19.3.4. Clock synchronization......................................................................................................... 485
19.3.5. Arbitration............................................................................................................................ 486
19.3.6. I2C communication flow...................................................................................................... 486
19.3.7. Programming model ........................................................................................................... 487
19.3.8. SCL line stretching.............................................................................................................. 496
19.3.9. Use DMA for data transfer .................................................................................................. 497
19.3.10. Packet error checking......................................................................................................... 497
19.3.11. SMBus support ................................................................................................................... 497
19.3.12. Status, errors and interrupts............................................................................................... 499
19.4. Register definition.................................................................................................... 501
19.4.1. Control register 0 (I2C_CTL0) ............................................................................................ 501
19.4.2. Control register 1 (I2C_CTL1) ............................................................................................ 503
19.4.3. Slave address register 0 (I2C_SADDR0) ........................................................................... 504
19.4.4. Slave address register 1 (I2C_SADDR1) ........................................................................... 504
19.4.5. Transfer buffer register (I2C_DATA) ................................................................................... 505
19.4.6. Transfer status register 0 (I2C_STAT0).............................................................................. 505

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19.4.7. Transfer status register 1 (I2C_STAT1).............................................................................. 508
19.4.8. Clock configure register (I2C_CKCFG) .............................................................................. 509
19.4.9. Rise time register (I2C_RT)................................................................................................ 510
19.4.10. Fast-mode-plus configure register(I2C_FMPCFG)............................................................. 510
20. Serial peripheral interface/Inter-IC sound (SPI/I2S).......................................512
20.1. Overview.................................................................................................................... 512
20.2. Characteristics.......................................................................................................... 512
20.2.1. SPI characteristics.............................................................................................................. 512
20.2.2. I2S characteristics .............................................................................................................. 512
20.3. SPI function overview.............................................................................................. 513
20.3.1. SPI block diagram............................................................................................................... 513
20.3.2. SPI signal description ......................................................................................................... 513
20.3.3. SPI clock timing and data format........................................................................................ 514
20.3.4. NSS function....................................................................................................................... 515
20.3.5. SPI operation modes .......................................................................................................... 516
20.3.6. DMA function....................................................................................................................... 525
20.3.7. CRC function....................................................................................................................... 525
20.3.8. SPI interrupts...................................................................................................................... 526
20.4. I2S function overview............................................................................................... 527
20.4.1. I2S block diagram............................................................................................................... 527
20.4.2. I2S signal description.......................................................................................................... 528
20.4.3. I2S audio standards............................................................................................................ 528
20.4.4. I2S clock ............................................................................................................................. 536
20.4.5. Operation............................................................................................................................ 537
20.4.6. DMA function....................................................................................................................... 541
20.4.7. I2S interrupts....................................................................................................................... 541
20.5. Register definition.................................................................................................... 543
20.5.1. Control register 0 (SPI_CTL0)............................................................................................ 543
20.5.2. Control register 1 (SPI_CTL1)............................................................................................ 545
20.5.3. Status register (SPI_STAT)................................................................................................. 546
20.5.4. Data register (SPI_DATA)................................................................................................... 547
20.5.5. CRC polynomial register (SPI_CRCPOLY) ........................................................................ 548
20.5.6. RX CRC register (SPI_RCRC) ........................................................................................... 548
20.5.7. TX CRC register (SPI_TCRC) ............................................................................................ 549
20.5.8. I I2S control register (SPI_I2SCTL).................................................................................... 550
20.5.9. I2S clock prescaler register (SPI_I2SPSC) ........................................................................ 551
20.5.10. Quad-SPI mode control register (SPI_QCTL) of SPI1 ....................................................... 552
21. HDMI-CEC controller (HDMI-CEC)...................................................................554
21.1. Overview.................................................................................................................... 554
21.2. Characteristics.......................................................................................................... 554

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21.3. Function overview.................................................................................................... 554
21.3.1. CEC bus pin........................................................................................................................ 554
21.3.2. Message description........................................................................................................... 555
21.3.3. Bit timing description........................................................................................................... 556
21.3.4. Arbitration............................................................................................................................ 557
21.3.5. SFT option bit description................................................................................................... 558
21.3.6. Error definition..................................................................................................................... 558
21.3.7. HDMI-CEC interrupt............................................................................................................ 561
21.4. Register definition.................................................................................................... 563
21.4.1. Control register (CEC_CTL) ............................................................................................... 563
21.4.2. Configuration register (CEC_CFG)..................................................................................... 564
21.4.3. Transmit data register (CEC_TDATA)................................................................................. 565
21.4.4. Receive data register (CEC_RDATA)................................................................................. 566
21.4.5. Interrupt Flag Register (CEC_INTF)................................................................................... 566
21.4.6. Interrupt enable register (CEC_INTEN).............................................................................. 568
22. Touch sensing interface (TSI)..........................................................................571
22.1. Overview.................................................................................................................... 571
22.2. Characteristics.......................................................................................................... 571
22.3. Function Overview ................................................................................................... 571
22.3.1. TSI block diagram............................................................................................................... 571
22.3.2. Touch sensing technique overview..................................................................................... 571
22.3.3. Charge transfer sequence .................................................................................................. 572
22.3.4. Charge transfer sequence FSM.......................................................................................... 574
22.3.5. Clock and duration time of states ....................................................................................... 576
22.3.6. PIN mode control of TSI ..................................................................................................... 577
22.3.7. Analog switch (ASW) and I/O hysteresis mode.................................................................. 577
22.3.8. TSI operation flow............................................................................................................... 578
22.3.9. TSI flags and interrupts....................................................................................................... 578
22.3.10. TSI GPIOs........................................................................................................................... 578
22.4. Registers definition.................................................................................................. 580
22.4.1. Control register0 (TSI_CTL0) ............................................................................................. 580
22.4.2. Interrupt enable register(TSI_INTEN)................................................................................. 582
22.4.3. Interrupt flag clear register (TSI_INTC) .............................................................................. 583
22.4.4. Interrupt flag register (TSI_INTF)........................................................................................ 583
22.4.5. Pin hysteresis mode register(TSI_PHM) ............................................................................ 584
22.4.6. Analog switch register(TSI_ASW) ...................................................................................... 584
22.4.7. Sample configuration register(TSI_SAMPCFG)................................................................. 585
22.4.8. Channel configuration register(TSI_CHCFG)..................................................................... 585
22.4.9. Group control register(TSI_GCTL) ..................................................................................... 586
22.4.10. Group x cycle number registers(TSI_GxCYCN)(x= 0..5) ................................................... 587
22.4.11. Control register1 (TSI_CTL1) ............................................................................................. 587

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23. Universal serial bus full-speed interface (USBFS).........................................589
23.1. Overview.................................................................................................................... 589
23.2. Characteristics.......................................................................................................... 589
23.3. Block diagram........................................................................................................... 590
23.4. Signal description .................................................................................................... 590
23.5. Function overview.................................................................................................... 590
23.5.1. USBFS clocks and working modes..................................................................................... 590
23.5.2. USB host function............................................................................................................... 592
23.5.3. USB device function ........................................................................................................... 594
23.5.4. OTG function overview ....................................................................................................... 595
23.5.5. Data FIFO........................................................................................................................... 596
23.5.6. Operation guide .................................................................................................................. 599
23.6. Interrupts................................................................................................................... 603
23.7. Register definition.................................................................................................... 605
23.7.1. Global control and status registers ..................................................................................... 605
23.7.2. Host control and status registers........................................................................................ 626
23.7.3. Device control and status registers .................................................................................... 637
23.7.4. Power and clock control register (USBFS_PWRCLKCTL)................................................. 661
24. Revision history................................................................................................663

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List of Figures
Figure 1-1. The structure of the Cortex®-M4 processor................................................................ 24
Figure 1-2. Series system architecture of GD32F3x0 series....................................................... 25
Figure 2-1. Process of page erase operation.................................................................................. 43
Figure 2-2. Process of the mass erase operation .......................................................................... 44
Figure 2-3. Process of the word programming operation............................................................ 46
Figure 3-1. Power supply overview.................................................................................................... 58
Figure 3-2. Waveform of the POR / PDR........................................................................................... 60
Figure 3-3. Waveform of the LVD threshold.................................................................................... 60
Figure 4-1. The system reset circuit.................................................................................................. 71
Figure 4-2. Clock tree ............................................................................................................................ 72
Figure 4-3. HXTAL clock source ......................................................................................................... 73
Figure 4-4. HXTAL clock source in bypass mode.......................................................................... 74
Figure 5-1. CTC overview ................................................................................................................... 107
Figure 5-2. CTC trim counter............................................................................................................. 108
Figure 6-1. Block diagram of EXTI ................................................................................................... 119
Figure 7-1. Basic structure of of a general-pupose I/O............................................................... 126
Figure 7-2. Basic structure of Input configuration....................................................................... 128
Figure 7-3. Basic structure of Output configuration ................................................................... 128
Figure 7-4. Basic structure of Analog configuration................................................................... 129
Figure 7-5. Basic structure of Alternate function configuration.............................................. 129
Figure 8-1. Block diagram of CRC calculation unit ..................................................................... 144
Figure 9-1. Block diagram of DMA................................................................................................... 150
Figure 9-2. Handshake mechanism ................................................................................................. 152
Figure 9-3. DMA interrupt logic......................................................................................................... 154
Figure 9-4. DMA request mapping.................................................................................................... 156
Figure 11-1. ADC module block diagram........................................................................................ 172
Figure 11-2. Single operation mode................................................................................................. 173
Figure 11-3. Continuous operation mode ...................................................................................... 174
Figure 11-4. Scan operation mode, continuous disable............................................................. 175
Figure 11-5. Scan operation mode, continuous enable.............................................................. 175
Figure 11-6. Discontinuous operation mode................................................................................. 176
Figure 11-7. Data storage mode of 12-bit resolution................................................................... 177
Figure 11-8. Data storage mode of 10-bit resolution................................................................... 177
Figure 11-9. Data storage mode of 8-bit resolution..................................................................... 177
Figure 11-10. Data storage mode of 6-bit resolution................................................................... 177
Figure 11-11. 20-bit to 16-bit result truncation.............................................................................. 180
Figure 11-12. Numerical example with 5-bits shift and rounding ............................................ 181
Figure 12-1. DAC block diagram....................................................................................................... 194
Figure 12-2. DAC LFSR algorithm.................................................................................................... 196
Figure 12-3. DAC triangle noise wave............................................................................................. 197

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Figure 13-1. CMP block diagram of GD32F3x0 series................................................................. 204
Figure 13-2. CMP hysteresis.............................................................................................................. 205
Figure 14-1. Free watchdog timer block diagram......................................................................... 211
Figure 14-2. Window watchdog timer block diagram.................................................................. 217
Figure 14-3. Window watchdog timer timing diagram................................................................ 218
Figure 15-1. Block diagram of RTC.................................................................................................. 223
Figure 16-1. Advanced timer block diagram.................................................................................. 252
Figure 16-2. Timing chart of internal clock divided by 1............................................................ 253
Figure 16-3. Timing chart of PSC value change from 0 to 2...................................................... 254
Figure 16-4. Timing chart of up counting mode, PSC=0/2......................................................... 255
Figure 16-5. Timing chart of up counting mode, change TIMERx_CAR on the go.............. 256
Figure 16-6. Timing chart of down counting mode, PSC=0/2 ................................................... 257
Figure 16-7. Timing chart of down counting mode, change TIMERx_CAR on the go........ 257
Figure 16-8. Timing chart of center-aligned counting mode..................................................... 259
Figure 16-9. Repetition counter timing chart of center-aligned counting mode.................. 260
Figure 16-10. Repetition counter timing chart of up counting mode...................................... 260
Figure 16-11. Repetition counter timing chart of down counting mode................................. 261
Figure 16-12. Channel input capture principle.............................................................................. 262
Figure 16-13. Output-compare under three modes ..................................................................... 264
Figure 16-14. EAPWM timechart....................................................................................................... 265
Figure 16-15. CAPWM timechart....................................................................................................... 265
Figure 16-16. Complementary output with dead-time insertion............................................... 268
Figure 16-17. Output behavior in response to a break(The break high active).................... 269
Figure 16-18. Counter behavior with CI0FE0 polarity non-inverted in mode 2 .................... 270
Figure 16-19. Counter behavior with CI0FE0 polarity inverted in mode 2............................. 270
Figure 16-20. Hall sensor is used to BLDC motor........................................................................ 271
Figure 16-21. Hall sensor timing between two timers................................................................. 272
Figure 16-22. Restart mode................................................................................................................ 273
Figure 16-23. Pause mode.................................................................................................................. 273
Figure 16-24. Event mode................................................................................................................... 274
Figure 16-25. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99............................... 275
Figure 16-26. TIMER0 Master/Slave mode timer example.......................................................... 275
Figure 16-27. Triggering TIMER0 with enable signal of TIMER1.............................................. 276
Figure 16-28. Triggering TIMER0 and TIMER1 with TIMER1’s CI0 input ................................ 277
Figure 16-29. General Level 0 timer block diagram..................................................................... 307
Figure 16-30. Timing chart of internal clock divided by 1.......................................................... 308
Figure 16-31. Timing chart of PSC value change from 0 to 2.................................................... 309
Figure 16-32. Timing chart of up counting mode, PSC=0/2....................................................... 310
Figure 16-33. Timing chart of up counting mode, change TIMERx_CAR on the go........... 311
Figure 16-34. Timing chart of down counting mode, PSC=0/2................................................. 312
Figure 16-35. Timing chart of down counting mode, change TIMERx_CAR on the go...... 312
Figure 16-36. Center-aligned counter timechart........................................................................... 314
Figure 16-37. Channels input capture principle ........................................................................... 315
Figure 16-38. Output-compare under three modes ..................................................................... 317

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Figure 16-39. EAPWM timechart....................................................................................................... 318
Figure 16-40. CAPWM timechart....................................................................................................... 318
Figure 16-41. Restart mode................................................................................................................ 320
Figure 16-42. Pause mode.................................................................................................................. 320
Figure 16-43. Event mode................................................................................................................... 320
Figure 16-44. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99............................... 322
Figure 16-45. General level2 timer block diagram ....................................................................... 348
Figure 16-46. Timing chart of internal clock divided by 1.......................................................... 349
Figure 16-47. Timing chart of PSC value change from 0 to 2.................................................... 350
Figure 16-48. Timing chart of up counting mode, PSC=0/2....................................................... 351
Figure 16-49. Timing chart of up counting mode, change TIMERx_CAR on the go ........... 351
Figure 16-50. Channel input capture principle.............................................................................. 352
Figure 16-51. Output-compare under three modes ..................................................................... 354
Figure 16-52. PWM mode timechart................................................................................................. 355
Figure 16-53. General level3 timer block diagram ....................................................................... 367
Figure 16-54. Timing chart of internal clock divided by 1.......................................................... 368
Figure 16-55. Timing chart of PSC value change from 0 to 2.................................................... 369
Figure 16-56. Timing chart of up counting mode, PSC=0/2....................................................... 370
Figure 16-57. Timing chart of up counting mode, change TIMERx_CAR on the go ........... 371
Figure 16-58. Repetition counter timing chart of up counting mode...................................... 372
Figure 16-59. Channel input capture principle.............................................................................. 373
Figure 16-60. Output-compare under three modes ..................................................................... 375
Figure 16-61. PWM mode timechart................................................................................................. 376
Figure 16-62. Complementary output with dead-time insertion............................................... 378
Figure 16-63. Output behavior in response to a break(The break high active).................... 379
Figure 16-64. Restart mode................................................................................................................ 380
Figure 16-65. Pause mode.................................................................................................................. 380
Figure 16-66. Event mode................................................................................................................... 381
Figure 16-67. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99............................... 382
Figure 16-68. General level4 timer block diagram ....................................................................... 404
Figure 16-69. Timing chart of internal clock divided by 1.......................................................... 405
Figure 16-70. Timing chart of PSC value change from 0 to 2.................................................... 406
Figure 16-71. Timing chart of up counting mode, PSC=0/2....................................................... 407
Figure 16-72. Timing chart of up counting mode, change TIMERx_CAR on the go ........... 408
Figure 16-73. Repetition counter timing chart of up counting mode...................................... 409
Figure 16-74. Channel input capture principle.............................................................................. 410
Figure 16-75. Output-compare under three modes ..................................................................... 412
Figure 16-76. PWM mode timechart................................................................................................. 413
Figure 16-77. Complementary output with dead-time insertion............................................... 415
Figure 16-78. Output behavior in response to a break (The break high active)................... 416
Figure 16-79. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60.................... 417
Figure 16-80. Basic timer block diagram........................................................................................ 434
Figure 16-81. Timing chart of internal clock divided by 1.......................................................... 435
Figure 16-82. Timing chart of PSC value change from 0 to 2.................................................... 436

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Figure 16-83. Timing chart of up counting mode, PSC=0/2....................................................... 437
Figure 16-84. Timing chart of up counting mode, change TIMERx_CAR on the go ........... 437
Figure 17-1. IFRP output timechart 1............................................................................................... 444
Figure 17-2. IFRP output timechart 2............................................................................................... 445
Figure 17-3. IFRP output timechart 3............................................................................................... 445
Figure 18-1. USART module block diagram................................................................................... 448
Figure 18-2. USART character frame (8 bits data and 1 stop bit) ............................................ 449
Figure 18-3. USART transmit procedure ........................................................................................ 451
Figure 18-4. Oversampling method of a receive frame bit (OSB=0)........................................ 452
Figure 18-5. Configuration step when using DMA for USART transmission........................ 453
Figure 18-6. Configuration step when using DMA for USART reception............................... 454
Figure 18-7. Hardware flow control between two USARTs........................................................ 454
Figure 18-8. Hardware flow control.................................................................................................. 455
Figure 18-9. Break frame occurs during idle state....................................................................... 456
Figure 18-10. Break frame occurs during a frame ....................................................................... 457
Figure 18-11. Example of USART in synchronous mode........................................................... 457
Figure 18-12. 8-bit format USART synchronous waveform (CLEN=1).................................... 458
Figure 18-13. IrDA SIR ENDEC module........................................................................................... 458
Figure 18-14. IrDA data modulation................................................................................................. 459
Figure 18-15. ISO7816-3 frame format............................................................................................. 460
Figure 18-16. USART receive FIFO structure................................................................................ 462
Figure 18-17. USART interrupt mapping diagram........................................................................ 464
Figure 19-1. I2C module block diagram.......................................................................................... 484
Figure 19-2. Data validation............................................................................................................... 485
Figure 19-3. START and STOP signal.............................................................................................. 485
Figure 19-4. Clock synchronization................................................................................................. 486
Figure 19-5. SDA line arbitration....................................................................................................... 486
Figure 19-6. I2C communication flow with 7-bit address........................................................... 487
Figure 19-7. I2C communication flow with 10-bit address (Master Transmit) ...................... 487
Figure 19-8. I2C communication flow with 10-bit address (Master Receive)........................ 487
Figure 19-9. Programming model for slave transmitting (10-bit address mode)................. 489
Figure 19-10. Programming model for slave receiving (10-bit address mode).................... 490
Figure 19-11. Programming model for master transmitting (10-bit address mode)............ 492
Figure 19-12. Programming model for master receiving using Solution A (10-bit address
mode)............................................................................................................................................... 494
Figure 19-13. Programming model for master receiving mode using solution B (10-bit
address mode)............................................................................................................................... 496
Figure 20-1. Block diagram of SPI.................................................................................................... 513
Figure 20-2. SPI timing diagram in normal mode......................................................................... 514
Figure 20-3. SPI timing diagram in Quad-SPI mode (CKPL=1, CKPH=1, LF=0) ................... 515
Figure 20-4. A typical full-duplex connection ............................................................................... 517
Figure 20-5. A typical simplex connection (Master: receive, Slave: transmit)..................... 518
Figure 20-6. A typical simplex connection (Master: transmit only, Slave: receive)............ 518
Figure 20-7. A typical bidirectional connection............................................................................ 518

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Figure 20-8. Timing diagram of TI master mode with discontinuous transfer..................... 520
Figure 20-9. Timing diagram of TI master mode with continuous transfer........................... 520
Figure 20-10. Timing diagram of TI slave mode ........................................................................... 521
Figure 20-11. Timing diagram of NSS pulse with continuous transmit.................................. 522
Figure 20-12. Timing diagram of write operation in Quad-SPI mode...................................... 523
Figure 20-13. Timing diagram of read operation in Quad-SPI mode....................................... 524
Figure 20-14. Block diagram of I2S.................................................................................................. 527
Figure 20-15. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0)....... 528
Figure 20-16. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1)....... 529
Figure 20-17. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0)....... 529
Figure 20-18. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1)....... 529
Figure 20-19. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0)....... 529
Figure 20-20. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1)....... 529
Figure 20-21. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0)....... 530
Figure 20-22. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1)....... 530
Figure 20-23. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0)... 530
Figure 20-24. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1)... 530
Figure 20-25. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0)... 531
Figure 20-26. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1)... 531
Figure 20-27. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0)... 531
Figure 20-28. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1)... 531
Figure 20-29. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0)... 531
Figure 20-30. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1)... 531
Figure 20-31. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0).... 532
Figure 20-32. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1).... 532
Figure 20-33. LSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0).... 532
Figure 20-34. LSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1).... 532
Figure 20-35. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=0, CKPL=0)...................................................................................................................... 533
Figure 20-36. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=0, CKPL=1)...................................................................................................................... 533
Figure 20-37. PCM standard short frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=0)...................................................................................................................... 533
Figure 20-38. PCM standard short frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=1)...................................................................................................................... 533
Figure 20-39. PCM standard short frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=0)...................................................................................................................... 534
Figure20-40. PCM standard short frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=1)...................................................................................................................... 534
Figure 20-41. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=0)...................................................................................................................... 534
Figure 20-42. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=1)...................................................................................................................... 534
Figure 20-43. PCM standard long frame synchronization mode timing diagram (DTLEN=00,

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CHLEN=0, CKPL=0)...................................................................................................................... 534
Figure20-44. PCM standard long frame synchronization mode timing diagram (DTLEN=00,
CHLEN=0, CKPL=1)...................................................................................................................... 535
Figure 20-45. PCM standard long frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=0)...................................................................................................................... 535
Figure 20-46. PCM standard long frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=1)...................................................................................................................... 535
Figure 20-47. PCM standard long frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=0)...................................................................................................................... 535
Figure 20-48. PCM standard long frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=1)...................................................................................................................... 535
Figure 20-49. PCM standard long frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=0)...................................................................................................................... 536
Figure 20-50. PCM standard long frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=1)...................................................................................................................... 536
Figure 20-51. Block diagram of I2S clock generator................................................................... 536
Figure 20-52. I2S initialization sequence........................................................................................ 538
Figure 20-53. I2S master reception disabling sequence............................................................ 540
Figure 21-1. HDMI-CEC Controller Block Diagram....................................................................... 555
Figure 21-2. Start bit ............................................................................................................................ 556
Figure 21-3. Valid data bit................................................................................................................... 556
Figure 21-4. Signal Free Time............................................................................................................ 557
Figure 21-5. Error Bit Period.............................................................................................................. 558
Figure 21-6. Bit period long error..................................................................................................... 559
Figure 21-7. Transmission error detection .................................................................................... 560
Figure 22-1. Block diagram of TSI module..................................................................................... 571
Figure 22-2. Block diagram of Sample pin and Channel Pin..................................................... 572
Figure 22-3. Voltage of a sample pin during charge-transfer sequence................................ 574
Figure 22-4. FSM flow of a charge-transfer sequence................................................................ 575
Figure 23-1. USBFS block diagram.................................................................................................. 590
Figure 23-2. Connection with host or device mode..................................................................... 591
Figure 23-3. Connection with OTG mode....................................................................................... 592
Figure 23-4. State transition diagram of host port....................................................................... 592
Figure 23-5. HOST mode FIFO space in SRAM............................................................................. 597
Figure 23-6. Host mode FIFO access register map ..................................................................... 597
Figure 23-7. Device mode FIFO space in SRAM........................................................................... 598
Figure 23-8. Device mode FIFO access register map ................................................................. 599