GigaDevice Semiconductor GD32F3x0 User manual

GigaDevice Semiconductor Inc.
GD32F3x0
Arm®Cortex®-M4 32-bit MCU
User Manual
Revision 2.6
(Jun. 2022)

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Table of Contents
Table of Contents...........................................................................................................2
List of Figures ..............................................................................................................15
List of Table..................................................................................................................21
1. System and memory architecture ........................................................................23
1.1. Arm®Cortex®-M4 processor......................................................................................... 23
1.2. System architecture....................................................................................................... 24
1.3. Memory map................................................................................................................... 25
1.3.1. Bit-banding............................................................................................................................ 28
1.3.2. On-chip SRAM memory........................................................................................................ 28
1.3.3. On-chip Flash memory ......................................................................................................... 29
1.4. Boot configuration......................................................................................................... 29
1.5. I / O compensation cell.................................................................................................. 30
1.6. System configuration registers (SYSCFG)................................................................. 31
1.6.1. System configuration register 0 (SYSCFG_CFG0) .............................................................. 31
1.6.2. EXTI sources selection register 0 (SYSCFG_EXTISS0)...................................................... 32
1.6.3. EXTI sources selection register 1 (SYSCFG_EXTISS1)...................................................... 33
1.6.4. EXTI sources selection register 2 (SYSCFG_EXTISS2)...................................................... 34
1.6.5. EXTI sources selection register 3 (SYSCFG_EXTISS3)...................................................... 36
1.6.6. System configuration register 2 (SYSCFG_CFG2) .............................................................. 37
1.6.7. I / O compensation control register (SYSCFG_CPSCTL).................................................... 38
1.7. Device electronic signature.......................................................................................... 39
1.7.1. Memory density information.................................................................................................. 39
1.7.2. Unique device ID (96 bits) .................................................................................................... 39
2. Flash memory controller (FMC)............................................................................41
2.1. Overview ......................................................................................................................... 41
2.2. Characteristics............................................................................................................... 41
2.3. Function overview.......................................................................................................... 41
2.3.1. Flash memory architecture ................................................................................................... 41
2.3.2. Read operations ................................................................................................................... 42
2.3.3. Unlock the FMC_CTL register .............................................................................................. 42
2.3.4. Page erase............................................................................................................................ 42
2.3.5. Mass erase ........................................................................................................................... 43
2.3.6. Main flash programming ....................................................................................................... 45
2.3.7. Option byte erase ................................................................................................................. 46
2.3.8. Option byte programming ..................................................................................................... 47

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2.3.9. Option byte description......................................................................................................... 47
2.3.10. Page erase/Program protection............................................................................................ 48
2.3.11. Security protection................................................................................................................ 49
2.4. Register definition.......................................................................................................... 50
2.4.1. Wait state register (FMC_WS).............................................................................................. 50
2.4.2. Unlock key register (FMC_KEY)........................................................................................... 50
2.4.3. Option byte unlock key register (FMC_OBKEY)................................................................... 51
2.4.4. Status register (FMC_STAT)................................................................................................. 51
2.4.5. Control register (FMC_CTL)................................................................................................. 52
2.4.6. Address register (FMC_ADDR) ............................................................................................ 53
2.4.7. Option byte status register (FMC_OBSTAT)......................................................................... 54
2.4.8. Write protection register (FMC_WP)..................................................................................... 54
2.4.9. Wait state enable register (FMC_WSEN)............................................................................. 55
2.4.10. Product ID register (FMC_PID)............................................................................................. 55
3. Power management unit (PMU)............................................................................57
3.1. Overview ......................................................................................................................... 57
3.2. Characteristics............................................................................................................... 57
3.3. Function overview.......................................................................................................... 57
3.3.1. Backup domain..................................................................................................................... 58
3.3.2. VDD / VDDA power domain...................................................................................................... 59
3.3.3. 1.2V power domain............................................................................................................... 61
3.3.4. Power saving modes ............................................................................................................ 61
3.4. Register definition.......................................................................................................... 65
3.4.1. Control register (PMU_CTL)................................................................................................. 65
3.4.2. Control and status register (PMU_CS)................................................................................. 67
4. Reset and clock unit (RCU)...................................................................................70
4.1. Reset control unit (RCTL) ............................................................................................. 70
4.1.1. Overview............................................................................................................................... 70
4.1.2. Function overview................................................................................................................. 70
4.2. Clock control unit (CCTL) ............................................................................................. 71
4.2.1. Overview............................................................................................................................... 71
4.2.2. Characteristics...................................................................................................................... 73
4.2.3. Function overview................................................................................................................. 73
4.3. Register definition.......................................................................................................... 78
4.3.1. Control register0 (RCU_CTL0)............................................................................................. 78
4.3.2. Configuration register 0 (RCU_CFG0) ................................................................................. 79
4.3.3. Interrupt register (RCU_INT) ................................................................................................ 83
4.3.4. APB2 reset register (RCU_APB2RST)................................................................................. 86
4.3.5. APB1 reset register (RCU_APB1RST)................................................................................. 87
4.3.6. AHB enable register (RCU_AHBEN).................................................................................... 89

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4.3.7. APB2 enable register (RCU_APB2EN) ................................................................................ 91
4.3.8. APB1 enable register (RCU_APB1EN) ................................................................................ 92
4.3.9. Backup domain control register (RCU_BDCTL)................................................................... 94
4.3.10. Reset source /clock register (RCU_RSTSCK) ..................................................................... 96
4.3.11. AHB reset register (RCU_AHBRST)..................................................................................... 97
4.3.12. Configuration register 1 (RCU_CFG1) ................................................................................. 99
4.3.13. Configuration register 2 (RCU_CFG2) ............................................................................... 100
4.3.14. Control register 1 (RCU_CTL1).......................................................................................... 101
4.3.15. Additional clock control register (RCU_ADDCTL) .............................................................. 101
4.3.16. Additional clock interrupt register (RCU_ADDINT)............................................................. 102
4.3.17. APB1 additional enable register (RCU_ADDAPB1EN)...................................................... 103
4.3.18. APB1 additional reset register (RCU_ADDAPB1RST)....................................................... 104
4.3.19. Voltage key register (RCU_VKEY) ..................................................................................... 104
4.3.20. Deep-sleep mode voltage register (RCU_DSV)................................................................. 105
5. Clock trim controller (CTC).................................................................................106
5.1. Overview ....................................................................................................................... 106
5.2. Characteristics............................................................................................................. 106
5.3. Function overview........................................................................................................ 106
5.3.1. REF sync pulse generator .................................................................................................. 107
5.3.2. CTC trim counter................................................................................................................. 107
5.3.3. Frequency evaluation and automatically trim process........................................................ 108
5.3.4. Software program guide ..................................................................................................... 109
5.4. Register definition........................................................................................................ 110
5.4.1. Control register 0 (CTC_CTL0)............................................................................................110
5.4.2. Control register 1 (CTC_CTL1)............................................................................................111
5.4.3. Status register (CTC_STAT)................................................................................................112
5.4.4. Interrupt clear register (CTC_INTC) ....................................................................................114
6. Interrupt/event controller (EXTI)......................................................................... 116
6.1. Overview ....................................................................................................................... 116
6.2. Characteristics............................................................................................................. 116
6.3. Interrupts function overview ...................................................................................... 116
6.4. External interrupt and event (EXTI) block diagram.................................................. 119
6.5. External interrupt and Event function overview ...................................................... 119
6.6. Register definition........................................................................................................ 121
6.6.1. Interrupt enable register (EXTI_INTEN) ............................................................................. 121
6.6.2. Event enable register (EXTI_EVEN) .................................................................................. 121
6.6.3. Rising edge trigger enable register (EXTI_RTEN) ............................................................. 122
6.6.4. Falling edge trigger enable register (EXTI_FTEN)............................................................. 122
6.6.5. Software interrupt event register (EXTI_SWIEV) ............................................................... 123

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6.6.6. Pending register (EXTI_PD) ............................................................................................... 123
7. General-purpose and alternate-function I/Os (GPIO)........................................125
7.1. Overview ....................................................................................................................... 125
7.2. Characteristics............................................................................................................. 125
7.3. Function overview........................................................................................................ 125
7.3.1. GPIO pin configuration ....................................................................................................... 126
7.3.2. Alternate functions (AF)...................................................................................................... 127
7.3.3. Additional functions............................................................................................................. 127
7.3.4. Input configuration .............................................................................................................. 127
7.3.5. Output configuration ........................................................................................................... 128
7.3.6. Analog configuration........................................................................................................... 128
7.3.7. Alternate function (AF) configuration.................................................................................. 129
7.3.8. GPIO locking function......................................................................................................... 130
7.3.9. GPIO single cycle toggle function....................................................................................... 130
7.3.10. GPIO very high speed drive capability ............................................................................... 130
7.4. Register definition........................................................................................................ 131
7.4.1. Port control register (GPIOx_CTL, x=A..D,F)..................................................................... 131
7.4.2. Port output mode register (GPIOx_OMODE, x=A..D,F)..................................................... 132
7.4.3. Port output speed register 0 (GPIOx_OSPD0, x=A..D,F)................................................... 134
7.4.4. Port pull-up/down register (GPIOx_PUD, x=A..D,F)........................................................... 136
7.4.5. Port input status register (GPIOx_ISTAT, x=A..D,F)........................................................... 137
7.4.6. Port output control register (GPIOx_OCTL, x=A..D,F) ....................................................... 138
7.4.7. Port bit operate register (GPIOx_BOP, x=A..D,F)............................................................... 138
7.4.8. Port configuration lock register (GPIOx_LOCK, x=A,B) ..................................................... 139
7.4.9. Alternate function selected register 0 (GPIOx_AFSEL0, x=A,B,C).................................... 140
7.4.10. Alternate function selected register 1 (GPIOx_AFSEL1, x=A,B,C).................................... 141
7.4.11. Bit clear register (GPIOx_BC, x=A..D,F) ............................................................................ 142
7.4.12. Port bit toggle register (GPIOx_TG, x=A..D,F)................................................................... 142
7.4.13. Port output speed register 1 (GPIOx_OSPD1, x=A..D,F)................................................... 143
8. Cyclic redundancy checks management unit (CRC) ........................................144
8.1. Overview ....................................................................................................................... 144
8.2. Characteristics............................................................................................................. 144
8.3. Function overview........................................................................................................ 145
8.4. Register definition........................................................................................................ 146
8.4.1. Data register (CRC_DATA)................................................................................................. 146
8.4.2. Free data register (CRC_FDATA)....................................................................................... 146
8.4.3. Control register (CRC_CTL)............................................................................................... 147
8.4.4. Initialization data register (CRC_IDATA)............................................................................. 147
8.4.5. Polynomial register (CRC_POLY)....................................................................................... 148

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9. Direct memory access controller (DMA)............................................................149
9.1. Overview ....................................................................................................................... 149
9.2. Characteristics............................................................................................................. 149
9.3. Block diagram .............................................................................................................. 150
9.4. Function overview........................................................................................................ 150
9.4.1. DMA operation.................................................................................................................... 150
9.4.2. Peripheral handshake......................................................................................................... 152
9.4.3. Arbitration............................................................................................................................ 152
9.4.4. Address generation............................................................................................................. 153
9.4.5. Circular mode...................................................................................................................... 153
9.4.6. Memory to memory mode................................................................................................... 153
9.4.7. Channel configuration......................................................................................................... 153
9.4.8. Interrupt............................................................................................................................... 154
9.4.9. DMA request mapping ........................................................................................................ 155
9.5. Register definition........................................................................................................ 158
9.5.1. Interrupt flag register (DMA_INTF)..................................................................................... 158
9.5.2. Interrupt flag clear register (DMA_INTC)............................................................................ 158
9.5.3. Channel x control register (DMA_CHxCTL) ....................................................................... 159
9.5.4. Channel x counter register (DMA_CHxCNT)...................................................................... 161
9.5.5. Channel x peripheral base address register (DMA_CHxPADDR)...................................... 162
9.5.6. Channel x memory base address register (DMA_CHxMADDR)........................................ 162
10. Debug (DBG).....................................................................................................164
10.1. Overview.................................................................................................................... 164
10.2. Serial Wire Debug port overview............................................................................ 164
10.2.1. Pin assignment ................................................................................................................... 164
10.2.2. JEDEC-106 ID code ........................................................................................................... 164
10.3. Debug hold function overview................................................................................ 165
10.3.1. Debug support for power saving mode............................................................................... 165
10.3.2. Debug support for TIMER, I2C, RTC, WWDGT and FWDGT............................................ 165
10.4. Register definition.................................................................................................... 166
10.4.1. ID code register (DBG_ID).................................................................................................. 166
10.4.2. Control register 0 (DBG_CTL0).......................................................................................... 166
10.4.3. Control register 1 (DBG_CTL1).......................................................................................... 168
11. Analog to digital converter (ADC) ...................................................................170
11.1. Overview.................................................................................................................... 170
11.2. Characteristics.......................................................................................................... 170
11.3. Pins and internal signals......................................................................................... 171
11.4. Function overview.................................................................................................... 172

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11.4.1. Foreground calibration function.......................................................................................... 172
11.4.2. Dual clock domain architecture........................................................................................... 173
11.4.3. ADCON enable................................................................................................................... 173
11.4.4. Routine sequence............................................................................................................... 173
11.4.5. Operation modes ................................................................................................................ 173
11.4.6. Conversion result threshold monitor function..................................................................... 176
11.4.7. Data storage mode ............................................................................................................. 176
11.4.8. Sample time configuration.................................................................................................. 177
11.4.9. External trigger configuration.............................................................................................. 178
11.4.10. DMA request ....................................................................................................................... 178
11.4.11. ADC internal channels........................................................................................................ 178
11.4.12. ADC interrupts .................................................................................................................... 179
11.4.13. Programmable resolution (DRES)...................................................................................... 179
11.4.14. On-chip hardware oversampling......................................................................................... 180
11.5. Register definition.................................................................................................... 183
11.5.1. Status register (ADC_STAT)............................................................................................... 183
11.5.2. Control register 0 (ADC_CTL0) .......................................................................................... 183
11.5.3. Control register 1 (ADC_CTL1) .......................................................................................... 185
11.5.4. Sampling time register 0 (ADC_SAMPT0) ......................................................................... 187
11.5.5. Sampling time register 1 (ADC_SAMPT1) ......................................................................... 187
11.5.6. Watchdog high threshold register (ADC_WDHT)............................................................... 188
11.5.7. Watchdog low threshold register (ADC_WDLT) ................................................................. 189
11.5.8. Routine sequence register0(ADC_RSQ0).......................................................................... 189
11.5.9. Routine sequence register1(ADC_RSQ1).......................................................................... 190
11.5.10. Routine sequence register 2 (ADC_RSQ2)........................................................................ 190
11.5.11. Routine data register (ADC_RDATA).................................................................................. 191
11.5.12. Oversampling control register (ADC_OVSAMPCTL) ......................................................... 191
12. Digital-to-analog converter (DAC)...................................................................194
12.1. Overview.................................................................................................................... 194
12.2. Characteristic............................................................................................................ 194
12.3. Function overview.................................................................................................... 195
12.3.1. DAC enable......................................................................................................................... 195
12.3.2. DAC output buffer............................................................................................................... 195
12.3.3. DAC data configuration....................................................................................................... 195
12.3.4. DAC trigger......................................................................................................................... 195
12.3.5. DAC workflow ..................................................................................................................... 196
12.3.6. DAC noise wave ................................................................................................................. 196
12.3.7. DAC output calculate.......................................................................................................... 197
12.3.8. DMA function....................................................................................................................... 197
12.4. Registers definition.................................................................................................. 198
12.4.1. Control register (DAC_CTL) ............................................................................................... 198

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12.4.2. Software trigger register (DAC_SWT) ................................................................................ 199
12.4.3. DAC 12-bit right-aligned data holding register(DAC_R12DH)............................................ 200
12.4.4. DAC 12-bit left-aligned data holding register(DAC_L12DH) .............................................. 200
12.4.5. DAC 8-bit right-aligned data holding register (DAC_R8DH)............................................... 201
12.4.6. DAC data output register (DAC_DO).................................................................................. 201
12.4.7. DAC Status register (DAC_STAT)...................................................................................... 201
13. Comparator (CMP)............................................................................................203
13.1. Overview.................................................................................................................... 203
13.2. Characteristic............................................................................................................ 203
13.3. Function overview.................................................................................................... 203
13.3.1. CMP clock and reset........................................................................................................... 204
13.3.2. CMP I/O configure .............................................................................................................. 204
13.3.3. CMP operating mode.......................................................................................................... 205
13.3.4. CMP hysteresis................................................................................................................... 205
13.3.5. CMP register write protection ............................................................................................. 205
13.4. CMP registers............................................................................................................ 206
13.4.1. Control/status register (CMP_CS)...................................................................................... 206
14. Watchdog timer (WDGT) ..................................................................................210
14.1. Free watchdog timer (FWDGT) ............................................................................... 210
14.1.1. Overview............................................................................................................................. 210
14.1.2. Characteristics.................................................................................................................... 210
14.1.3. Function overview............................................................................................................... 210
14.1.4. Register definition............................................................................................................... 213
14.2. Window watchdog timer (WWDGT)........................................................................ 217
14.2.1. Overview............................................................................................................................. 217
14.2.2. Characteristics.................................................................................................................... 217
14.2.3. Function overview............................................................................................................... 217
14.2.4. Register definition............................................................................................................... 220
15. Real-time clock (RTC).......................................................................................222
15.1. Overview.................................................................................................................... 222
15.2. Characteristics.......................................................................................................... 222
15.3. Function overview.................................................................................................... 223
15.3.1. Block diagram..................................................................................................................... 223
15.3.2. Clock source and prescalers .............................................................................................. 223
15.3.3. Shadow registers introduction ............................................................................................ 224
15.3.4. Configurable and field maskable alarm .............................................................................. 224
15.3.5. RTC initialization and configuration .................................................................................... 225
15.3.6. Calendar reading ................................................................................................................ 226
15.3.7. Resetting the RTC .............................................................................................................. 227

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15.3.8. RTC shift function ............................................................................................................... 227
15.3.9. RTC reference clock detection ........................................................................................... 228
15.3.10. RTC smooth digital calibration............................................................................................ 229
15.3.11. Time-stamp function ........................................................................................................... 231
15.3.12. Tamper detection ................................................................................................................ 231
15.3.13. Calibration clock output ...................................................................................................... 232
15.3.14. Alarm output........................................................................................................................ 232
15.3.15. RTC power saving mode management.............................................................................. 233
15.3.16. RTC interrupts..................................................................................................................... 233
15.4. Register definition.................................................................................................... 234
15.4.1. Time register (RTC_TIME).................................................................................................. 234
15.4.2. Date register (RTC_DATE)................................................................................................. 234
15.4.3. Control register (RTC_CTL)................................................................................................ 235
15.4.4. Status register (RTC_STAT) ............................................................................................... 237
15.4.5. Prescaler register (RTC_PSC) ........................................................................................... 239
15.4.6. Alarm 0 time and date register (RTC_ALRM0TD).............................................................. 239
15.4.7. Write protection key register (RTC_WPK).......................................................................... 241
15.4.8. Sub second register (RTC_SS) .......................................................................................... 241
15.4.9. Shift function control register (RTC_SHIFTCTL)................................................................ 241
15.4.10. Time of time stamp register (RTC_TTS)............................................................................. 242
15.4.11. Date of time stamp register (RTC_DTS)............................................................................. 243
15.4.12. Sub second of time stamp register (RTC_SSTS)............................................................... 243
15.4.13. High resolution frequency compensation register (RTC_HRFC) ....................................... 244
15.4.14. Tamper register (RTC_TAMP) ............................................................................................ 245
15.4.15. Alarm 0 sub second register (RTC_ALRM0SS) ................................................................. 247
15.4.16. Backup registers (RTC_BKPx) (x = 0..4)............................................................................ 248
16. Timer (TIMERx) .................................................................................................250
16.1. Advanced timer (TIMERx ,x=0)................................................................................ 251
16.1.1. Overview............................................................................................................................. 251
16.1.2. Characteristics.................................................................................................................... 251
16.1.3. Block diagram..................................................................................................................... 252
16.1.4. Function overview............................................................................................................... 253
16.1.5. Register definition............................................................................................................... 279
16.2. General level0 timer (TIMERx, x=1, 2).................................................................... 306
16.2.1. Overview............................................................................................................................. 306
16.2.2. Characteristics.................................................................................................................... 306
16.2.3. Block diagram..................................................................................................................... 307
16.2.4. Function overview............................................................................................................... 308
16.2.5. Register definition............................................................................................................... 323
16.3. General level2 timer (TIMERx, x=13)...................................................................... 348
16.3.1. Overview............................................................................................................................. 348
16.3.2. Characteristics.................................................................................................................... 348

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16.3.3. Block diagram..................................................................................................................... 348
16.3.4. Function overview............................................................................................................... 349
16.3.5. Register definition............................................................................................................... 356
16.4. General level3 timer (TIMERx, x=14)...................................................................... 366
16.4.1. Overview............................................................................................................................. 366
16.4.2. Characteristics.................................................................................................................... 366
16.4.3. Block diagram..................................................................................................................... 367
16.4.4. Function overview............................................................................................................... 368
16.4.5. Register definition............................................................................................................... 383
16.5. General level4 timer (TIMERx, x=15,16)................................................................. 403
16.5.1. Overview............................................................................................................................. 403
16.5.2. Characteristics.................................................................................................................... 403
16.5.3. Block diagram..................................................................................................................... 404
16.5.4. Function overview............................................................................................................... 405
16.5.5. Register definition............................................................................................................... 418
16.6. Basic timer (TIMERx, x=5) ....................................................................................... 434
16.6.1. Overview............................................................................................................................. 434
16.6.2. Characteristics.................................................................................................................... 434
16.6.3. Block diagram..................................................................................................................... 434
16.6.4. Function overview............................................................................................................... 434
16.6.5. Register definition............................................................................................................... 439
17. Infrared ray port (IFRP) ....................................................................................444
17.1. Overview.................................................................................................................... 444
17.2. Characteristics.......................................................................................................... 444
17.3. Function overview.................................................................................................... 444
18. Universal synchronous / asynchronous receiver / transmitter (USART).....446
18.1. Overview.................................................................................................................... 446
18.2. Characteristics.......................................................................................................... 446
18.3. Function overview.................................................................................................... 448
18.3.1. USART frame format .......................................................................................................... 448
18.3.2. Baud rate generation .......................................................................................................... 449
18.3.3. USART transmitter.............................................................................................................. 450
18.3.4. USART receiver.................................................................................................................. 451
18.3.5. Use DMA for data buffer access......................................................................................... 452
18.3.6. Hardware flow control......................................................................................................... 454
18.3.7. Multi-processor communication.......................................................................................... 455
18.3.8. LIN mode ............................................................................................................................ 456
18.3.9. Synchronous mode............................................................................................................. 457
18.3.10. IrDA SIR ENDEC mode ...................................................................................................... 458
18.3.11. Half-duplex communication mode ...................................................................................... 459