GigaDevice Semiconductor GD32E50 Series User manual

GigaDevice Semiconductor Inc.
GD32E50x
Arm® Cortex®-M33 32-bit MCU
For GD32E503xx, GD32E505xx, GD32E507xx, GD32E508xx,
GD32EPRTxx
User Manual
Revision 1.7
(Jun. 2022)

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Table of Contents
Table of Contents.................................................................................................................2
List of Figures ....................................................................................................................21
List of Tables ......................................................................................................................31
1. System and memory architecture ............................................................................36
1.1. Arm® Cortex®-M33 processor..................................................................................36
1.2. System architecture................................................................................................37
1.3. Memory map............................................................................................................39
1.3.1. On-chip SRAM memory ..........................................................................................43
1.3.2. On-chip flash memory overview................................................................................43
1.4. Boot configuration..................................................................................................44
1.5. Device electronic signature ....................................................................................44
1.5.1. Memory density information.....................................................................................45
1.5.2. Unique device ID (96 bits) .......................................................................................45
1.6. System configuration registers ..............................................................................46
2. Flash me mory controller (FMC) ................................................................................47
2.1. Overview..................................................................................................................47
2.2. Characteristics........................................................................................................47
2.3. Function overview...................................................................................................47
2.3.1. Flash memory architecture ......................................................................................47
2.3.2. Read operations ....................................................................................................48
2.3.3. Unlock the FMC_CTL register..................................................................................49
2.3.4. Page erase ...........................................................................................................50
2.3.5. Mass erase...........................................................................................................51
2.3.6. Main flash programming..........................................................................................52
2.3.7. OTP programming..................................................................................................54
2.3.8. Option bytes erase.................................................................................................54
2.3.9. Option bytes modify................................................................................................55
2.3.10. Option bytes description..........................................................................................55
2.3.11. Page erase / program protection...............................................................................57
2.3.12. Security protection .................................................................................................57
2.4. Register definition...................................................................................................58
2.4.1. Wait state register (FMC_WS)..................................................................................58
2.4.2. Unlock key register (FMC_KEY)...............................................................................59
2.4.3. Option byte unlock key register (FMC_OBKEY) ..........................................................59
2.4.4. Status register (FMC_STAT) ....................................................................................60

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2.4.5. Control register (FMC_CTL).....................................................................................61
2.4.6. Address register (FMC_ADDR) ................................................................................62
2.4.7. Option byte status register (FMC_OBSTAT) ...............................................................62
2.4.8. Erase/Program protection register (FMC_WP)............................................................63
2.4.9. Product ID register (FMC_PID).................................................................................63
3. Backup registers (BKP)..............................................................................................65
3.1. Overview..................................................................................................................65
3.2. Characteristics........................................................................................................65
3.3. Function overview...................................................................................................65
3.3.1. RTC clock calibration..............................................................................................65
3.3.2. Tamper detection ...................................................................................................65
3.4. Register definition...................................................................................................67
3.4.1. Backup data register x (BKP_DATAx) (x= 0..41)..........................................................67
3.4.2. RTC signal output control register (BKP_OCTL)..........................................................67
3.4.3. Tamper pin control register (BKP_TPCTL)..................................................................68
3.4.4. Tamper control and status register (BKP_TPCS).........................................................69
4. Power management unit (PMU) ................................................................................70
4.1. Overview..................................................................................................................70
4.2. Characteristics........................................................................................................70
4.3. Function overview...................................................................................................70
4.3.1. Backup domain......................................................................................................71
4.3.2. VDD / VDDA power domain.........................................................................................72
4.3.3. 1.1V power domain ................................................................................................75
4.3.4. Power saving modes ..............................................................................................75
4.4. Register definition...................................................................................................80
4.4.1. Control register 0 (PMU_CTL0) ................................................................................80
4.4.2. Control and status register 0 (PMU_CS0) ..................................................................82
4.4.3. Control register 1 (PMU_CTL1) ................................................................................84
4.4.4. Control and status register 1 (PMU_CS1) ..................................................................85
5. Reset and clock unit (RCU) .......................................................................................86
High density reset and clock control unit (RCU)..............................................................86
5.1. Reset control unit (RCTL) .......................................................................................86
5.1.1. Overview ..............................................................................................................86
5.1.2. Function overview ..................................................................................................86
5.2. Clock control unit (CCTL) .......................................................................................87
5.2.1. Overview ..............................................................................................................87
5.2.2. Characteristics.......................................................................................................89
5.2.3. Function overview ..................................................................................................89

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5.3. Register definition...................................................................................................94
5.3.1. Control register (RCU_CTL).....................................................................................94
5.3.2. Clock configuration register 0 (RCU_CFG0)...............................................................95
5.3.3. Clock interrupt register (RCU_INT) ...........................................................................99
5.3.4. APB2 reset register (RCU_APB2RST).....................................................................101
5.3.5. APB1 reset register (RCU_APB1RST).....................................................................104
5.3.6. AHB enable register (RCU_AHBEN).......................................................................107
5.3.7. APB2 enable register (RCU_APB2EN)....................................................................108
5.3.8. APB1 enable register (RCU_APB1EN).................................................................... 111
5.3.9. Backup domain control register (RCU_BDCTL).........................................................114
5.3.10. Reset source/clock register (RCU_RSTSCK)............................................................115
5.3.11. AHB reset register (RCU_AHBRST)........................................................................117
5.3.12. Clock configuration register 1 (RCU_CFG1).............................................................118
5.3.13. Deep-sleep mode voltage register (RCU_DSV).........................................................118
5.3.14. Additional clock control register (RCU_ADDCTL) ......................................................119
5.3.15. Additional clock interrupt register (RCU_ADDINT) .....................................................120
5.3.16. PLL clock spread spectrum control register (RCU_PLLSSCTL) ...................................120
5.3.17. Clock configuration register 2 (RCU_CFG2).............................................................121
5.3.18. APB1 additional reset register (RCU_ADDAPB1RST)................................................122
5.3.19. APB1 additional enable register (RCU_ADDAPB1EN) ...............................................122
Connectivity line devices: reset and clock control unit (RCU) ......................................124
5.4. Reset control unit (RCTL) .....................................................................................124
5.4.1. Overview ............................................................................................................124
5.4.2. Function overview ................................................................................................124
5.5. Clock control unit (CCTL) .....................................................................................125
5.5.1. Overview ............................................................................................................125
5.5.2. Characteristics.....................................................................................................127
5.5.3. Function overview ................................................................................................128
5.6. Register definition.................................................................................................133
5.6.1. Control register (RCU_CTL)...................................................................................133
5.6.2. Clock configuration register 0 (RCU_CFG0).............................................................135
5.6.3. Clock interrupt register (RCU_INT) .........................................................................138
5.6.4. APB2 reset register (RCU_APB2RST).....................................................................142
5.6.5. APB1 reset register (RCU_APB1RST).....................................................................144
5.6.6. AHB enable register (RCU_AHBEN).......................................................................147
5.6.7. APB2 enable register (RCU_APB2EN)....................................................................149
5.6.8. APB1 enable register (RCU_APB1EN)....................................................................152
5.6.9. Backup domain control register (RCU_BDCTL).........................................................155
5.6.10. Reset source/clock register (RCU_RSTSCK)............................................................156
5.6.11. AHB reset register (RCU_AHBRST)........................................................................158
5.6.12. Clock configuration register 1 (RCU_CFG1).............................................................159
5.6.13. Deep-sleep mode voltage register (RCU_DSV).........................................................162

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5.6.14. Additional clock control register (RCU_ADDCTL) ......................................................162
5.6.15. Additional Clock configuration register (RCU_ADDCFG) ............................................164
5.6.16. Additional clock interrupt register (RCU_ADDINT) .....................................................165
5.6.17. PLL clock spread spectrum control register (RCU_PLLSSCTL) ...................................166
5.6.18. Clock configuration register 2 (RCU_CFG2).............................................................167
5.6.19. APB1 additional reset register (RCU_ADDAPB1RST)................................................168
5.6.20. APB1 additional enable register (RCU_ADDAPB1EN) ...............................................168
6. Clock trim controller (CTC)......................................................................................170
6.1. Overview................................................................................................................170
6.2. Characteristics......................................................................................................170
6.3. Function overview.................................................................................................170
6.3.1. REF sync pulse generator .....................................................................................171
6.3.2. CTC trim counter..................................................................................................171
6.3.3. Frequency evaluation and automatically trim process ................................................172
6.3.4. Software program guide........................................................................................173
6.4. Register definition.................................................................................................175
6.4.1. Control register 0 (CTC_CTL0)...............................................................................175
6.4.2. Control register 1 (CTC_CTL1)...............................................................................176
6.4.3. Status register (CTC_STAT)...................................................................................177
6.4.4. Interrupt clear register (CTC_INTC) ........................................................................179
7. Interrupt/event controller (EXTI).............................................................................181
7.1. Overview................................................................................................................181
7.2. Characteristics......................................................................................................181
7.3. Interrupts function overview.................................................................................181
7.4. External interrupt and event (EXTI) block diagram ..............................................186
7.5. External Interrupt and event function overview ...................................................186
7.6. EXTI Register.........................................................................................................189
7.6.1. Interrupt enable register (EXTI_INTEN) ...................................................................189
7.6.2. Event enable register (EXTI_EVEN)........................................................................189
7.6.3. Rising edge trigger enable register (EXTI_RTEN)......................................................190
7.6.4. Falling edge trigger enable register (EXTI_FTEN) .....................................................190
7.6.5. Software interrupt event register (EXTI_SWIEV).......................................................190
7.6.6. Pending register (EXTI_PD)...................................................................................191
8. General-purpose and alternate-function I/Os (GPIO and AFIO).........................192
8.1. Overview................................................................................................................192
8.2. Characteristics......................................................................................................192
8.3. Function overview.................................................................................................192
8.3.1. GPIO pin configuration..........................................................................................193

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8.3.2. External interrupt/event lines..................................................................................194
8.3.3. Alternate functions (AF).........................................................................................194
8.3.4. Input configuration................................................................................................194
8.3.5. Output configuration.............................................................................................195
8.3.6. Analog configuration.............................................................................................195
8.3.7. Alternate function (AF) configuration .......................................................................196
8.3.8. IO pin function selection........................................................................................196
8.3.9. GPIO locking function...........................................................................................197
8.3.10. GPIO I/O compensation cell...................................................................................197
8.4. Remapping function I/O and debug configuration...............................................197
8.4.1. Introduction.........................................................................................................197
8.4.2. Main features ......................................................................................................197
8.4.3. JTAG/SWD alternate function remapping.................................................................198
8.4.4. ADC AF remapping ..............................................................................................198
1.1.1. TIMER AF remapping ...........................................................................................199
1.1.1. USART AF remapping...........................................................................................200
3.1.1. I2C0 AF remapping ..............................................................................................201
3.1.2. SPI0/SPI2/I2S AF remapping.................................................................................201
3.1.3. CAN0/1 AF remapping..........................................................................................202
3.1.4. Ethernet AF remapping.........................................................................................203
3.1.5. CTC AF remapping...............................................................................................203
3.1.6. CLK pins AF remapping ........................................................................................203
3.2. Register definition.................................................................................................205
3.2.1. Port control register 0 (GPIOx_CTL0, x=A..G) ..........................................................205
3.2.2. Port control register 1 (GPIOx_CTL1, x=A..G) ..........................................................207
3.2.3. Port input status register (GPIOx_ISTAT, x=A..G)......................................................208
3.2.4. Port output control register (GPIOx_OCTL, x=A..G)...................................................209
3.2.5. Port bit operate register (GPIOx_BOP, x=A..G).........................................................209
3.2.6. Port bit clear register (GPIOx_BC, x=A..G)...............................................................210
3.2.7. Port configuration lock register (GPIOx_LOCK, x=A..G) .............................................210
3.2.8. Port bit speed register (GPIOx_ SPD, x=A..G)..........................................................211
3.2.9. Event control register (AFIO_EC)............................................................................212
3.2.10. AFIO port configuration register 0 (AFIO_PCF0).......................................................212
3.2.11. EXTI sources selection register 0 (AFIO_EXTISS0)...................................................219
3.2.12. EXTI sources selection register 1 (AFIO_EXTISS1)...................................................220
3.2.13. EXTI sources selection register 2 (AFIO_EXTISS2)...................................................221
3.2.14. EXTI sources selection register 3 (AFIO_EXTISS3)...................................................222
3.2.15. AFIO port configuration register 1 (AFIO_PCF1).......................................................224
3.2.16. IO compensation control register (AFIO_CPSCTL)....................................................225
3.2.17. AFIO port configuration register A (AFIO_PCFA).......................................................226
3.2.18. AFIO port configuration register B (AFIO_PCFB).......................................................228
3.2.19. AFIO port configuration register C (AFIO_PCFC)......................................................230
3.2.20. AFIO port configuration register D (AFIO_PCFD)......................................................232

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3.2.21. AFIO port configuration register E (AFIO_PCFE).......................................................233
3.2.22. AFIO port configuration register G (AFIO_PCFG)......................................................234
9. Cyclic redundancy checks management unit (CRC)...........................................237
3.3. Overview................................................................................................................237
3.4. Characteristics......................................................................................................237
3.5. Function overview.................................................................................................238
3.6. Register definition.................................................................................................239
3.6.1. Data register (CRC_DATA)....................................................................................239
3.6.2. Free data register (CRC_FDATA) ...........................................................................239
9.1.1. Control register (CRC_CTL)...................................................................................240
9.1.2. Initialization data register (CRC_IDATA)...................................................................240
9.1.3. Polynomial register (CRC_POLY) ...........................................................................241
10. Trigonometric Math Unit (TMU)............................................................................242
10.1. Overview ............................................................................................................242
10.2. Characteristics...................................................................................................242
10.3. Function overview .............................................................................................242
10.3.1. TMU block diagram ..............................................................................................242
10.3.2. Data format .........................................................................................................243
10.3.3. Mode 0 description...............................................................................................244
10.3.4. Mode 1 description...............................................................................................244
10.3.5. Mode 2 description...............................................................................................245
10.3.6. Mode 3 description...............................................................................................245
10.3.7. Mode 4 description...............................................................................................245
10.3.8. Mode 5 description...............................................................................................246
10.3.9. Mode 6 description...............................................................................................246
10.3.10. Mode 7 description...............................................................................................248
10.3.11. Mode 8 description...............................................................................................248
10.4. Software guideline .............................................................................................248
10.5. TMU register.......................................................................................................250
10.5.1. Input data0 register (TMU_IDATA0).........................................................................250
10.5.2. Input data1 register (TMU_IDATA1).........................................................................250
10.5.3. Control register (TMU_CTL)...................................................................................251
10.5.4. Data0 register (TMU_DATA0).................................................................................252
10.5.5. Data1 register (TMU_DATA1).................................................................................252
10.5.6. Status register (TMU_STAT) ..................................................................................252
11. Direct memory access controller (DMA) ............................................................254
11.1. Overview ............................................................................................................254
11.2. Characteristics...................................................................................................254

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11.3. Block diagram....................................................................................................255
11.4. Function overview .............................................................................................255
11.4.1. DMA operation.....................................................................................................255
11.4.2. Peripheral handshake...........................................................................................257
11.4.3. Arbitration...........................................................................................................257
11.4.4. Address generation ..............................................................................................258
11.4.5. Circular mode......................................................................................................258
11.4.6. Memory to memory mode......................................................................................258
11.4.7. Channel configuration...........................................................................................258
11.4.8. Interrupt..............................................................................................................259
11.4.9. DMA request mapping ..........................................................................................259
11.5. Register definition .............................................................................................263
11.5.1. Interrupt flag register (DMA_INTF)..........................................................................263
11.5.2. Interrupt flag clear register (DMA_INTC) ..................................................................264
11.5.3. Channel x control register (DMA_CHxCTL) ..............................................................264
11.5.4. Channel x counter register (DMA_CHxCNT).............................................................266
11.5.5. Channel x peripheral base address register (DMA_CHxPADDR) .................................267
11.5.6. Channel x memory base address register (DMA_CHxMADDR)...................................267
12. Debug (DBG)...........................................................................................................269
12.1. Introduction........................................................................................................269
12.2. JTAG/SW function description ..........................................................................269
12.2.1. Switch JTAG or SW interface.................................................................................269
12.2.2. Pin assignment ....................................................................................................269
12.2.3. JTAG daisy chained structure.................................................................................270
12.2.4. Debug reset ........................................................................................................270
12.2.5. JEDEC-106 ID code.............................................................................................270
12.3. Debug hold function description.......................................................................270
12.3.1. Debug support for power saving mode ....................................................................270
12.3.2. Debug support for TIMER, I2C, WWDGT, FWDGT and CAN.......................................271
12.4. DBG registers.....................................................................................................272
12.4.1. ID code register (DBG_ID).....................................................................................272
12.4.2. Control register (DBG_CTL)...................................................................................272
13. Analog-to-digital converter (ADC).......................................................................276
13.1. Introduction........................................................................................................276
13.2. Characteristics...................................................................................................276
13.3. Pins and internal signals ...................................................................................277
13.4. Functional overview...........................................................................................278
13.4.1. Foreground calibration function ..............................................................................279
13.4.2. ADC clock...........................................................................................................280

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13.4.3. ADCON enable....................................................................................................280
13.4.4. Single-ended and differential input channels.............................................................280
13.4.5. Routine sequence................................................................................................281
13.4.6. Operation modes .................................................................................................281
13.4.7. Conversion result threshold monitor........................................................................284
13.4.8. Data storage mode...............................................................................................284
13.4.9. Sample time configuration.....................................................................................285
13.4.10. External trigger configuration .................................................................................285
13.4.11. DMA request .......................................................................................................286
13.4.12. ADC internal channels ..........................................................................................286
13.4.13. Programmable resolution (DRES)...........................................................................287
13.4.14. On-chip hardware oversampling.............................................................................287
13.5. ADC sync mode .................................................................................................289
13.5.1. Free mode ..........................................................................................................290
13.5.2. Routine parallel mode...........................................................................................290
13.5.3. Routine follow-up fast mode...................................................................................291
13.5.4. Routine follow-up slow mode .................................................................................291
13.6. ADC interrupts ...................................................................................................292
13.7. ADC registers.....................................................................................................293
13.7.1. Status register (ADC_STAT) ..................................................................................293
13.7.2. Control register 0 (ADC_CTL0) ..............................................................................294
13.7.3. Control register 1 (ADC_CTL1) ..............................................................................296
13.7.4. Sample time register 0 (ADC_SAMPT0) ..................................................................298
13.7.5. Sample time register 1 (ADC_SAMPT1) ..................................................................299
13.7.6. Watchdog high threshold register 0 (ADC_WDHT0)...................................................300
13.7.7. Watchdog low threshold register 0 (ADC_WDLT0).....................................................300
13.7.8. Routine sequence register 0 (ADC_RSQ0) ..............................................................300
13.7.9. Routine sequence register 1 (ADC_RSQ1) ..............................................................301
13.7.10. Routine sequence register 2 (ADC_RSQ2) ..............................................................302
13.7.11. Routine data register (ADC_RDATA).......................................................................302
13.7.12. Oversample control register (ADC_OVSAMPCTL) ....................................................303
13.7.13. Watchdog 1 channel selection register (ADC_WD1SR)..............................................304
13.7.14. Watchdog 2 channel selection register (ADC_WD2SR)..............................................305
13.7.15. Watchdog threshold register 1 (ADC_WDT1)............................................................305
13.7.16. Watchdog threshold register 2 (ADC_WDT2)............................................................306
13.7.17. Differential mode control register (ADC_DIFCTL) ......................................................307
14. Digital-to-analog converter (DAC) .......................................................................308
14.1. Introduction........................................................................................................308
14.2. Main features .....................................................................................................308
14.3. Function description..........................................................................................309
14.3.1. DAC enable.........................................................................................................309

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14.3.2. DAC output buffer ................................................................................................309
14.3.3. DAC data configuration.........................................................................................310
14.3.4. DAC trigger.........................................................................................................310
14.3.5. DAC workflow......................................................................................................310
14.3.6. DAC output FIFO.................................................................................................311
14.3.7. DAC noise wave ..................................................................................................311
14.3.8. DAC output calculate............................................................................................312
14.3.9. DMA funtion ........................................................................................................312
14.3.10. DAC concurrent conversion...................................................................................313
14.4. DAC registers.....................................................................................................314
14.4.1. Control register 0 (DAC_CTL0) ..............................................................................314
14.4.2. Software trigger register (DAC_SWT)......................................................................317
14.4.3. DAC_OUT0 12-bit right-aligned data holding register (OUT0_R12DH) .........................317
14.4.4. DAC_OUT0 12-bit left-aligned data holding register (OUT0_L12DH)............................318
14.4.5. DAC_OUT0 8-bit right-aligned data holding register (OUT0_R8DH).............................318
14.4.6. DAC_OUT1 12-bit right-aligned data holding register (OUT1_R12DH) .........................319
14.4.7. DAC_OUT1 12-bit left-aligned data holding register (OUT1_L12DH)............................319
14.4.8. DAC_OUT1 8-bit right-aligned data holding register (OUT1_R8DH).............................320
14.4.9. DAC concurrent mode 12-bit right-aligned data holding register (DACC_R12DH)...........320
14.4.10. DAC concurrent mode 12-bit left-aligned data holding register (DACC_L12DH).............321
14.4.11. DAC concurrent mode 8-bit right-aligned data holding register (DACC_R8DH) ..............321
14.4.12. DAC_OUT0 data output register (OUT0_DO) ...........................................................322
14.4.13. DAC_OUT1 data output register (OUT1_DO) ...........................................................322
14.4.14. DAC Status register 0 (DAC_STAT0).......................................................................323
14.4.15. DAC Control Register 1 (DAC_CTL1)......................................................................323
14.4.16. DAC Status Register 1 (DAC_STAT1) .....................................................................324
15. Comparator (CMP) .................................................................................................326
15.1. Overview ............................................................................................................326
15.2. Characteristic.....................................................................................................326
15.3. Function overview.............................................................................................326
15.3.1. CMP I/O configuration...........................................................................................327
15.3.2. CMP output blanking ............................................................................................328
15.3.3. CMP register write protection.................................................................................329
15.4. CMP registers.....................................................................................................330
15.4.1. CMP1 Control/status register (CMP1_CS)................................................................330
15.4.2. CMP3 Control/status register (CMP3_CS)................................................................331
15.4.3. CMP5 Control/status register (CMP5_CS)................................................................333
16. Watchdog timer (WDGT) .......................................................................................336
16.1. Free watchdog timer (FWDGT) ..........................................................................336
16.1.1. Overview ............................................................................................................336
16.1.2. Characteristics.....................................................................................................336

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16.1.3. Function overview ................................................................................................336
16.1.4. Register definition ................................................................................................339
16.2. Window watchdog timer (WWDGT) ...................................................................342
16.2.1. Overview ............................................................................................................342
16.2.2. Characteristics.....................................................................................................342
16.2.3. Function overview ................................................................................................342
16.2.4. Register definition ................................................................................................345
17. Real-time clock (RTC)............................................................................................347
3.7. Overview................................................................................................................347
3.8. Characteristics......................................................................................................347
3.9. Function overview.................................................................................................347
17.1.1. RTC reset...........................................................................................................348
17.1.2. RTC reading........................................................................................................348
17.1.3. RTC configuration................................................................................................348
17.1.4. RTC flag assertion................................................................................................349
3.10. RTC Register......................................................................................................351
17.1.5. RTC interrupt enable register (RTC_INTEN).............................................................351
17.1.6. RTC control register (RTC_CTL).............................................................................351
17.1.7. RTC prescaler high register (RTC_PSCH) ...............................................................352
17.1.8. RTC prescaler low register (RTC_PSCL) .................................................................353
17.1.9. RTC divider high register (RTC_DIVH) ....................................................................353
17.1.10. RTC divider low register (RTC_DIVL)......................................................................353
17.1.11. RTC counter high register (RTC_CNTH) ..................................................................354
17.1.12. RTC counter low register (RTC_CNTL)....................................................................354
17.1.13. RTC alarm high register (RTC_ALRMH) ..................................................................355
17.1.14. RTC alarm low register (RTC_ALRML)....................................................................355
18. Timer (TIMERx).......................................................................................................356
18.1. Advanced timer (TIMERx, x=0, 7) ......................................................................357
18.1.1. Overview ............................................................................................................357
18.1.2. Characteristics.....................................................................................................357
18.1.3. Block diagram......................................................................................................358
18.1.4. Function overview ................................................................................................358
18.1.5. TIMERx registers(x=0, 7).......................................................................................385
18.2. General level0 timer (TIMERx, x=1, 2, 3, 4)........................................................413
18.2.1. Overview ............................................................................................................413
18.2.2. Characteristics.....................................................................................................413
18.2.3. Block diagram......................................................................................................413
18.2.4. Function overview ................................................................................................414
18.2.5. TIMERx registers(x=1, 2, 3, 4)................................................................................429
18.3. General level1 timer (TIMERx, x=8, 11)..............................................................455

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18.3.1. Overview ............................................................................................................455
18.3.2. Characteristics.....................................................................................................455
18.3.3. Block diagram......................................................................................................455
18.3.4. Function overview ................................................................................................456
18.3.5. TIMERx registers(x=8, 11).....................................................................................467
18.4. General level2 timer (TIMERx, x=9, 10, 12, 13) ..................................................480
18.4.1. Overview ............................................................................................................480
18.4.2. Characteristics.....................................................................................................480
18.4.3. Block diagram......................................................................................................480
18.4.4. Function overview ................................................................................................481
18.4.5. TIMERx registers(x=9, 10, 12, 13) ..........................................................................489
18.5. Basic timer (TIMERx, x=5, 6)..............................................................................500
18.5.1. Overview ............................................................................................................500
18.5.2. Characteristics.....................................................................................................500
18.5.3. Block diagram......................................................................................................500
18.5.4. Function overview ................................................................................................500
18.5.5. TIMERx registers(x=5, 6).......................................................................................504
19. Super High-Resolution Timer (SHRTIMER) .......................................................509
19.1. Overview............................................................................................................509
19.2. Characteristics...................................................................................................509
19.3. Block diagram....................................................................................................509
19.4. Function overview.............................................................................................510
19.4.1. Master_TIMER unit ..............................................................................................510
19.4.2. Slave_TIMERx(x=0..4) unit....................................................................................518
19.4.3. DLL calibrate.......................................................................................................549
19.4.4. Bunch mode........................................................................................................549
19.4.5. Synchronization input/output..................................................................................554
19.4.6. External event .....................................................................................................555
19.4.7. Fault input...........................................................................................................557
19.4.8. Trigger to ADC.....................................................................................................559
19.4.9. Trigger to DAC.....................................................................................................560
19.4.10. Interrupt..............................................................................................................561
19.4.11. DMA request .......................................................................................................562
19.4.12. DMA mode..........................................................................................................563
19.4.13. Debug mode .......................................................................................................564
19.5. Register definition .............................................................................................564
19.5.1. Master_TIMER registers........................................................................................565
19.5.2. Slave_TIMERx registers(x=0..4).............................................................................577
19.5.3. Common registers................................................................................................639
20. Universal synchronous/asynchronous receiver /transmitter (USART).........683

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20.1. Universal synchronous/asynchronous receiver /transmitter (USARTx, x=0..4)
683
20.1.1. Overview ............................................................................................................683
20.1.2. Characteristics.....................................................................................................683
20.1.3. Function overview ................................................................................................684
20.1.4. Register definition ................................................................................................700
20.2. Universal synchronous/asynchronous receiver /transmitter (USARTx, x=5) ..714
20.2.1. Overview ............................................................................................................714
20.2.2. Characteristics.....................................................................................................714
20.2.3. Function overview ................................................................................................715
20.2.4. Register defintion.................................................................................................732
21. Inter-integrated circuit interface (I2C).................................................................749
21.1. Inter-integrated circuit interface (I2Cx, x=0, 1)..................................................749
21.1.1. Overview ............................................................................................................749
21.1.2. Characteristics.....................................................................................................749
21.1.3. Function overview ................................................................................................749
21.1.4. Register definition ................................................................................................766
21.2. Inter-integrated circuit interface (I2Cx, x=2)......................................................780
21.2.1. Overview ............................................................................................................780
21.2.2. Characteristics.....................................................................................................780
21.2.3. Function overview ................................................................................................780
21.2.4. Register definition ................................................................................................806
22. Serial peripheral interface/Inter-IC sound (SPI/I2S)..........................................820
22.1. Overview............................................................................................................820
22.2. Characteristics...................................................................................................820
22.2.1. SPI characteristics .............................................................................................820
22.2.2. I2S characteristics..............................................................................................820
22.3. SPI function overview........................................................................................821
22.3.1. SPI block diagram ..............................................................................................821
22.3.2. SPI signal description.........................................................................................821
22.3.3. SPI clock timing and data format.........................................................................822
22.3.4. NSS function......................................................................................................824
22.3.5. SPI operation modes ..........................................................................................825
22.3.6. DMA function.....................................................................................................833
22.3.7. CRC function .....................................................................................................833
22.3.8. SPI interrupts.....................................................................................................834
22.4. I2S function overview........................................................................................835
22.4.1. I2S block diagram...............................................................................................835
22.4.2. I2S signal description.........................................................................................836
22.4.3. I2S audio standards............................................................................................836

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22.4.4. I2S clock............................................................................................................844
22.4.5. Operation...........................................................................................................845
22.4.6. DMA function.....................................................................................................849
22.4.7. I2S interrupts .....................................................................................................849
22.5. Register definition .............................................................................................852
22.5.1. Control register 0 (SPI_CTL0)..............................................................................852
22.5.2. Control register 1 (SPI_CTL1)..............................................................................854
22.5.3. Status register (SPI_STAT)..................................................................................855
22.5.4. Data register (SPI_DATA) ....................................................................................856
22.5.5. CRC polynomial register (SPI_CRCPOLY) ............................................................857
22.5.6. RX CRC register (SPI_RCRC) ..............................................................................857
22.5.7. TX CRC register (SPI_TCRC)...............................................................................858
22.5.8. I2S control register (SPI_I2SCTL) ........................................................................859
22.5.9. I2S clock prescaler register (SPI_I2SPSC)............................................................860
22.5.10. Quad-SPI mode control register (SPI_QCTL) of SPI0.............................................861
23. Serial/Quad Parallel Interface (SQPI) ..................................................................863
23.1. Overview............................................................................................................863
23.2. Characteristics...................................................................................................863
23.3. Function overview.............................................................................................864
23.3.1. SQPI controller sampling polarity............................................................................864
23.3.2. SQPI controller special command...........................................................................865
23.3.3. SQPI controller read ID command ..........................................................................865
23.3.4. SQPI controller output clock configuration................................................................866
23.3.5. SQPI controller initialization...................................................................................866
23.3.6. Read ID command flow.........................................................................................866
23.3.7. Read/Write operation flow...................................................................................866
23.3.8. SQPI controller mode timing ..................................................................................866
23.4. Register definition .............................................................................................868
23.4.1. SQPI Initial Register (SQPI_INIT) ...........................................................................869
23.4.2. SQPI Read Command Register (SQPI_RCMD) ........................................................869
23.4.3. SQPI Write Command Register (SQPI_WCMD)........................................................870
23.4.4. SQPI ID Low Register (SQPI_IDL)..........................................................................871
23.4.5. SQPI ID High Register (SQPI_IDH).........................................................................871
24. Secure digital input/output interface (SDIO) .....................................................873
24.1. Introduction........................................................................................................873
24.2. Main features .....................................................................................................873
24.3. SDIO bus topology.............................................................................................873
24.4. SDIO functional description ..............................................................................876
24.4.1. SDIO adapter ......................................................................................................876
24.4.2. AHB interface......................................................................................................880

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24.5. Card functional description...............................................................................882
24.5.1. Card registers......................................................................................................882
24.5.2. Commands .........................................................................................................883
24.5.3. Responses..........................................................................................................894
24.5.4. Data packets format .............................................................................................898
24.5.5. Two status fields of the card...................................................................................899
24.6. Programming sequence ....................................................................................906
24.6.1. Card identification ................................................................................................906
24.6.2. No data commands ..............................................................................................908
24.6.3. Single block or multiple block write..........................................................................909
24.6.4. Single block or multiple block read..........................................................................910
24.6.5. Stream write and stream read (MMC only)...............................................................911
24.6.6. Erase.................................................................................................................912
24.6.7. Bus width selection...............................................................................................913
24.6.8. Protection management........................................................................................914
24.6.9. Card Lock/Unlock operation...................................................................................914
24.7. Specific operations............................................................................................916
24.7.1. SD I/O specific operations .....................................................................................916
24.7.2. CE-ATA specific operations....................................................................................920
24.8. SDIO registers....................................................................................................922
24.8.1. Power control register (SDIO_PWRCTL) .................................................................922
24.8.2. Clock control register (SDIO_CLKCTL)....................................................................922
24.8.3. Command argument register (SDIO_CMDAGMT) .....................................................924
24.8.4. Command control register (SDIO_CMDCTL) ............................................................924
24.8.5. Command index response register (SDIO_RSPCMDIDX)...........................................926
24.8.6. Response register (SDIO_RESPx x=0..3)................................................................926
24.8.7. Data timeout register (SDIO_DATATO)....................................................................927
24.8.8. Data length register (SDIO_DATALEN)....................................................................927
24.8.9. Data control register (SDIO_DATACTL) ...................................................................928
24.8.10. Data counter register (SDIO_DATACNT)..................................................................929
24.8.11. Status register (SDIO_STAT) .................................................................................930
24.8.12. Interrupt clear register (SDIO_INTC) .......................................................................931
24.8.13. Interrupt enable register (SDIO_INTEN) ..................................................................932
24.8.14. FIFO counter register (SDIO_FIFOCNT)..................................................................934
24.8.15. FIFO data register (SDIO_FIFO).............................................................................935
25. External memory controller (EXMC) ...................................................................936
25.1. Overview ............................................................................................................936
25.2. Characteristics...................................................................................................936
25.3. Function overview .............................................................................................936
25.3.1. Block diagram......................................................................................................936
25.3.2. Basic regulation of EXMC access ...........................................................................937

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25.3.3. External device address mapping...........................................................................938
25.3.4. NOR/PSRAM controller.........................................................................................941
25.3.5. NAND Flash or PC Card controller..........................................................................960
25.4. Registers definition............................................................................................966
25.4.1. NOR/PSRAM controller registers............................................................................966
25.4.2. NAND Flash/PC Card controller registers.................................................................970
26. Controller area network (CAN).............................................................................977
26.1. Overview ............................................................................................................977
26.2. Characteristics...................................................................................................977
26.3. Function overview .............................................................................................978
26.3.1. Working mode .....................................................................................................978
26.3.2. Communication modes .........................................................................................979
26.3.3. Data transmission ................................................................................................980
26.3.4. Data reception.....................................................................................................982
26.3.5. Filtering function ..................................................................................................984
26.3.6. Time-triggered communication ...............................................................................987
26.3.7. Communication parameters...................................................................................987
26.3.8. CAN FD operation................................................................................................989
26.3.9. Transmitter Delay Compensation............................................................................990
26.3.10. Error flags...........................................................................................................991
26.3.11. CAN interrupts.....................................................................................................991
26.4. CAN registers.....................................................................................................994
26.4.1. Control register (CAN_CTL)...................................................................................994
26.4.2. Status register (CAN_STAT) ..................................................................................995
26.4.3. Transmit status register (CAN_TSTAT) ....................................................................997
26.4.4. Receive message FIFO0 register (CAN_RFIFO0)...................................................1000
26.4.5. Receive message FIFO1 register (CAN_RFIFO1)...................................................1000
26.4.6. Interrupt enable register (CAN_INTEN)..................................................................1001
26.4.7. Error register (CAN_ERR) ...................................................................................1003
26.4.8. Bit timing register (CAN_BT)................................................................................1004
26.4.9. FD control register (CAN_FDCTL) ........................................................................1005
26.4.10. FD status register (CAN_FDSTAT)........................................................................1006
26.4.11. FD transmitter delay compensation register (CAN_FDTDC)......................................1006
26.4.12. Date Bit timing register (CAN_DBT) ......................................................................1007
26.4.13. Transmit mailbox identifier register (CAN_TMIx) (x = 0…2).......................................1008
26.4.14. Transmit mailbox property register (CAN_TMPx) (x = 0…2)......................................1008
26.4.15. Transmit mailbox data0 register (CAN_TMDATA0x) (x = 0…2)..................................1009
26.4.16. Transmit mailbox data1 register (CAN_TMDATA1x) (x = 0...2)...................................1010
26.4.17. Receive FIFO mailbox identifier register (CAN_RFIFOMIx) (x = 0,1) ..........................1010
26.4.18. Receive FIFO mailbox property register (CAN_RFIFOMPx) (x = 0,1).......................... 1011
26.4.19. Receive FIFO mailbox data0 register (CAN_RFIFOMDATA0x) (x = 0,1)......................1012

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26.4.20. Receive FIFO mailbox data1 register (CAN_RFIFOMDATA1x) (x = 0,1)......................1012
26.4.21. Filter control register (CAN_FCTL)........................................................................1013
26.4.22. Filter mode configuration register (CAN_FMCFG) ...................................................1013
26.4.23. Filter scale configuration register (CAN_FSCFG) ....................................................1014
26.4.24. Filter associated FIFO register (CAN_FAFIFO).......................................................1015
26.4.25. Filter working register (CAN_FW) .........................................................................1016
26.4.26. Filter x data y register (CAN_FxDATAy) (x = 0…27, y = 0,1)......................................1017
27. Ethernet (ENET)....................................................................................................1018
27.1. Overview ..........................................................................................................1018
27.2. Characteristics.................................................................................................1018
27.2.1. Block diagram....................................................................................................1019
27.2.2. MAC 802.3 Ethernet packet description.................................................................1020
27.2.3. Ethernet signal description...................................................................................1021
27.3. Function overview ...........................................................................................1022
27.3.1. Interface configuration ........................................................................................1022
27.3.2. MAC function overview .......................................................................................1027
27.3.3. DMA controller description...................................................................................1038
27.3.4. MAC statistics counters: MSC..............................................................................1062
27.3.5. Wake up management: WUM...............................................................................1063
27.3.6. Precision time protocol: PTP................................................................................1066
27.3.7. Example for a typical configuration flow of Ethernet .................................................1070
27.3.8. Ethernet interrupts..............................................................................................1072
27.4. Register definition ...........................................................................................1074
27.4.1. MAC configuration register (ENET_MAC_CFG)......................................................1074
27.4.2. MAC frame filter register (ENET_MAC_FRMF).......................................................1076
27.4.3. MAC hash list high register (ENET_MAC_HLH)......................................................1078
27.4.4. MAC hash list low register (ENET_MAC_HLL)........................................................1079
27.4.5. MAC PHY control register (ENET_MAC_PHY_CTL)................................................1079
27.4.6. MAC PHY data register (ENET_MAC_PHY_DATA) .................................................1080
27.4.7. MAC flow control register (ENET_MAC_FCTL).......................................................1080
27.4.8. MAC VLAN tag register (ENET_MAC_VLT)............................................................1082
27.4.9. MAC remote wakeup frame filter register (ENET_MAC_RWFF).................................1083
27.4.10. MAC wakeup management register (ENET_MAC_WUM).........................................1083
27.4.11. MAC debug register (ENET_MAC_DBG)...............................................................1084
27.4.12. MAC interrupt flag register (ENET_MAC_INTF) ......................................................1086
27.4.13. MAC interrupt mask register (ENET_MAC_INTMSK)...............................................1087
27.4.14. MAC address 0 high register (ENET_MAC_ADDR0H) .............................................1088
27.4.15. MAC address 0 low register (ENET_MAC_ADDR0L)...............................................1088
27.4.16. MAC address 1 high register (ENET_MAC_ADDR1H) .............................................1089
27.4.17. MAC address 1 low register (ENET_MAC_ADDR1L)...............................................1090
27.4.18. MAC address 2 high register (ENET_MAC_ADDR2H) .............................................1090
27.4.19. MAC address 2 low register (ENET_MAC_ADDR2L)...............................................1091

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27.4.20. MAC address 3 high register (ENET_MAC_ADDR3H) .............................................1091
27.4.21. MAC address 3 low register (ENET_MAC_ADDR3L)...............................................1092
27.4.22. MAC flow control threshold register (ENET_MAC_FCTH).........................................1092
27.4.23. MSC control register (ENET_MSC_CTL) ...............................................................1093
27.4.24. MSC receive interrupt flag register (ENET_MSC_RINTF) .........................................1094
27.4.25. MSC transmit interrupt flag register (ENET_MSC_TINTF) ........................................1095
27.4.26. MSC receive interrupt mask register (ENET_MSC_RINTMSK)..................................1096
27.4.27. MSC transmit interrupt mask register (ENET_MSC_TINTMSK).................................1097
27.4.28. MSC transmitted good frames after a single collision counter register (ENET_MSC_SCCNT)
1097
27.4.29. MSC transmitted good frames after more than a single collision counter register
(ENET_MSC_MSCCNT) ..................................................................................................1098
27.4.30. MSC transmitted good frames counter register (ENET_MSC_TGFCNT).....................1098
27.4.31. MSC received frames with CRC error counter register (ENET_MSC_RFCECNT).........1099
27.4.32. MSC received frames with alignment error counter register (ENET_MSC_RFAECNT) ..1099
27.4.33. MSC received good unicast frames counter register (ENET_MSC_RGUFCNT) ........... 1100
27.4.34. PTP time stamp control register (ENET_PTP_TSCTL)............................................. 1100
27.4.35. PTP subsecond increment register (ENET_PTP_SSINC) ......................................... 1103
27.4.36. PTP time stamp high register (ENET_PTP_TSH).................................................... 1103
27.4.37. PTP time stamp low register (ENET_PTP_TSL)...................................................... 1104
27.4.38. PTP time stamp update high register (ENET_PTP_TSUH) ....................................... 1104
27.4.39. PTP time stamp update low register (ENET_PTP_TSUL)......................................... 1105
27.4.40. PTP time stamp addend register (ENET_PTP_TSADDEND)..................................... 1105
27.4.41. PTP expected time high register (ENET_PTP_ETH)................................................ 1106
27.4.42. PTP expected time low register (ENET_PTP_ETL).................................................. 1106
27.4.43. PTP time stamp flag register (ENET_PTP_TSF) ..................................................... 1106
27.4.44. PTP PPS control register (ENET_PTP_PPSCTL).................................................... 1107
27.4.45. DMA bus control register (ENET_DMA_BCTL) ....................................................... 1107
27.4.46. DMA transmit poll enable register (ENET_DMA_TPEN) ............................................1110
27.4.47. DMA receive poll enable register (ENET_DMA_RPEN).............................................1110
27.4.48. DMA receive descriptor table address register (ENET_DMA_RDTADDR) ....................1111
27.4.49. DMA transmit descriptor table address register (ENET_DMA_TDTADDR)....................1111
27.4.50. DMA status register (ENET_DMA_STAT)................................................................1112
27.4.51. DMA control register (ENET_DMA_CTL) ................................................................1115
27.4.52. DMA interrupt enable register (ENET_DMA_INTEN).................................................1118
27.4.53. DMA missed frame and buffer overflow counter register (ENET_DMA_MFBOCNT)...... 1120
27.4.54. DMA receive state watchdog counter register (ENET_DMA_RSWDC)........................ 1121
27.4.55. DMA current transmit descriptor address register (ENET_DMA_CTDADDR) ............... 1121
27.4.56. DMA current receive descriptor address register (ENET_DMA_CRDADDR)................ 1122
27.4.57. DMA current transmit buffer address register (ENET_DMA_CTBADDR)..................... 1122
27.4.58. DMA current receive buffer address register (ENET_DMA_CRBADDR)...................... 1123
28.Universal Serial Bus full-speed device interface (USBD).............................. 1124
28.1. Overview .......................................................................................................... 1124

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28.2. Main features ................................................................................................... 1124
28.3. Block diagram.................................................................................................. 1125
28.4. Signal description............................................................................................ 1125
28.5. Clock configuration ......................................................................................... 1125
28.6. Function overview ........................................................................................... 1126
28.6.1. USB endpoints................................................................................................... 1126
28.6.2. Operation procedure........................................................................................... 1129
28.6.3. USB events and interrupts................................................................................... 1131
28.6.4. Operation guide................................................................................................. 1133
28.7. Registers definition.......................................................................................... 1135
28.7.1. USBD control register (USBD_CTL)...................................................................... 1135
28.7.2. USBD interrupt flag register (USBD_INTF)............................................................. 1136
28.7.3. USBD status register (USBD_STAT) ..................................................................... 1138
28.7.4. USBD device address register (USBD_DADDR)..................................................... 1138
28.7.5. USBD buffer address register (USBD_BADDR) ...................................................... 1139
28.7.6. USBD endpoint x control and status register (USBD_EPxCS), x=[0..7] ....................... 1139
28.7.7. USBD endpoint x transmission buffer address register (USBD_EPxTBADDR), x can be in
[0..7] 1141
28.7.8. USBD endpoint x transmission buffer byte count register (USBD_EPxTBCNT), x can be in
[0..7] 1141
28.7.9. USBD endpoint x reception buffer address register (USBD_EPxRBADDR), x can be in
[0..7] 1142
28.7.10. USBD endpoint x reception buffer byte count register (USBD_EPxRBCNT), x can be in
[0..7] 1142
28.7.11. USBD LPM control and status register (USBD_LPMCS) .......................................... 1143
29. Universal serial bus High-Speed interface (USBHS)...................................... 1144
29.1. Overview .......................................................................................................... 1144
29.2. Characteristics................................................................................................. 1144
29.3. Block diagram.................................................................................................. 1145
29.4. Signal description............................................................................................ 1145
29.5. Function overview ........................................................................................... 1146
29.5.1. USBHS PHY selection, clocks and working modes.................................................. 1146
29.5.2. USB host function .............................................................................................. 1149
29.5.3. USB device function........................................................................................... 1151
29.5.4. OTG function overview........................................................................................ 1153
29.5.5. Data FIFO......................................................................................................... 1154
29.5.6. DMA function..................................................................................................... 1157
29.5.7. Operation guide................................................................................................. 1158
29.6. Interrupts.......................................................................................................... 1164

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29.7. Register definition ........................................................................................... 1167
29.7.1. USBHS global registers....................................................................................... 1167
29.7.2. Host control and status registers........................................................................... 1196
29.7.3. Device control and status registers .......................................................................1210
29.7.4. Power and clock control register (USBHS_PWRCLKCTL) ........................................1239
30. Appendix ...............................................................................................................1241
30.1. List of abbreviations used in register .............................................................1241
30.2. List of terms.....................................................................................................1241
30.3. Available peripherals.......................................................................................1242
31. Revision history ...................................................................................................1243