GOWIN DK-GoAI-GW2AR18QN88P User manual

DK-GoAI-GW2AR18QN88P_V1.1
User Guide
DBUG377-1.0E, 08/17/2020

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preliminary. GOWINSEMI may make changes to this document at any time without prior
notice. Anyone relying on this documentation should contact GOWINSEMI for the current
documentation and errata.

Revision History
Date
Version
Description
08/17/2020
1.0E
Initial version published.

Contents
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Contents
Contents ............................................................................................................... i
List of Figures.................................................................................................... iii
List of Tables...................................................................................................... iv
1About This Guide ............................................................................................ 1
1.1 Purpose..........................................................................................................................1
1.2 Supported Products ........................................................................................................1
1.3 Related Documents ........................................................................................................1
1.4 Terminology and Abbreviations........................................................................................2
1.5 Support and Feedback....................................................................................................3
2Introduction ..................................................................................................... 4
2.1 Overview ........................................................................................................................4
2.2 Development Kit .............................................................................................................5
2.3 PCB Components...........................................................................................................6
2.4 System Block Diagram....................................................................................................7
2.5 Features .........................................................................................................................7
2.6 Development Board Description......................................................................................8
3Development Board Circuit.......................................................................... 10
3.1 FPGA Module ...............................................................................................................10
3.2 Download .....................................................................................................................10
3.2.1 Overview ...................................................................................................................10
3.2.2 USB Download Circuit................................................................................................11
3.2.3 Download Flow ..........................................................................................................11
3.2.4 Pinout ........................................................................................................................11
3.3 Power Supply ...............................................................................................................11
3.3.1 Overview ...................................................................................................................11
3.3.2 Power System Distribution .........................................................................................12
3.3.3 FPGA Power Pinout ...................................................................................................13

Contents
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3.4 Clock, Reset .................................................................................................................13
3.4.1 Overview ...................................................................................................................13
3.4.2 Clock, Reset Circuit ...................................................................................................14
3.4.3 Pinout ........................................................................................................................14
3.5 LED ..............................................................................................................................14
3.5.1 Overview ...................................................................................................................14
3.5.2 LED Circuit ................................................................................................................15
3.5.3 Pinout ........................................................................................................................15
3.6 GPIO ............................................................................................................................15
3.6.1 Overview ...................................................................................................................15
3.6.2 Pinout ........................................................................................................................16
3.7 FPC Connector.............................................................................................................16
3.7.1 Overview ...................................................................................................................16
3.7.2 FPC Circuit ................................................................................................................16
3.7.3 Pinout ........................................................................................................................17
3.8 HDMI............................................................................................................................18
3.8.1 Overview ...................................................................................................................18
3.8.2 HDMI Circuit ..............................................................................................................18
3.8.3 Pinout ........................................................................................................................19
4Notes .............................................................................................................. 20
5Gowin Software ............................................................................................. 21

List of Figures
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List of Figures
Figure 2-1 DK-GoAI-GW2AR18QN88P_V1.1 Development Board.................................................4
Figure 2-2 A Development Kit ........................................................................................................5
Figure 2-3 PCB Components.........................................................................................................6
Figure 2-4 System Block Diagram..................................................................................................7
Figure 3-1 Connection Diagram for FPGA USB Download .............................................................11
Figure 3-2 Power System Distribution ............................................................................................12
Figure 3-3 Clock, Reset Circuit ......................................................................................................14
Figure 3-4 LED Circuit ...................................................................................................................15
Figure 3-5 FPC Circuit ...................................................................................................................16
Figure 3-6 HDMI Connection Diagram ...........................................................................................18

List of Tables
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List of Tables
Table 1-1 Terminology and Abbreviations .......................................................................................2
Table 2-1 Development Board Description .....................................................................................8
Table 3-1 FPGA Download Pinout..................................................................................................11
Table 3-2 FPGA Power Pinout .......................................................................................................13
Table 3-3 FPGA Clock and Reset Pinout........................................................................................14
Table 3-4 LED Pinout.....................................................................................................................15
Table 3-5 GPIO Pinout...................................................................................................................16
Table 3-6 FPC Pinout.....................................................................................................................17
Table 3-7 HDMI_TX Pinout ............................................................................................................19
Table 3-8 HDMI_RX Pinout............................................................................................................19

1 About This Guide
1.1 Purpose
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1About This Guide
1.1 Purpose
DK-GoAI-GW2AR18QN88P_V1.1 user guide consists of the following
four parts:
1. A brief introduction to the features and hardware resources of the
development board;
2. An introduction to the function, circuit, and pinout of each module;
3. Notes for the use of the development board;
4. An introduction to the usage of the FPGA development software.
1.2 Supported Products
The information in the guide applies to GW1N2AR series of FPGA
products: GW2AR-18.
1.3 Related Documents
You can find the related documents at www.gowinsemi.com:
1. DS226, GW2AR series of FPGA Products Data Sheet
2. UG229, GW2AR series of FPGA Products Package and Pinout User
Guide
3. UG115, GW2AR-18 Pinout
4. UG290, Gowin FPGA Products Programming and Configuration User
Guide
5. SUG100, Gowin Software User Guide

1 About This Guide
1.4 Terminology and Abbreviations
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1.4 Terminology and Abbreviations
The terminology and abbreviations used in this manual are as shown
in Table 1-1.
Table 1-1 Terminology and Abbreviations
Te r minology and Abbreviations Meaning
FPGA Field Programmable Gate Array
SIP System in Package
SDRAM Synchronous Dynamic RAM
CFU Configurable Function Unit
CLS Configurable Logic Slice
CRU Configurable Routing Unit
LUT4 Four-input Look-up Tables
LUT5 Five-input Look-up Tables
LUT6 Six-input Look-up Tables
LUT7 Seven-input Look-up Tables
LUT8 Eight-input Look-up Tables
REG Register
ALU Arithmetic Logic Unit
IOB IOB
S-SRAM Shadow Static Random Access Memory
B-SRAM Block Static Random Access Memory
SP Single Port
SDP Semi Dual Port
DP Dual Port
DSP Digital Signal Processing
TDM Time Division Multiplexing
DQCE Dynamic Quadrant Clock Enable
DCS Dynamic Clock Selector
PLL PLL
DLL DLL
QN88 QFN88

1 About This Guide
1.5 Support and Feedback
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1.5 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly by the following ways.
Website: www.gowinsemi.com
E-mail: [e-mail]

2 Introduction
2.1 Overview
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2Introduction
2.1 Overview
Figure 2-1 DK-GoAI-GW2AR18QN88P_V1.1 Development Board
This board uses the GW2AR-18 device with embedded 64 Mbit
PSRAM. The GW2AR series of FPGA products are the first generation
products of the Arora®family. They offer a SIP chip. The main difference
between the GW2A series and the GW2AR series is that the GW2AR
series integrates abundant memories. The GW2AR series also provides
high-performance DSP resources, high-speed LVDS interfaces, and
abundant BSRAM resources. These embedded resources in combination
with a streamlined FPGA architecture with 55nm process make the
GW2AR series of FPGA products suitable for high-speed and low-cost
applications.
The development board offers abundant external interfaces including
camera, HDMI interfaces. There are also LED, reset, clock and other

2 Introduction
2.2 Development Kit
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resources for developers or learners to use.
2.2 Development Kit
The development board kit includes the following items:
DK-GoAI-GW2AR18QN88P_V1.1 development board
USB Cable
Quick Start Guide
Figure 2-2 A Development Kit
4
1
23
①Gowin DK-GoAI-GW2AR18QN88P_V1.1
Development Board
②USB Cable
③DC5V Power Adaptor
④Quick Start Guide

2 Introduction
2.3 PCB Components
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2.3 PCB Components
Figure 2-3 PCB Components
5V Power Outlet
Power Switch
FPGA
HDMI RX
Fla sh
LED Camera
Reset Key
3.3V, 1.8V Power Supply
2.5V、1.2V Power Supply
2.8V Power Supply
USB
USB to JTAG Chip
Crystal Oscillator
HDMI TX
1.0V Power Supply

2 Introduction
2.4 System Block Diagram
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2.4 System Block Diagram
Figure 2-4 System Block Diagram
4*LED
OSC
50MHz
1*RST
1*Camera(FPC
connector)
6*LED
OSC
27MHZ
1*HDMI(TX)
1*HDMI(RX)
Power
1.0V/1.2V/1.8V/2.5V/2.8V/3.3V
GW2AR-
LV18QN88P
MINI USB
1*64Mbit
SPI Flash
FT232HL
DC POWER
JACK
SWITCH
5V 5V
2.5 Features
The features of the development board are as follows:
1. FPGA
QN48 package
Up to 66 user I/O
Abundant LUT4 resources
Multiple modes and capacities of B-SRAM
2. FPGA Configuration Modes
JTAG

2 Introduction
2.6 Development Board Description
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3. MSPI
4. Clock resource
27MHz Clock Crystal Oscillator
5. Key
One reset key
One power key
6. LED
One power indicator (green)
Two HDMI hot-plug indicators (green)
Six LEDs (green)
7. Memory
64Mbit embedded PSRAM
64Mbit external SPI flash
8. GPIO
5 extended I/Os
9. HDMI
One HDMI TX Interface
One HDMI RX Interface
10. DC-DC(LDO) Power
3.3 V, 2.8V, 2.5V, 1.8V,1.2V and 1.0V supported
2.6 Development Board Description
Table 2-1 Development Board Description
No. Name Functional Description Conditions Remarks
1 FPGA Core chip – –
2 Download USB interface; JTAG
and MSPI supported USB to JTAG chip integrated on board –
3 Power Supply
3.3 V, 2.8V, 2.5V,
1.8V,1.2 V, 1.0V output
via DC-DC(LDO) circuit
Input power: 5V
Provide power for FPGA, download,
HDMI and other circuits via 5V to 3.3
V circuit;
Provide power for camera input via
5V to 2.8V circuit;
Provide power for FPGA and HDMI
RX via 5V to 2.5V circuit;
Provide power for FPGA PSRAM via
5V to1.8V circuit;
Provide power for camera input via
5V to 1.2V circuit;
–

2 Introduction
2.6 Development Board Description
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No. Name Functional Description Conditions Remarks

Provide power for FPGA via 5 V to
1.0 V circuit.
4 Switch FPGA Power switch 1 –
5 Reset key FPGA reset key 1 –
6 LED
Test indicator, hot plug
indicator and power
indicator
Six test indicators, green;
Two hot plug indicators, green;

One power indicator, green.
–
7
Crystal
Oscillator
Provide 27MHz clock
for FPGA Package2520 –
8 Memory Provide PSRAM and
Flash
64Mbit embedded PSRAM
64Mbit external SPI flash –
9 GPIO I/O for user to extend
and test
5 –
10 HDMI For design use.
One HDMI TX Interface and one HDMI
RX Interface –
11
FPC
connector For camera input 24PIN FPC –
12 Protection
USB interface with
ESD protection;
Power interface
with inverse and
over current
protection;
HDMI interface
with ESD
protection.
USB interface with ESD protection:
±15kV non-contact discharge and ±
8kV contact discharge;
Schottky diode is connected
between positive and negative
anodes of power interface;
2A self-recovery fuses are
connected at power input
HDMI interface with ESD protection:
±15kV non-contact discharge and ±
8kV contact discharge;
–
13 Voltage – Input Voltage: 5V –
14 Humidity – 95% –
15 Temperature – Operating range: -40°~85° –

3 Development Board Circuit
3.1 FPGA Module
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3Development Board Circuit
3.1 FPGA Module
Overview
For the resources of GW1NSR series of FPGA Products, please refer
to DS226, GW2AR series of FPGA products.
I/O BANK Introduction
For the I/O BANK, package and pinout information, see UG229,
GW2AR Series of FPGA Products for more details.
3.2 Download
3.2.1 Overview
The development board provides an USB download interface. The
bitstream file can be downloaded to the internal SRAM, or the external SPI
flash as needed.
Note!
When downloaded to SRAM, the bitstream file will be lost if the device is powered
down, and it will need to be downloaded again after power-on.
If downloaded to SPI flash, the bitstream file will not be lost if the device is powered
down.

3 Development Board Circuit
3.3 Power Supply
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3.2.2 USB Download Circuit
Figure 3-1 Connection Diagram for FPGA USB Download
F_TMS
F_TCK
F_TDI
F_TDO
USB to JTAG
Chip
USB_D+
USB_D-
14
13
16
18
U1
U9
GW2AR-
LV18QN88P
3.2.3 Download Flow
1. FPGA SRAM Download Mode:
Plug the USB cable to the USB interface (J2) on the development
board. Power on, then open the Programmer, select SRAM mode, and
then select the bitstream file you required.
2. FPGA MSPI Download Mode:
Plug the USB cable to the USB interface (J2) on the development
board, then power on. Open the Programmer, select External Flash
mode, and then select the bitstream file and FLASH you required. Turn
off the power after downloading. Power on, and then the device will
import the bitstream file to SRAM from the external Flash.
3.2.4 Pinout
Table 3-1 FPGA Download Pinout
Name
Pin No.
BANK
Description
I/O Level
TMS 5 2 JTAG Signal 1.8V
TCK 6 2 JTAG Signal 1.8V
TDI 7 2 JTAG Signal 1.8V
TDO 8 2 JTAG Signal 1.8V
MODE0
88
3 Mode selection pin 3.3V
MODE1
87
3 Mode selection pin 3.3V
3.3 Power Supply
3.3.1 Overview
DC5V is input by USB interface. The TI LDO and ONSEMI DC-DC
power supply chip are used to step down voltage from 5V to 3.3V, 2.8V,
2.5V, 1.8V, 1.2V and 1.0V, which can meet the power demands of the

3 Development Board Circuit
3.3 Power Supply
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development board.
3.3.2 Power System Distribution
Figure 3-2 Power System Distribution
DC5V Input
PAM2306AYPA
DC-DC
2.5V
PAM2306AYPA
DC-DC
3.3V
PAM2306AYPA
DC-DC
1.8V
USB to JTAG
（FT2232）
FPGA
VCCO3&VCCX&VCC
O1&VCCO6
27Mhzclock &
FPGA reset
LED
FPGA
VCCO2&VCCO7
(PSRAM)
HDMI
HDMI & FPC
connector & MSPI
FPGA
VCCO0&VCCO5
TPS7A7001
LDO
1.0V
FPGA
VCC&VCCPLL
PAM2306AYPA
DC-DC
2.8V
FPC Connector
PAM2306AYPA
DC-DC
1.2V
FPC Connector

3 Development Board Circuit
3.4 Clock, Reset
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3.3.3 FPGA Power Pinout
Table 3-2 FPGA Power Pinout
Name Pin No. BANK Description I/O Level
VCCO0 78 0 I/O Bank Voltage 2.5V
VCCO1 12, 67 1 I/O Bank Voltage 3.3V
VCCO2 3, 64 2 I/O Bank Voltage 1.8V
VCCO3 58 3 I/O Bank Voltage 3.3V
VCCO4 44 4 I/O Bank Voltage 3.3V
VCCO5 23 5 I/O Bank Voltage 2.5V
VCCO6 12, 67 6 I/O Bank Voltage 3.3V
VCCO7 3, 64 7 I/O Bank Voltage 1.8V
VCCPLLL1 14 - PLLL1 power 1.0V
VCCPLLR1 50 - PLLR1 power 1.0V
VCCX 12, 67 -
Auxiliary voltage
and VCCO1, VCCO6
are internal
connected.
3.3V
VCC
1, 22, 45,
66 - Core voltage 1.0V
VSS
2, 21, 24,
43, 46, 65,
68
- GND -
3.4 Clock, Reset
3.4.1 Overview
The development board provides a 27MHz crystal oscillator connected
to the PLL input pin. This can be employed as the input clock for the PLL in
FPGA. Frequency division and multiplication of PLL can provide the clock
required by the user.
For easier debugging, one reset signal active-low, is added on the
development board.