GOWIN GW1N Series User manual

DK_START_GW1N-LV4LQ144C6I5_V1.1
User Guide
DBUG353-1.06E, 01/06/2021

Copyright© 2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
No part of this document may be reproduced or transmitted in any form or by any denotes,
electronic, mechanical, photocopying, recording or otherwise, without the prior written
consent of GOWINSEMI.
Disclaimer
GOWINSEMI®, LittleBee®,Arora, and the GOWINSEMI logos are trademarks of
GOWINSEMI and are registered in China, the U.S. Patent and Trademark Office and other
countries. All other words and logos identified as trademarks or service marks are the
property of their respective holders, as described at www.gowinsemi.com. GOWINSEMI
assumes no liability and provides no warranty (either expressed or implied) and is not
responsible for any damage incurred to your hardware, software, data, or property resulting
from usage of the materials or intellectual property except as outlined in the GOWINSEMI
Terms and Conditions of Sale. All information in this document should be treated as
preliminary. GOWINSEMI may make changes to this document at any time without prior
notice. Anyone relying on this documentation should contact GOWINSEMI for the current
documentation and errata.

Revision History
Date
Version
Description
6/13/2017
1.00E
Initial version published.
7/18/2017
1.01E
Precautions for using development board and selection
range of MSPI download rate added.
11/20/2017
1.02E
Notes for GW1N-1, GW1N-4/4B, and GW1N-9 updated.
8/29/2018
1.03E
DK_START_GW1N-LV4LQ144C6I5_V1.1 circuit diagrams
updated.
12/20/2018
1.04E
Power pins distribution modified;
Further details about Bank power supply requirements
added.
04/23/2019
1.05E
Supported Products updated.
01/06/2021
1.06E
The name of the board updated;
The description of chapter 3.1 FPGA Module updated.

Contents
DBUG353-1.06E
i
Contents
Contents...............................................................................................................i
List of Figures....................................................................................................iii
List of Tables......................................................................................................iv
1About This Guide ..........................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Supported Products............................................................................................................1
1.3 Related Documents............................................................................................................1
1.4 Abbreviations and Terminology...........................................................................................2
1.5 Support and Feedback .......................................................................................................2
2Development Board Description..................................................................3
2.1 Overview............................................................................................................................. 3
2.2 A Development Board Kit.................................................................................................... 4
2.3 PCB Components............................................................................................................... 5
2.4 System Architecture............................................................................................................6
2.5 Features.............................................................................................................................. 6
2.6 Development Board Specification ......................................................................................7
3FPGA Circuits................................................................................................9
3.1 FPGA Module ..................................................................................................................... 9
3.2 Download Interface............................................................................................................. 9
3.2.1 Overview.......................................................................................................................... 9
3.2.2 USB Download Circuit...................................................................................................10
3.2.3 Downloading the Data Stream.......................................................................................10
3.2.4 Pins Distribution............................................................................................................. 11
3.3 Power Supply.................................................................................................................... 11
3.3.1 Overview........................................................................................................................ 11

Contents
DBUG353-1.06E
ii
3.3.2 Power System Distribution ............................................................................................12
3.3.3 Power Pins Distribution .................................................................................................12
3.4 Clock, Reset ..................................................................................................................... 13
3.4.1 Overview........................................................................................................................13
3.4.2 Clock, Reset ..................................................................................................................13
3.4.3 Pins Distribution.............................................................................................................14
3.5 LED...................................................................................................................................14
3.5.1 Overview........................................................................................................................14
3.5.2 LED Circuit.....................................................................................................................14
3.5.3 Pins Distribution.............................................................................................................14
3.6 Switches ........................................................................................................................... 15
3.6.1 Overview........................................................................................................................15
3.6.2 Key Switch Circuit..........................................................................................................15
3.6.3 Pins Distribution.............................................................................................................15
3.7 Key....................................................................................................................................16
3.7.1 Overview........................................................................................................................16
3.7.2 Key Circuit .....................................................................................................................16
3.7.3 Pins Distribution.............................................................................................................16
3.8 GPIO.................................................................................................................................16
3.8.1 Overview........................................................................................................................16
3.8.2 GPIO Circuit................................................................................................................... 17
3.8.3 Pins Distribution.............................................................................................................17
3.9 LVDS................................................................................................................................. 20
3.9.1 Overview........................................................................................................................20
3.9.2 LVDS Circuit ..................................................................................................................20
3.9.3 Pins Distribution.............................................................................................................20
4Notes ............................................................................................................23
5Gowin Software...........................................................................................25

List of Figures
DBUG353-1.06E
iii
List of Figures
Figure 2-1 DK_START_GW1N-LV4LQ144C6I5_V1.1.......................................................................3
Figure 2-2 A Development Board Kit ................................................................................................. 4
Figure 2-3 PCB Components.............................................................................................................5
Figure 2-4 System Architecture.......................................................................................................... 6
Figure 3-3 Connection Diagram for FPGA USB Downloading and Configuration.............................10
Figure 3-4 Power System Distribution ............................................................................................... 12
Figure 3-5 Clock, Reset..................................................................................................................... 13
Figure 3-6 LED Circuit .......................................................................................................................14
Figure 3-7 Key Switch Circuit............................................................................................................. 15
Figure 3-8 Key Circuit Diagram.......................................................................................................... 16
Figure 3-9 GPIO Circuit ..................................................................................................................... 17
Figure 3-10 LVDS Circuit ................................................................................................................... 20
Figure 4-1 Download Speed..............................................................................................................23

List of Tables
DBUG353-1.06E
iv
List of Tables
Table 1-1 Abbreviations and Terminologies ....................................................................................... 2
Table 2-1 Development Board Specification...................................................................................... 7
Table 3-3 FPGA Download and Pins Distribution ..............................................................................11
Table 3-4 GW1N-4 FPGA Power Pins Distribution............................................................................ 12
Table 3-5 FPGA Clock and Reset Pins Distribution...........................................................................14
Table 3-6 LED Pins Distribution.........................................................................................................14
Table 3-7 Clock Circuit Pins Distribution............................................................................................15
Table 3-8 Key Pins Distribution.......................................................................................................... 16
Table 3-9 J8 FPGA Pin Distribution.................................................................................................... 17
Table 3-10 J9 FPGA Pin Distribution.................................................................................................. 19
Table 3-11 J10 FPGA Pin Distribution................................................................................................20
Table 3-12 J10 FPGA Pin Distribution ............................................................................................... 21

1About This Guide
1.1Purpose
DBUG353-1.06E
1(25)
1About This Guide
1.1 Purpose
The DK_START_GW1N-LV4LQ144C6I5_V1.1 user manual consists
of the following four parts:
A brief introduction to the features and hardware resources of the
development board;
An introduction to the hardware circuits functions, circuit, and pins
distribution;
Notes for using the development board;
Introduction to the use of the FPGA development software.
1.2 Supported Products
The information in the guide applies to GW1N series of FPGA products:
GW1N-4.
1.3 Related Documents
The latest user guides are available on the GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
DS100, GW1N series of FPGA Products Data Sheet
UG103, GW1N series of FPGA Products Package and Pinout
UG105, GW1N-4 Pinout
UG290, Gowin FPGA Products Programming and Configuration User
Guide
SUG100, Gowin Software User Guide

1About This Guide
1.4Abbreviations and Terminology
DBUG353-1.06E
2(25)
1.4 Abbreviations and Terminology
The abbreviations and terminology used in this manual are set out in
Table 1-1 below.
Table 1-1 Abbreviations and Terminologies
Abbreviations and Terminology
Full Name
FPGA
Field Programmable GateArray
LED
Light Emitting Diode
LDO
Low Dropout Regulator
GPIO
Gowin Programmable I/O
LUT4
Four-input Look-up Tables
SSRAM
Shadow Static Random Access Memory
BSRAM
Block Static Random Access Memory
PLL
Phase-locked Loop
DLL
Delay-locked Loop
DSP
Digital Signal Processing
LQ144
LQFP144
1.5 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly using the information provided below.
Website: www.gowinsemi.com
E-mail: [email protected]

2Development Board Description
2.1Overview
DBUG353-1.06E
3(25)
2Development Board Description
2.1 Overview
Figure 2-1 DK_START_GW1N-LV4LQ144C6I5_V1.1
The Development board adopts the GW1N-LV4/4BLQ144 devices of
the GW1N series of FPGA products. It features a range of advanced
features including low power consumption, instant start-up, high security,
low-cost, and flexible extensions, all of which can effectively reduce the
learning cost and help users quickly design and develop programmable
logic devices.
The development board includes two GPIO ports and two LVDS ports.
These provide users with a hardware evaluation and testing platform that
offers a high integration level and stable performance via flexible VCCO
regulation (3.3 V, 2.5 V, and 1.2 V). The development board also offers

2Development Board Description
2.2A Development Board Kit
DBUG353-1.06E
4(25)
slide switches, key switches, a clock, and LEDs, all of which are useful for
both developers and hobbyists alike.
With abundant GPIO resources, the development board can be used
as the main board to design an image-sampling system and the other
related systems by combining video daughter boards. Motion control
systems can also be designed by combining the development board with
AD/DA industrial daughter boards, while human-computer interface and
image processing can be realized by combining the development board
with the display daughter board.
2.2 A Development Board Kit
A development board suite includes the following items:
DK_START_GW1N-LV4LQ144C6I5_V1.1 V1.1
5V power adapter (220V input, DC 5V 2Aoutput)
USB cable
Quick Start
Figure 2-2 A Development Board Kit
①DK_START_GW1N-LV4LQ144C6I5_V1.1
②5V power adapter
③USB cable
④Quick Start Guide

2Development Board Description
2.3PCB Components
DBUG353-1.06E
5(25)
2.3 PCB Components
Figure 2-3 PCB Components

2Development Board Description
2.4System Architecture
DBUG353-1.06E
6(25)
2.4 System Architecture
Figure 2-4 System Architecture
MODE
LEDSwitch
Crystal
Oscillator
JTAG
External
Clock
DONE
Light
40PIN GPIO
Header
40PIN GPIO
Header
FLASH
Configurat-
ion
X36
X36
Reset
X2 X4 X10 X10
X1
X1
X1 X4 X4 X4
X4
Key
20PIN
LVDS
Header
20PIN
LVDS
Header
X1
2.5 Features
The structure and features of the development board are as follows:
1. FPGA
LQFP144 package
Embedded flash, data not easily lost if power down
Abundant LUT4 resources
Multiple modes and capacities of BSRAM
Supports LV
2. FPGA Configuration Mode
JTAG, AUTO BOOT, MSPI
3. Clock Resources
50MHz clock crystal oscillator;
SMA external clock input
4. Key switch and slide switch
One reset button
Four Key switches
Four Slide switches

2Development Board Description
2.6Development Board Specification
DBUG353-1.06E
7(25)
5. LED
One power indicator (green)
One DONE indicator (green)
Four LEDs (green)
6. Memory
One 64Mbit SPI flash
7. GPIO
72 I/O Resources
8. LDO Power
Inverse voltage protection, overcurrent protection;
Supports 3.3 V, 2.5 V, and1.2V.
2.6 Development Board Specification
Table 2-1 Development Board Specification
No.
Item
Functional Description
Technical Conditions
Comments
1
FPGA
Core chip
–
–
2
Download
Interface
Support USB interface;
Support JTAG,
AUTOBOOT, MSPI
USB-JTAG module on board
–
3
Power
Supply
Provide DC 5V input; 3.3
V, 2.5V and 1.2 V output
via LDO circuit
Input power: 5V
Provide power for FPGA, download
circuit and other circuits via 5V–3.3
V circuit;
Provide power for FPGA via 5V–
2.5V circuit;
Provide power to FPGAcore via 3.3
V–1.2 V circuit.
–
4
Slide
Switches
Available for testing
4
–
5
Key
Switches
Available for testing
4
–
6
Reset button
Reset for FPGA
1
–
7
LED
Test indicator, DONE
indicator, Power
indicator
Four Test indicator, green
One DONE indicator, green
One Power indicator, green
–
8
Crystal
Oscillator
Provide 50MHz clock for
FPGA
Package5032
–
9
External
Clock
Input external clock
frequency via SMA,
used for testing
–
–
10
GPIO
I/O, convenient for user
extension and test
76 GPIO; Can be adjusted to 3.3V, 2.5V,
and 1.2V IO voltage
–

2Development Board Description
2.6Development Board Specification
DBUG353-1.06E
8(25)
No.
Item
Functional Description
Technical Conditions
Comments
11
LVDS
LVDS, used for testing
Ten pairs
–
12
Protection
USB interface: ESD
protection;
Power interface:
Inverse current and
over current
protection
USB interface ESD protection:
±15kV non-contact discharge, ±8kV
contact discharge;
Schottky diode is connected
between positive and negative
anodes of power outlet;
2A self-recovery fuses are
connected at power inlet
–
13
Voltage
–
Input range: 2.7V~5.5V
–
14
Humidity
–
95%
–
15
Temperatur
e
–
Operating range: –20°~70°
–

3FPGA Circuits
DBUG353-1.06E
9(25)
3FPGA Circuits
3.1 FPGA Module
Overview
For the resources of GW1N series of FPGA Products, please refer to
DS100, GW1N series of FPGA Products Data Sheet
I/O BANK Introduction
For the I/O BANK, package and pinout information, please refer to
UG103, GW1N series of FPGAProducts Package and Pinout
3.2 Download Interface
3.2.1 Overview
The development board provides an USB download interface. The
data stream file can be downloaded to the internal SRAM, internal flash, or
external flash as needed.
Note!
When downloaded to SRAM, the data stream file will be lost if the device is power
down, and it will need to be downloaded again after power-on.
If downloaded to flash, the data stream file will not be lost if the device is powered
down.

3FPGA Circuits
3.2Download Interface
DBUG353-1.06E
10(25)
3.2.2 USB Download Circuit
Figure 3-1 Connection Diagram for FPGA USB Downloading and Configuration
MSPI_CK_A
MSPI_CS_A
MSPI_DI_A
MSPI_DO
93 94 95 96
TMS
TCK
TDI
TDO_A
USB to JTAG
Chip
USB_D+
USB_D- 14
13
16
18
Configure
FLASH
U8
U6
U5
3.2.3 Downloading the Data Stream
The data stream file can be downloaded in the following ways:
SRAM:
Scan the device and download the bit file after powering the device on.
The Done indicator lights up to denote that the download has been
successful.
Note!
The mode is independent of the values of MODE0 and MODE1.
Internal Flash:
Power on and download. After downloading the data stream file
successfully, power down to reset and load the bit file from the internal
Flash, and when the Done indicator lights up to denote that the
download has been successful.
Note!
Before downloading the bit file and the internal starting FLASH, MODE0 and MODE1
need to set to "00".
External Flash Configuration:
Power on and download. Power down to reset and load the bit file from
the external flash. The Done indicator lights up to denote that the
download has been successful.
Note!
When downloading external FLASH, MODE0 and MODE1 both need to set to
"1".
When loading external FLASH, MODE0 and MODE1 need to set to "0" and "1"
respectively.

3FPGA Circuits
3.3Power Supply
DBUG353-1.06E
11(25)
3.2.4 Pins Distribution
Table 3-1 FPGA Download and Pins Distribution
Signal Name
Pin No.
BANK
Description
I/O
TMS
13
3
JTAG Signal
VCCO3
TCK
14
3
JTAG Signal
VCCO3
TDI
16
3
JTAG Signal
VCCO3
TDO_A
18
3
JTAG Signal
VCCO3
MSPI_CK_A
93
1
FLASH signals configuration
VCCO1
MSPI_CS_A
94
1
FLASH signals configuration
VCCO1
MSPI_DI_A
95
1
FLASH signals configuration
VCCO1
MSPI_DO
96
1
FLASH signals configuration
VCCO1
Note！
The VCCO1 of GW1N-4 can only be supplied with 3.3V or 2.5V, optional.
3.3 Power Supply
3.3.1 Overview
The DC5V input power interface has overcurrent and inverse current
protection. The overcurrent limit is 2A.
The TI LDO power supply chip is used to step down voltage from 5V to
3.3V, 3.3V to 2.5V and 3.3V to 1.2V. The power supply can support up to
2A, which can meet the power demand of the development board.

3FPGA Circuits
3.3Power Supply
DBUG353-1.06E
12(25)
3.3.2 Power System Distribution
Figure 3-2 Power System Distribution
5V 2A
Power
Adapter
TPS7A7001
LDO
3.3V 2A
TPS7A7001
LDO
2.5V 2A
VCCO0
(FPGA)
40PIN GPIO
40PIN GPIO
USB to JTAG
（FT2232）
Configure FLASH
(W25Q64)
Key&Switch
TPS7A7001
LDO
1.2V 2A
VCCO1
(FPGA)
VCCO2
(FPGA)
VCCO3
(FPGA)
VCCX
(FPGA)
VCC
(FPGA)
LED*4
3.3.3 Power Pins Distribution
Table 3-2 GW1N-4 FPGA Power Pins Distribution
Signal Name
FPGA Pins No.
BANK
Description
I/O Voltage
VCCO0
109,127
0
I/O Bank Voltage
3.3V/2.5V/1.2V
VCCO1
77,91
1
I/O Bank Voltage
3.3V/2.5V
VCCO2
37,55
2
I/O Bank Voltage
3.3V/2.5V/1.2V
VCCO3
5,19
3
I/O Bank Voltage
3.3V/2.5V/1.2V
VCCX
31,103
-
Auxiliary Voltage
3.3V
VCC
1,36,73,108
-
Core Voltage
1.2V
VSS
2,17,33,35,53,74,
89,105,107,125
-
GND
-

3FPGA Circuits
3.4Clock, Reset
DBUG353-1.06E
13(25)
Note!
The VCCO1 of GW1N-4 can only be supplied with 3.3V or 2.5V, optional.
3.4 Clock, Reset
3.4.1 Overview
A 50MHz crystal oscillator is provided in the development board that
connects to the PLL input pin. This can be employed as the input clock for
the PLL in FPGA, and the output clock as needed via multiplication and
division of the PLL frequency.
To facilitate testing, a SMA socket is reserved on the development
board as the clock input interface. The clock signal is connected to the
FPGA global clock pin.
3.4.2 Clock, Reset
Figure 3-3 Clock, Reset
6
56
92
KEY5
50MHz
ADM811
JC3.660.046
3.3V
FPGA_RST_N
F_CLK_SMA
FPGA_CLK
U6
U7
J7
X2