GOWIN DK START GW2AR18 V1.1 User manual

DK_START_GW2AR18_V1.1
User Guide
DBUG359-1.2E, 09/03/2021

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and is not responsible for any damage incurred to your hardware, software, data, or
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the GOWINSEMI Terms and Conditions of Sale. All information in this document should be
treated as preliminary. GOWINSEMI may make changes to this document at any time
without prior notice. Anyone relying on this documentation should contact GOWINSEMI for
the current documentation and errata.

Revision History
Date
Version
Description
01/15/2019
1.0E
Initial version published.
09/12/2019
1.1E
One precaution added.
09/03/2021
1.2E
The Quick Start in 2.2 A Development Board Suite removed;
The chapter 6 Quick Start added.

Contents
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Contents
Contents ...............................................................................................................i
List of Figures....................................................................................................iii
List of Tables......................................................................................................iv
1 About This Guide.............................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents ............................................................................................................1
1.3 Abbreviations and Terminology...........................................................................................1
1.4 Support and Feedback .......................................................................................................2
2 Development Board Description ....................................................................3
2.1 Overview.............................................................................................................................3
2.2 A Development Board Suite................................................................................................ 4
2.3 PCB Components ............................................................................................................... 5
2.4 System Architecture............................................................................................................5
2.5 Features.............................................................................................................................. 6
2.6 Development Board Specification ......................................................................................7
3 Development Board Circuit ............................................................................9
3.1 FPGA Module .....................................................................................................................9
3.1.1 Overview..........................................................................................................................9
3.1.2 I/O BANK Introduction ................................................................................................... 10
3.2 Download.......................................................................................................................... 11
3.2.1 Overview........................................................................................................................ 11
3.2.2 USB Download Circuit ................................................................................................... 11
3.2.3 Download Flow ..............................................................................................................12
3.2.4 Pinout.............................................................................................................................12
3.3 Power Supply....................................................................................................................12
3.3.1 Overview........................................................................................................................12
3.3.2 Power System Distribution ............................................................................................ 13

Contents
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3.3.3 FPGA Power Pinout.......................................................................................................13
3.4 Clock, Reset .....................................................................................................................14
3.4.1 Overview........................................................................................................................14
3.4.2 Clock, Reset ..................................................................................................................14
3.4.3 Pinout.............................................................................................................................15
3.5 LED ...................................................................................................................................15
3.5.1 Overview........................................................................................................................15
3.5.2 LED Circuit.....................................................................................................................15
3.5.3 Pinout.............................................................................................................................15
3.6 Switches ...........................................................................................................................16
3.6.1 Overview........................................................................................................................16
3.6.2 Switch Circuit .................................................................................................................16
3.6.3 Pins Distribution.............................................................................................................16
3.7 Key.................................................................................................................................... 16
3.7.1 Overview........................................................................................................................16
3.7.2 Key Circuit .....................................................................................................................17
3.7.3 Pinout.............................................................................................................................17
3.8 GPIO .................................................................................................................................17
3.8.1 Overview........................................................................................................................17
3.8.2 GPIO Circuit...................................................................................................................18
3.8.3 Pinout.............................................................................................................................18
3.9 LVDS.................................................................................................................................21
3.9.1 Overview........................................................................................................................21
3.9.2 LVDS Circuit .................................................................................................................. 21
3.9.3 Pinout.............................................................................................................................21
3.10 Ethernet ..........................................................................................................................23
3.10.1 Overview...................................................................................................................... 23
3.10.2 Ethernet Circuit ............................................................................................................ 23
3.10.3 Pinout...........................................................................................................................23
4 Considerations...............................................................................................25
5 Gowin Software..............................................................................................26
6 Quick Start .....................................................................................................27

List of Figures
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List of Figures
Figure 2-1 DK_START_GW2AR18_V1.1 Development Board .........................................................3
Figure 2-2 A Development Board Suite ............................................................................................. 4
Figure 2-3 PCB Components............................................................................................................. 5
Figure 2-4 System Architecture.......................................................................................................... 5
Figure 3-1 GW2AR I/O Bank Distribution .......................................................................................... 10
Figure 3-2 View of GW2AR-18 EQ144 Pinout (Top View).................................................................10
Figure 3-3 Connection Diagram for FPGA USB Downloading ..........................................................11
Figure 3-4 Power System Distribution ...............................................................................................13
Figure 3-5 Clock, Reset .....................................................................................................................14
Figure 3-6 LED Circuit .......................................................................................................................15
Figure 3-7 Switch Circuit.................................................................................................................... 16
Figure 3-8 Key Circuit ........................................................................................................................17
Figure 3-9 GPIO Circuit .....................................................................................................................18
Figure 3-10 LVDS Circuit ................................................................................................................... 21
Figure 3-11 Ethernet Download Connection ...................................................................................... 23

List of Tables
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List of Tables
Table 1-1 Abbreviations and Terminology ..........................................................................................2
Table 2-1 Development Board Specification...................................................................................... 7
Table 3-1 GW2AR-18 FPGA Resources List ..................................................................................... 9
Table 3-2 FPGA I/O Pinout................................................................................................................. 11
Table 3-3 FPGA Download and Pinout .............................................................................................. 12
Table 3-4 FPGA Power Pinout ...........................................................................................................13
Table 3-5 FPGA Clock and Reset Pinout ........................................................................................... 15
Table 3-6 LED Pinout .........................................................................................................................15
Table 3-7 Clock Circuit Pinout............................................................................................................ 16
Table 3-8 Key Pinout.......................................................................................................................... 17
Table 3-9 J5 GPIO Pinout ..................................................................................................................18
Table 3-10 J14 GPIO Pinout .............................................................................................................. 19
Table 3-11 J2 GPIO Pinout ................................................................................................................ 20
Table 3-12 J15 GPIO Pinout .............................................................................................................. 20
Table 3-13 J3 FPGA Pinout................................................................................................................ 21
Table 3-14 J4 FPGA Pinout................................................................................................................ 22
Table 3-15 Ethernet1 Pinout ..............................................................................................................23
Table 3-16 Ethernet2 Pinout ..............................................................................................................24

1 About This Guide
1.1 Purpose
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1About This Guide
1.1 Purpose
The DK_START_GW2AR18_V1.1 Development Board user manual
consists of the following four parts:
1. A brief introduction to the features and hardware resources of the
development board;
2. An introduction to the hardware circuits functions, circuit, and pinout;
3. Consideration for the use of the development board;
4. Introduction to the use of the FPGA development software.
1.2 Related Documents
The latest user guides are available on the GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
1. DS226, GW2AR series of FPGA Products Data Sheet
2. UG229, GW2AR series of FPGA Products Package and Pinout
3. U115, GW2AR-18 Pinout
4. UG290, Gowin FPGA Products Programming and Configuration User
Guide
5. SUG100, Gowin Software User Guide
1.3 Abbreviations and Terminology
The abbreviations and terminology used in this manual are as shown
in Table 1-1 below.

1 About This Guide
1.4 Support and Feedback
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Table 1-1 Abbreviations and Terminology
Abbreviations and Terminology
Full Name
FPGA
Field Programmable Gate Array
SIP
System in Package
SDRAM
Synchronous Dynamic RAM
CFU
Configurable Function Unit
CLS
Configurable Logic Slice
CRU
Configurable Routing Unit
LUT4
4-input Look-up Table
LUT5
5-input Look-up Table
LUT6
6-input Look-up Table
LUT7
7-input Look-up Table
LUT8
8-input Look-up Table
REG
Register
ALU
Arithmetic Logic Unit
IOB
Input/Output Block
S-SRAM
Shadow SRAM
B-SRAM
Block SRAM
SP
Single Port
SDP
Semi Dual Port
DP
Dual Port
DSP
Digital Signal Processing
TDM
Time Division Multiplexing
DQCE
Dynamic Quadrant Clock Enable
DCS
Dynamic Clock Selector
PLL
Phase-locked Loop
DLL
Delay-locked Loop
EQ144
EQFP144
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly using the information provided below.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Development Board Description
2.1 Overview
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2Development Board Description
2.1 Overview
Figure 2-1 DK_START_GW2AR18_V1.1 Development Board
DK-START-GW2AR18 adopts the GW2AR-18 device. 64Mbit PSRAM
is embedded in this device. The GW2AR series of FPGA products are the
first generation products of the Arora family. They offer one form of SIP chip.
The main difference between the GW2A series and the GW2AR series is
that the GW2AR series integrates abundant memories. The GW2AR series
also provides high-performance DSP resources, a high-speed LVDS
interface, and abundant BSRAM resources. These embedded resources in
combination with a streamlined FPGA architecture with 55nm process
make the GW2AR series of FPGA products suitable for high-speed and
low-cost applications.
The development board offers abundant external interfaces, including
LVDS interfaces, GPIO interfaces, slide switches, key switches, LED, reset,
clock resources, etc.