GOWIN DK START GW2AR18 V1.1 User manual

DK_START_GW2AR18_V1.1
User Guide
DBUG359-1.2E, 09/03/2021

Copyright © 2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
, Gowin, and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor
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GOWINSEMI assumes no liability and provides no warranty (either expressed or implied)
and is not responsible for any damage incurred to your hardware, software, data, or
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the GOWINSEMI Terms and Conditions of Sale. All information in this document should be
treated as preliminary. GOWINSEMI may make changes to this document at any time
without prior notice. Anyone relying on this documentation should contact GOWINSEMI for
the current documentation and errata.

Revision History
Date
Version
Description
01/15/2019
1.0E
Initial version published.
09/12/2019
1.1E
One precaution added.
09/03/2021
1.2E
The Quick Start in 2.2 A Development Board Suite removed;
The chapter 6 Quick Start added.

Contents
DBUG359-1.2E
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Contents
Contents ...............................................................................................................i
List of Figures....................................................................................................iii
List of Tables......................................................................................................iv
1 About This Guide.............................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents ............................................................................................................1
1.3 Abbreviations and Terminology...........................................................................................1
1.4 Support and Feedback .......................................................................................................2
2 Development Board Description ....................................................................3
2.1 Overview.............................................................................................................................3
2.2 A Development Board Suite................................................................................................ 4
2.3 PCB Components ............................................................................................................... 5
2.4 System Architecture............................................................................................................5
2.5 Features.............................................................................................................................. 6
2.6 Development Board Specification ......................................................................................7
3 Development Board Circuit ............................................................................9
3.1 FPGA Module .....................................................................................................................9
3.1.1 Overview..........................................................................................................................9
3.1.2 I/O BANK Introduction ................................................................................................... 10
3.2 Download.......................................................................................................................... 11
3.2.1 Overview........................................................................................................................ 11
3.2.2 USB Download Circuit ................................................................................................... 11
3.2.3 Download Flow ..............................................................................................................12
3.2.4 Pinout.............................................................................................................................12
3.3 Power Supply....................................................................................................................12
3.3.1 Overview........................................................................................................................12
3.3.2 Power System Distribution ............................................................................................ 13

Contents
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3.3.3 FPGA Power Pinout.......................................................................................................13
3.4 Clock, Reset .....................................................................................................................14
3.4.1 Overview........................................................................................................................14
3.4.2 Clock, Reset ..................................................................................................................14
3.4.3 Pinout.............................................................................................................................15
3.5 LED ...................................................................................................................................15
3.5.1 Overview........................................................................................................................15
3.5.2 LED Circuit.....................................................................................................................15
3.5.3 Pinout.............................................................................................................................15
3.6 Switches ...........................................................................................................................16
3.6.1 Overview........................................................................................................................16
3.6.2 Switch Circuit .................................................................................................................16
3.6.3 Pins Distribution.............................................................................................................16
3.7 Key.................................................................................................................................... 16
3.7.1 Overview........................................................................................................................16
3.7.2 Key Circuit .....................................................................................................................17
3.7.3 Pinout.............................................................................................................................17
3.8 GPIO .................................................................................................................................17
3.8.1 Overview........................................................................................................................17
3.8.2 GPIO Circuit...................................................................................................................18
3.8.3 Pinout.............................................................................................................................18
3.9 LVDS.................................................................................................................................21
3.9.1 Overview........................................................................................................................21
3.9.2 LVDS Circuit .................................................................................................................. 21
3.9.3 Pinout.............................................................................................................................21
3.10 Ethernet ..........................................................................................................................23
3.10.1 Overview...................................................................................................................... 23
3.10.2 Ethernet Circuit ............................................................................................................ 23
3.10.3 Pinout...........................................................................................................................23
4 Considerations...............................................................................................25
5 Gowin Software..............................................................................................26
6 Quick Start .....................................................................................................27

List of Figures
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List of Figures
Figure 2-1 DK_START_GW2AR18_V1.1 Development Board .........................................................3
Figure 2-2 A Development Board Suite ............................................................................................. 4
Figure 2-3 PCB Components............................................................................................................. 5
Figure 2-4 System Architecture.......................................................................................................... 5
Figure 3-1 GW2AR I/O Bank Distribution .......................................................................................... 10
Figure 3-2 View of GW2AR-18 EQ144 Pinout (Top View).................................................................10
Figure 3-3 Connection Diagram for FPGA USB Downloading ..........................................................11
Figure 3-4 Power System Distribution ...............................................................................................13
Figure 3-5 Clock, Reset .....................................................................................................................14
Figure 3-6 LED Circuit .......................................................................................................................15
Figure 3-7 Switch Circuit.................................................................................................................... 16
Figure 3-8 Key Circuit ........................................................................................................................17
Figure 3-9 GPIO Circuit .....................................................................................................................18
Figure 3-10 LVDS Circuit ................................................................................................................... 21
Figure 3-11 Ethernet Download Connection ...................................................................................... 23

List of Tables
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List of Tables
Table 1-1 Abbreviations and Terminology ..........................................................................................2
Table 2-1 Development Board Specification...................................................................................... 7
Table 3-1 GW2AR-18 FPGA Resources List ..................................................................................... 9
Table 3-2 FPGA I/O Pinout................................................................................................................. 11
Table 3-3 FPGA Download and Pinout .............................................................................................. 12
Table 3-4 FPGA Power Pinout ...........................................................................................................13
Table 3-5 FPGA Clock and Reset Pinout ........................................................................................... 15
Table 3-6 LED Pinout .........................................................................................................................15
Table 3-7 Clock Circuit Pinout............................................................................................................ 16
Table 3-8 Key Pinout.......................................................................................................................... 17
Table 3-9 J5 GPIO Pinout ..................................................................................................................18
Table 3-10 J14 GPIO Pinout .............................................................................................................. 19
Table 3-11 J2 GPIO Pinout ................................................................................................................ 20
Table 3-12 J15 GPIO Pinout .............................................................................................................. 20
Table 3-13 J3 FPGA Pinout................................................................................................................ 21
Table 3-14 J4 FPGA Pinout................................................................................................................ 22
Table 3-15 Ethernet1 Pinout ..............................................................................................................23
Table 3-16 Ethernet2 Pinout ..............................................................................................................24

1 About This Guide
1.1 Purpose
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1About This Guide
1.1 Purpose
The DK_START_GW2AR18_V1.1 Development Board user manual
consists of the following four parts:
1. A brief introduction to the features and hardware resources of the
development board;
2. An introduction to the hardware circuits functions, circuit, and pinout;
3. Consideration for the use of the development board;
4. Introduction to the use of the FPGA development software.
1.2 Related Documents
The latest user guides are available on the GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
1. DS226, GW2AR series of FPGA Products Data Sheet
2. UG229, GW2AR series of FPGA Products Package and Pinout
3. U115, GW2AR-18 Pinout
4. UG290, Gowin FPGA Products Programming and Configuration User
Guide
5. SUG100, Gowin Software User Guide
1.3 Abbreviations and Terminology
The abbreviations and terminology used in this manual are as shown
in Table 1-1 below.

1 About This Guide
1.4 Support and Feedback
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Table 1-1 Abbreviations and Terminology
Abbreviations and Terminology
Full Name
FPGA
Field Programmable Gate Array
SIP
System in Package
SDRAM
Synchronous Dynamic RAM
CFU
Configurable Function Unit
CLS
Configurable Logic Slice
CRU
Configurable Routing Unit
LUT4
4-input Look-up Table
LUT5
5-input Look-up Table
LUT6
6-input Look-up Table
LUT7
7-input Look-up Table
LUT8
8-input Look-up Table
REG
Register
ALU
Arithmetic Logic Unit
IOB
Input/Output Block
S-SRAM
Shadow SRAM
B-SRAM
Block SRAM
SP
Single Port
SDP
Semi Dual Port
DP
Dual Port
DSP
Digital Signal Processing
TDM
Time Division Multiplexing
DQCE
Dynamic Quadrant Clock Enable
DCS
Dynamic Clock Selector
PLL
Phase-locked Loop
DLL
Delay-locked Loop
EQ144
EQFP144
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly using the information provided below.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Development Board Description
2.1 Overview
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2Development Board Description
2.1 Overview
Figure 2-1 DK_START_GW2AR18_V1.1 Development Board
DK-START-GW2AR18 adopts the GW2AR-18 device. 64Mbit PSRAM
is embedded in this device. The GW2AR series of FPGA products are the
first generation products of the Arora family. They offer one form of SIP chip.
The main difference between the GW2A series and the GW2AR series is
that the GW2AR series integrates abundant memories. The GW2AR series
also provides high-performance DSP resources, a high-speed LVDS
interface, and abundant BSRAM resources. These embedded resources in
combination with a streamlined FPGA architecture with 55nm process
make the GW2AR series of FPGA products suitable for high-speed and
low-cost applications.
The development board offers abundant external interfaces, including
LVDS interfaces, GPIO interfaces, slide switches, key switches, LED, reset,
clock resources, etc.

2 Development Board Description
2.2 A Development Board Suite
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2.2 A Development Board Suite
A development board suite includes the following items:
DK_START_GW2AR18_V1.1 development board
USB cable
Figure 2-2 A Development Board Suite
1
2
①DK_START_GW2AR18_V1.1
development board
②USB Cale

2 Development Board Description
2.3 PCB Components
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2.3 PCB Components
Figure 2-3 PCB Components
Ethernet
LVDS
KEY
GPIO
1.0V
GPIO
GPIO
GPIO
3.3V
OSC
LED
Switch
Reset
Mode
Control
FPGA
Download
5V IN
FLASH
FPGA
GPIO
LVDS
Power
ON/OFF
Ethernet
1.8V
2.4 System Architecture
Figure 2-4 System Architecture
4*LED
2*SWITCH
OSC
50MHz
MINI USB
5Pairs
LVDS INPUT
2*BUTTON
5Pairs
LVDS OUTPUT
2*10PIN
GPIO
2*Ethernet
FPGA USB Download
Interface
1*26PIN
GPIO
GW2AR18_V1.1
DC5V IN MINI USB
3.3V/1.8V/1.0V
1*20PIN
GPIO

2 Development Board Description
2.5 Features
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2.5 Features
The structure and features of the development board are as follows:
1. FPGA
EQFP144 package
Up to 120 user I/O
Abundant LUT4 resources
Multiple modes and capacities of B-SRAM
2. FPGA Configuration Mode
JTAG
MSPI
Multi BOOT
3. Clock resource
50MHz Clock Crystal Oscillator
4. Key switch and slide switch
One reset button
Two key switches
Two slide switches
5. LED
One power indicator (green)
One DONE indicator (green)
Four LEDs (green)
6. Memory
64Mbit built-in PSRAM
7. LVDS
5 pairs of LVDS differential input; 5 pairs of LVDS differential output
8. GPIO
50 I/O expansion resources
9. Ethernet
2 Ethernet interfaces
10. LDO Power
Supports 3.3 V, 1.8V, and1.0V.

2 Development Board Description
2.6 Development Board Specification
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2.6 Development Board Specification
Table 2-1 Development Board Specification
No.
Item
Functions
Technical Conditions
Note
1
FPGA
Core chip
–
–
2
Download
Support an USB
interface; Support
JTAG, MSPI, and
Multi BOOT
USB-JTAG module on board
–
3
Power Supply
3.3 V, 1.8V and
1.0 V output via
LDO circuit
Input power: 5V
Provide power for FPGA,
download circuit and other
circuits via 5V–3.3V circuit;
Provide power for FPGA
PSRAM via 5V–1.8V circuit;
Provide power for FPGA via
5V–1.0V circuit.
–
4
Slide
Switches
Available for
testing
2
–
5
Key Switches
Available for
testing
2
–
6
Reset button
Reset for FPGA
1
–
7
LED
Test indicator,
DONE indicator,
Power indicator
Four Test indicators, green
One DONE indicator, green
One Power indicator, green
–
8
Crystal
Oscillator
Provide 50MHz
clock for FPGA
Package5032
–
9
Memory
Offers PSRAM
64Mbit built-in PSRAM
–
10
GPIO
I/O, convenient for
user extension and
test
50
–
11
LVDS
LVDS, used for
testing
5 pairs of input, 5 pairs of output
–
12
Ethernet
For design use.
2 Ethernet interfaces
–
13
Protection
USB interface:
ESD protection;
Power interface:
Inverse current
and over current
protection
USB interface ESD
protection: ±15kV
non-contact discharge, ±
8kV contact discharge;
Schottky diode is connected
–

2 Development Board Description
2.6 Development Board Specification
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No.
Item
Functions
Technical Conditions
Note
between positive and
negative anodes of power
outlet;
2A self-recovery fuses are
connected at power inlet
14
Voltage
–
Input Voltage: 5V
–
15
Humidity
–
95%
–
16
Temperature
–
Operating range: –20°~70°
–

3 Development Board Circuit
3.1 FPGA Module
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3Development Board Circuit
3.1 FPGA Module
3.1.1 Overview
The resources of GW2AR series of FPGA products are set out in Table
3-1.
Table 3-1 GW2AR-18 FPGA Resources List
Device
GW2AR-18
LUT4
20,736
Flip-Flop (FF)
15,552
Shadow SRAM
S-SRAM (bits)
41,472
Block SRAM
B-SRAM (bits)
828K
B-SRAM quantity
46
PSRAM(bits)
64M
18 x 18 Multiplier
48
Maximum1(PLLs+DLLs)
4+4
Total number of I/O banks
8
Max. user I/O2
140
Core voltage
1.0V
Note!
See DS226, GW2AR series of FPGA Products Data Sheet for further details.

3 Development Board Circuit
3.1 FPGA Module
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3.1.2 I/O BANK Introduction
There are four I/O Banks in the GW2AR series of FPGA products, as
shown in Figure 3-1.
Figure 3-1 GW2AR I/O Bank Distribution
GW2AR
IO Bank0 IO Bank1
IO Bank2 IO Bank3
IO Bank4IO Bank5
IO Bank6IO Bank7
Figure 3-2 View of GW2AR-18 EQ144 Pinout (Top View)

3 Development Board Circuit
3.2 Download
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Table 3-2 FPGA I/O Pinout
I/O BANK No.
Signals
I/O BANK0
Pins used for download mode selection
LVDS differential input
LED&Reset&Slide switch&Key switch
GPIO
I/O BANK1
LVDS differential input
LVDS differential output
I/O BANK2
JTAG
GPIO
I/O BANK3
DONE&RECONFIG_N&READY
MSPI
GPIO
I/O BANK4
Ethernet
I/O BANK5
GPIO
Ethernet
I/O BANK6
GPIO
I/O BANK7
50MHz clock input
GPIO
3.2 Download
3.2.1 Overview
The development board provides an USB download interface. The
data stream file can be downloaded to the internal SRAM, or the external
flash as needed.
Note!
When downloaded to SRAM, the data stream file will be lost if the device is power
down, and it will need to be downloaded again after power-on.
If downloaded to flash, the data stream file will not be lost if the device is powered
down.
3.2.2 USB Download Circuit
Figure 3-3 Connection Diagram for FPGA USB Downloading
TMS_LQ144
TCK_LQ144
TDI_LQ144
TDO_LQ144
USB-to-JTAG
Chip
USB_D+
USB_D- 14
13
16
18
U9
U4
GW2AR18_V1.1

3 Development Board Circuit
3.3 Power Supply
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3.2.3 Download Flow
1. FPGA SRAM Download Mode:
Plug the USB cable to the USB interface (J26) on the development
board. Power on. Open the Programmer, select SRAM mode, and then
select the bitstream file you required.
2. FPGA MSPI Download Mode:
Plug the USB cable to the USB interface (J26) on the development
board. Set J13 to "0", and set J9 and J10 to "1". Power on. Open the
Programmer, select External Flash mode, and then select the bitstream
file you required. Turn off the power after downloading. Set J13, J9,
and J10 to "0", power on, and then the device will import the bitstream
file to SRAM from the external Flash.
3.2.4 Pinout
Table 3-3 FPGA Download and Pinout
Signal Name
Pin No.
BANK
Description
I/O
TMS
13
2
JTAG Signal
1.8V
TCK
14
2
JTAG Signal
1.8V
TDI
16
2
JTAG Signal
1.8V
TDO
18
2
JTAG Signal
1.8V
MODE0
144
0
One Mode
selection pin
3.3V
MODE1
142
0
One Mode
selection pin
3.3V
MODE2
143
0
One Mode
selection pin
3.3V
RECONFIG_N
20
3
RECONFIG_N
3.3V
DONE
21
3
One DONE
indicator
3.3V
READY
22
3
READY
3.3V
3.3 Power Supply
3.3.1 Overview
DC5V is input by USB interface. The TI LDO power supply chip is used
to step down voltage from 5V to 3.3V, 1.8V and 1.0V, which can meet the
power demand of the development board.

3 Development Board Circuit
3.3 Power Supply
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3.3.2 Power System Distribution
Figure 3-4 Power System Distribution
DC5V
TPS7A7001
LDO
1.0V
TPS7A7001
LDO
3.3V
TPS7A7001
LDO
1.8V
USB-JTAG
（FT2232）
FPGA VCCO0&VCCO1
&VCCO3&VCCO4
&VCCO5&VCCO6&VCCX
Ethernet
LED&SWTICH&BUTTON
FPGA
VCCO2&VCCO7
(PSRAM)
FPGA VCC
3.3.3 FPGA Power Pinout
Table 3-4 FPGA Power Pinout
Signal Name
Pin No.
BANK
Description
I/O
VCCO0
127
0
I/O Bank Power
3.3V
VCCO1
109
1
I/O Bank Power
3.3V
VCCO2
103
2
I/O Bank Power
1.8V
VCCO3
77, 91
3
I/O Bank Power
3.3V
VCCO4
55
4
I/O Bank Power
3.3V
VCCO5
37
5
I/O Bank Power
3.3V
VCCO6
31
6
I/O Bank Power
3.3V
VCCO7
5, 19
7
I/O Bank Power
1.8V