GOWIN DK-START-GW2A55-PG484 User manual

DK-START-GW2A55-PG484 V1.3
Development
BoardDK-START-GW2A55-PG484 V1.3
Development Board
User Guide
DBUG375-1.0E, 04/22/2020

Copyright© 2020 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
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consent of GOWINSEMI.
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responsible for any damage incurred to your hardware, software, data, or property resulting
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Terms and Conditions of Sale. All information in this document should be treated as
preliminary. GOWINSEMI may make changes to this document at any time without prior
notice. Anyone relying on this documentation should contact GOWINSEMI for the current
documentation and errata.

Revision History
Date
Version
Description
04/22/2020
1.0E
Initial version published.

Contents
DBUG375-1.0E
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Contents
Contents...............................................................................................................i
List of Figures....................................................................................................iv
List of Tables......................................................................................................vi
1About This Guide.............................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Supported Products............................................................................................................1
1.3 Related Documents............................................................................................................1
1.4 Terminology and Abbreviations...........................................................................................2
1.5 Support and Feedback .......................................................................................................2
2Introduction......................................................................................................3
2.1 Overview.............................................................................................................................3
2.2 Development Kit ................................................................................................................. 4
2.3 PCB Components............................................................................................................... 5
2.4 System Block Diagram .......................................................................................................6
2.5 Features..............................................................................................................................6
3Development Board Circuit ............................................................................9
3.1 FPGA Module .....................................................................................................................9
3.2 Download Module............................................................................................................... 9
3.2.1 Introduction......................................................................................................................9
3.2.2 Pinout.............................................................................................................................10
3.3 Power Supply.................................................................................................................... 11
3.3.1 Introduction.................................................................................................................... 11
3.4 Clock and Reset ...............................................................................................................12
3.4.1 Introduction....................................................................................................................12
3.4.2 Pinout.............................................................................................................................13

Contents
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3.5 DDR3................................................................................................................................ 13
3.5.1 Introduction....................................................................................................................13
3.5.2 Pinout.............................................................................................................................13
3.6 Ethernet ............................................................................................................................15
3.6.1 Introduction....................................................................................................................15
3.6.2 Pinout.............................................................................................................................16
3.7 LVDS Interfaces................................................................................................................ 16
3.7.1 Introduction....................................................................................................................16
3.7.2 Pinout.............................................................................................................................17
3.8 MIPI DSI ........................................................................................................................... 20
3.8.1 Introduction....................................................................................................................20
3.8.2 Pinout.............................................................................................................................21
3.9 MIPI CSI ........................................................................................................................... 22
3.9.1 Introduction....................................................................................................................22
3.9.2 Pinout.............................................................................................................................23
3.10 SD Card..........................................................................................................................24
3.10.1 Introduction..................................................................................................................24
3.10.2 Pinout...........................................................................................................................25
3.11 RTC.................................................................................................................................25
3.11.1 Introduction ..................................................................................................................25
3.11.2 Pinout........................................................................................................................... 25
3.12 AD/DA.............................................................................................................................26
3.12.1 Introduction..................................................................................................................26
3.12.2 Pinout...........................................................................................................................26
3.13 CAN ................................................................................................................................27
3.13.1 Introduction..................................................................................................................27
3.13.2 Pinout...........................................................................................................................27
3.14 WIFI ................................................................................................................................ 27
3.14.1 Introduction..................................................................................................................27
3.14.2 Pinout...........................................................................................................................28
3.15 GPIO...............................................................................................................................28
3.15.1 Introduction..................................................................................................................28

Contents
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3.15.2 Pinout...........................................................................................................................30
3.16 Industry Screen Interface ............................................................................................... 32
3.16.1 Introduction..................................................................................................................32
3.16.2 Pinout...........................................................................................................................33
3.17 LED Module....................................................................................................................34
3.17.1 Introduction..................................................................................................................34
3.17.2 Pinout...........................................................................................................................34
3.18 Keys Module...................................................................................................................35
3.18.1 Introduction..................................................................................................................35
3.18.2 Pinout...........................................................................................................................35
3.19 Switches Module............................................................................................................. 35
3.19.1 Introduction..................................................................................................................35
3.19.2 Pinout...........................................................................................................................36
4Quick Start .....................................................................................................37
4.1 Install Software.................................................................................................................37
4.2 Development Board Power-on Test..................................................................................37
4.3 Build Demo Program ........................................................................................................37
4.4 Download and Run...........................................................................................................38

List of Figures
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List of Figures
Figure 2-1 DK-START-GW2A55-PG484 V1.3 ................................................................................... 3
Figure 2-2 Development Kit ............................................................................................................... 4
Figure 2-3 PCB Components.............................................................................................................5
Figure 2-4 System Block Diagram..................................................................................................... 6
Figure 3-1 Connection Diagram of FPGA Downloading and Configuration ......................................10
Figure 3-2 Asynchronous FIFO Connection Diagram........................................................................ 10
Figure 3-3 Connection Diagram of Clock and Reset......................................................................... 12
Figure 3-4 Connection Diagram of FPGA and DDR3........................................................................ 13
Figure 3-5 Connection Diagram of FPGA and Ethernet ....................................................................15
Figure 3-6 LVDS TX Interface............................................................................................................ 17
Figure 3-7 LVDS RX Interface ........................................................................................................... 17
Figure 3-8 Connection Diagram of MIPI DSI ..................................................................................... 20
Figure 3-9 Connection Diagram of MIPI CSI ..................................................................................... 23
Figure 3-10 Connection Diagram of SD Card.................................................................................... 24
Figure 3-11 Connection Diagram of RTC........................................................................................... 25
Figure 3-12 Connection Diagram of AD/DA....................................................................................... 26
Figure 3-13 Connection Diagram of CAN.......................................................................................... 27
Figure 3-14 Connection Diagram of WIFI.......................................................................................... 28
Figure 3-15 40pin Diagram ................................................................................................................ 29
Figure 3-16 20pin Diagram ................................................................................................................ 30
Figure 3-17 50pin FPC Interface Diagram......................................................................................... 32
Figure 3-18 LED Connection Diagram............................................................................................... 34
Figure 3-19 Key Circuit Diagram........................................................................................................35
Figure 3-20 Switch Circuit Diagram................................................................................................... 36
Figure 4-1 Design Window.................................................................................................................38

List of Figures
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Figure 4-2 Process Window............................................................................................................... 38
Figure 4-3 Build Completed ............................................................................................................... 38
Figure 4-4 Programmer Window........................................................................................................ 39
Figure 4-5 Device Configure Window................................................................................................ 39
Figure 4-6 Click Program/Configure ..................................................................................................40

List of Tables
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List of Tables
Table 1-1 Abbreviations and Terminology..........................................................................................2
Table 3-1 FPGA Download and Pinout ..............................................................................................10
Table 3-2 Asynchronous FIFO Pinout................................................................................................11
Table 3-3 Clock and Reset Pinout...................................................................................................... 13
Table 3-4 DDR3 Pinout ...................................................................................................................... 13
Table 3-5 Ethernet Pinout .................................................................................................................. 16
Table 3-6 LVDS TX Pinout .................................................................................................................17
Table 3-7 LVDS TX2 Pinout ...............................................................................................................18
Table 3-8 LVDS TX2 Pinout ...............................................................................................................18
Table 3-9 LVDS TX2 Pinout ...............................................................................................................19
Table 3-10 MIPI DSI Pinout................................................................................................................21
Table 3-11 MIPI DSI Pinout................................................................................................................23
Table 3-12 SD Card Pinout ................................................................................................................ 25
Table 3-13 RTC Pinout.......................................................................................................................25
Table 3-14 AD/DA Pinout ...................................................................................................................26
Table 3-15 CAN Pinout ...................................................................................................................... 27
Table 3-16 WIFI Pinout ......................................................................................................................28
Table 3-17 40pin Interface Pinout......................................................................................................30
Table 3-18 20pin Interface Pinout......................................................................................................31
Table 3-19 50pin FPC Interface Pinout.............................................................................................. 33
Table 3-20 LCD Screen Brightness Control Pinout............................................................................34
Table 3-21 LED Pinout.......................................................................................................................34
Table 3-22 Pins Distribution of Keys Module .....................................................................................35
Table 3-23 Switches Module Pinout................................................................................................... 36

1 About This Guide
1.1 Purpose
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1About This Guide
1.1 Purpose
The DK-START-GW2A55-PG484 V1.3 development board
(hereinafter referred to development board) user guide consists of following
three parts:
1. A brief introduction to the features of the development board;
2. An introduction to the development board system architecture and
hardware resources;
3. An introduction to the hardware circuits, functions and pinout.
1.2 Supported Products
The information presented in this guide applies to GW2A-LV55PG484
device.
1.3 Related Documents
The latest user guides are available on the GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
1. DS102, GW2A series FPGA Products Data Sheet
2. UG113, GW2A-55 Pinout
3. UG111, GW2A series of FPGAProducts Package and Pinout User
Guide

1 About This Guide
1.4 Terminology and Abbreviations
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1.4 Terminology and Abbreviations
The terminology and abbreviations used in this manual are as shown
in Table 1-1.
Table 1-1 Abbreviations and Terminology
Terminology and Abbreviations
Meaning
B-SRAM
Block Static Random Access Memory
DDR
Double-Data-Rate Synchronous Dynamic
Random Access Memory
DSP
Digital Signal Processing
FLASH
Flash Memory
FPGA
Field Programmable GateArray
GPIO
General Purpose Input Output
LDO
Low Dropout Regulator
LUT4
Four-input Look-up Tables
LVDS
Low-Voltage Differential Signaling
S-SRAM
Shadow Static Random Access Memory
1.5 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly by the following ways.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Introduction
2.1 Overview
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2Introduction
2.1 Overview
Figure 2-1 DK-START-GW2A55-PG484 V1.3
DK-START-GW2A55-PG484 V1.3 applies to high speed data storage
based on DDR3, high-speed communication test based on MIPI, LVDS and
GbE, 55k series of FPGA products functions evaluation, the verification of
hardware reliability, software learning and debugging, etc.
The development board uses the GW2A- LV55PG484 FPGAdevice,

2 Introduction
2.2 Development Kit
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which is the first generation product of GowinArora family. The GW2A
series of FPGA products offer a range of features and rich resources like
high-performance DSP, high-speed LVDS interface and BSRAM. These
embedded resources combine a streamlined FPGA architecture with a
55nm process to make the GW2A series of FPGA products ideal for
high-speed and low-cost applications.
GW2A- LV55PG484 development board includes a DDR3 chip with
2Gbit, 16-bit bus width. Its two Gigabit Ethernet interfaces support 10M,
100M, 1000M Ethernet communication. It has abundant peripheral
interfaces, including LVDS interfaces, a SD card socket, CAN bus interface,
MIPI CSI, MIPI DSI, AD/DA interface and GPIO interfaces. RTC module is
designed to provide real-time clock for MCU IP. Besides that, it also offers
an external Flash, switches, keys, LED, etc.
2.2 Development Kit
The development kit includes the following items:
1. DK-START-GW2A55-PG484 V1.3
2. 5V power (Input: 100-240V~50/60Hz 0.5A, output: DC 5V 2A)
3. USB Mini B Cable
4. Quick Start Guide
Figure 2-2 Development Kit

2 Introduction
2.3 PCB Components
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2.3 PCB Components
Figure 2-3 PCB Components
Button Cell
2.5V Power
Ethernet1
1.0V Power
DDR3
1.5V Power
3.3V Power
Power Socket
Power Switch
40PIN
GPIO
LED*4
USB
MINI B
Switch*4 USB to
JTAG chip
LVDS RX LVDS TX
FPGA
Key*4 Reset
Configure
FLASH
Bank4 Level
Selection
SD
20PIN
GPIO
LCD Interface
CAN Interface
CSI
DSI
AD/DA
WIFI
1.2V Power1.8V Power
Dip switch
Ethernet2

2 Introduction
2.4 System Block Diagram
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2.4 System Block Diagram
Figure 2-4 System Block Diagram
2.5 Features
The key features are as follows:
1. The FPGA device
Gowin GW2A-LV55PG484 FPGA
Max. user I/O 319
2. Download and Boot
Integrates the download module and can be downloaded with USB
Mini B cable
External Flash boot
The blue DONE light is on after loading.
3. Power
External DC 5V 2A
The blue POWER light is on after power on.

2 Introduction
2.5 Features
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The development board generates 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, 1.0v,
0.75v and the power needed by LCD interface and MIPI interface.
4. Clock system
50MHz crystal oscillator input
5. Memory Device
2Gbit DDR3 SDRAM
64Mbit FLASH
6. Ethernet interface
Two Ethernet interfaces
Uses B50610KML chip from Broadcom and supports RGMII
(10/100/1000) interface.
RJ45 connector integrating transformer
7. LVDS interfaces
Two LVDS interfaces for receiving, including ten pairs of differential
signals.
Two LVDS interface for sending, including ten pairs of differential
signals.
I/O voltage is adjustable when used as GPIO, supporting 3.3v, 2.5v
and 1.8v.
Note!
J13 needs to be set to 2.5V when LVDS is used.
8. MIPI DSI Interface
The interface includes 5 pairs of differential signals, among which
one for clock and four for data.
The stacked board connector with 30 contacts, 0.4mm pitch is
used.
Five lane DSI signals are simultaneously channeled to 20pin
double row of pins with 2.00mm pitch.
9. MIPI CSI Interface
MIPI interface includes 3 pairs of differential signals, among which
one for clock and four for data.
15pin FPC connector with 1mm pitch is used.
Differential signals of three lanes are simultaneously channeled to
the double row pin of 20 pin and 2.00mm pitch.
10. SD card slot
Eight contacts, push-push type
Card detection
11. RTC
NXP PCF8563 externally connected to 32.768KHz quartz crystal is
used.
Dual power supply design can be used to develop board power

2 Introduction
2.5 Features
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supply or button cell.
The communication interface with FPGA is I2C.
12. AD/DA
ADI AD5593R chip is used.
Supports 12-bit A/D and D/A converters, and 8-channel interface
can be configured to any combination of ADC/DAC/GPIO.
The input and output interface uses 8pin.
13. CAN
NXP TJA1050 transceiver chip is used.
The communication with FPGA is via UART.
The maximum rate is 1Mbps.
14. WIFI
The ESP-WROOM-02 WIFI module of Lexin is used;
The communication with FPGA is via SPI;
SPI rate is 20Mbps.
15. GPIO Interface
There are 40PIN double rows pins, including 34 GPIOs. I/O Bank
voltage is adjusted to 3.3V and there are also 3.3V voltage and 5V
voltage and two ground pins.
There are 20PIN double rows pins, including 16 GPIOs. All I/O and
40PIN multiplex GPIO of FPGA. There are two 3.3V ground pins
and one 5V ground pin.
16. Debug
Four keys
Four switches
Four blue LEDs

3 Development Board Circuit
3.1 FPGA Module
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3Development Board Circuit
3.1 FPGA Module
Overview
For the resources of GW2A-LV55PG484 FPGAproducts, see DS102,
GW2A Series of FPGA Products.
I/O BANK Introduction
For the I/O BANK, package and pinout information, see UG111, GW2A
Series of FPGA Products Package and Pinout User Guide.
3.2 Download Module
3.2.1 Introduction
The development board provides USB download interface, which is
realized by the A channel of FT2232 USB conversion chip. You can set the
MODE value to download the programs to the on-chip SRAM or external
Flash. When downloaded to SRAM, the data stream file will be lost if the
device is power down. When downloaded to Flash, the data stream file will
not be lost if power down.
The MODE value configuration is as follows:
1. In any modes, you can download the data stream file to the on-chip
SRAM and run it immediately.
2. Set MODE as "011" to download the data stream file to the external
Flash. Set MODE to "000" and power on again. The device will read the
FPGA configuration data from the Flash automatically.
The connection diagram for downloading and configuration is as
follows:

3 Development Board Circuit
3.2 Download Module
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Figure 3-1 Connection Diagram of FPGA Downloading and Configuration
FLASH_SPI_MISO
FLASH_SPI_MOSI
FLASH_SPI_CS_N
FLASH_SPI_CLK
JTAG_TCK
JTAG_TDO
JTAG_TDI
JTAG_TMS
USB to
JTAG chip
USB_D+
USB_D-
Configure
FLASH
By configuring EEPROM chip, the B channel of FT2232 can be
configured as an asynchronous FIFO interface. The connection diagram is
follows.
Figure 3-2 Asynchronous FIFO Connection Diagram
EEDATA
EECLK
EECS
FTDI_RD#
FTDI_TXE#
FTDI_RXF#
FIFO_D[7:0]
USB to
FIFO
USB_D+
USB_D-
Configure
EEPROM
FTDI_SIWU#
FTDI_WR#
3.2.2 Pinout
Table 3-1 FPGA Download and Pinout
Name
FPGA Pin No.
BANK
I/O Level
Description
JTAG_TCK
N20
2
3.3V
JTAG Signal
JTAG_TDO
M22
2
3.3V
JTAG Signal
JTAG_TDI
M20
2
3.3V
JTAG Signal
JTAG_TMS
N22
2
3.3V
JTAG Signal

3 Development Board Circuit
3.3 Power Supply
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Name
FPGA Pin No.
BANK
I/O Level
Description
FLASH_SPI_MISO
P19
3
1.5V
Configure
FLASH Signal
FLASH_SPI_MOSI
P20
3
1.5V
Configure
FLASH Signal
FLASH_SPI_CS_N
N18
3
1.5V
Configure
FLASH Signal
FLASH_SPI_CLK
P18
3
1.5V
Configure
FLASH Signal
Table 3-2 Asynchronous FIFO Pinout
Name
FPGA Pin No.
BANK
I/O Level
Description
FTDI_SIWU#
B12
0
1.2V
Send/wake up
signal
FTDI_WR#
A11
0
1.2V
Write signal
FTDI_RD#
B11
0
1.2V
Read signal
FTDI_TXE#
C9
0
1.2V
Write Enable
Signal
FTDI_RXF#
C10
0
1.2V
Read Enable
Signal
FIFO_D0
E19
2
3.3V
Data bits 0
FIFO_D1
E20
2
3.3V
Data bit 1
FIFO_D2
F18
2
3.3V
Data bit 2
FIFO_D3
F19
2
3.3V
Data bit 3
FIFO_D4
G20
2
3.3V
Data bit 4
FIFO_D5
G19
2
3.3V
Data bit 5
FIFO_D6
H20
2
3.3V
Data bit 6
FIFO_D7
H18
2
3.3V
Data bit 7
3.3 Power Supply
3.3.1 Introduction
The development board is powered through a power adapter. The
input parameter is 100-240V~50/60MHz 0.5A, and the output is DC +5V
2A.
The input 5V power can generate 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, 1.0v and
0.75v power required by DDR3, 17.4v, +5V and -5v required by MIPI DSI
interface and 16V, 10.4v, 9.9v, -7v required by RGB screen interface
through the power chip on the development board.