GOWIN GW1NS Series User manual

DK-START-GW1NS4&GW1NSR4&GW1NS
ER4_QN48
User Guide
DBUG371-1.0E, 7/8/2020

Copyright©2020 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
No part of this document may be reproduced or transmitted in any form or by any denotes,
electronic, mechanical, photocopying, recording or otherwise, without the prior written
consent of GOWINSEMI.
Disclaimer
GOWINSEMI®, LittleBee®,Arora, and the GOWINSEMI logos are trademarks of
GOWINSEMI and are registered in China, the U.S. Patent and Trademark Office, and other
countries. All other words and logos identified as trademarks or service marks are the
property of their respective holders, as described at www.gowinsemi.com. GOWINSEMI
assumes no liability and provides no warranty (either expressed or implied) and is not
responsible for any damage incurred to your hardware, software, data, or property resulting
from usage of the materials or intellectual property except as outlined in the GOWINSEMI
Terms and Conditions of Sale. All information in this document should be treated as
preliminary. GOWINSEMI may make changes to this document at any time without prior
notice. Anyone relying on this documentation should contact GOWINSEMI for the current
documentation and errata.

Revision History
Date
Version
Description
7/8/2020
1.0E
Initial version published.

Contents
DBUG371-1.0E
i
Contents
Contents...............................................................................................................i
List of Figures....................................................................................................iii
List of Tables......................................................................................................iv
1About This Guide ..........................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Supported Products............................................................................................................1
1.1 Related Documents............................................................................................................1
1.2 Terminology and Abbreviations...........................................................................................2
1.3 Support and Feedback .......................................................................................................2
2Development Board Introduction.................................................................3
2.1 Overview.............................................................................................................................3
2.2 A Development Board Suite................................................................................................4
2.3 PCB Components............................................................................................................... 5
2.4 System Block Diagram .......................................................................................................6
2.5 Features..............................................................................................................................6
2.6 Development Board Specification ......................................................................................7
3Development Board Circuit..........................................................................9
3.1 FPGA Module .....................................................................................................................9
3.2 Download & Debug............................................................................................................. 9
3.2.1 Overview.......................................................................................................................... 9
3.2.2 USB ............................................................................................................................... 10
3.2.3 J- LINK...........................................................................................................................10
3.2.4 Procedure ...................................................................................................................... 10
3.2.5 Pins Distribution............................................................................................................. 11
3.3 Power Supply.................................................................................................................... 11
3.3.1 Overview........................................................................................................................ 11
3.3.2 Power System Distribution ............................................................................................12

Contents
DBUG371-1.0E
ii
3.3.3 Pins Distribution.............................................................................................................13
3.4 Clock, Reset ..................................................................................................................... 13
3.4.1 Overview........................................................................................................................13
3.4.2 Clock, Reset ..................................................................................................................13
3.4.3 Pins Distribution.............................................................................................................14
3.5 LED...................................................................................................................................14
3.5.1 Overview........................................................................................................................14
3.5.2 LED Circuit.....................................................................................................................14
3.5.3 Pins Distribution.............................................................................................................15
3.6 Switches ........................................................................................................................... 15
3.6.1 Overview........................................................................................................................15
3.7 Key....................................................................................................................................15
3.7.1 Overview........................................................................................................................15
3.7.2 Key Circuit .....................................................................................................................15
3.7.3 Pins Distribution.............................................................................................................16
3.8 GPIO.................................................................................................................................16
3.8.1 Overview........................................................................................................................16
3.8.2 GPIO Circuit................................................................................................................... 16
3.8.3 Pins Distribution.............................................................................................................16
3.9 MIPI/LVDS ........................................................................................................................17
3.9.1 Overview........................................................................................................................17
3.9.2 MIPI/LVDS Circuit..........................................................................................................17
3.9.3 Pins Distribution.............................................................................................................18
3.10 RS232.............................................................................................................................20
3.10.1 Overview......................................................................................................................20
3.10.2 RS232 Circuit...............................................................................................................20
3.10.3 Pins Distribution...........................................................................................................20
4Precautions..................................................................................................21
5Gowin Software...........................................................................................22

List of Figures
DBUG371-1.0E
iii
List of Figures
Figure 2-1 DK-START-GW1NS4&GW1NSR4& GW1NSER4_QN48 V1.1........................................3
Figure 2-2A Development Board Suite .............................................................................................. 4
Figure 2-3 PCB Components.............................................................................................................5
Figure 2--4 System Block Diagram.................................................................................................... 6
Figure 3-1 Connection Diagram for FPGA USB ................................................................................10
Figure 3-2 FPGA J-LINK Connection Diagram..................................................................................10
Figure 3-3 Power System Distribution ............................................................................................... 12
Figure 3-4 Clock, Reset..................................................................................................................... 13
Figure 3-5 LED Circuit .......................................................................................................................14
Figure 3-6 Key Circuit Diagram.......................................................................................................... 15
Figure 3-7 GPIO Circuit ..................................................................................................................... 16
Figure 3-8 LVDS Circuit .....................................................................................................................17
Figure 3-9 RS232 Download Connection ..........................................................................................20

List of Tables
DBUG371-1.0E
iv
List of Tables
Table 1-1 Terminology and Abbreviations.......................................................................................... 2
Table 2-1 Development Board Specification...................................................................................... 7
Table 3-1 FPGA Download Pins Distribution ..................................................................................... 11
Table 3-2 FPGA Power Pins Distribution ...........................................................................................13
Table 3-3 FPGA Clock and Reset Pins Distribution........................................................................... 14
Table 3-4 LED Pins Distribution.........................................................................................................15
Table 3-5 Key Circut Pins Distribution ............................................................................................... 16
Table 3-6 J17 GPIO Pins Distribution ................................................................................................16
Table 3-7 J15 FPGA Pin Distribution..................................................................................................18
Table 3-8 J16 FPGA Pin Distribution..................................................................................................19
Table 3-9 RS232 Pins Distribution.....................................................................................................20

1 About This Guide
1.1 Purpose
DBUG371-1.0E
1(22)
1About This Guide
1.1 Purpose
DK-START-GW1NS4&GW1NSR4&GW1NSER4_QN48 V1.1 user
manual consists of the following four parts:
1. A brief introduction to the features and hardware resources of the
development board;
2. An introduction to the function, circuit, and pin distribution of each
module;
3. Attentions in use of the development board;
4. An introduction to the usage of the FPGA development software.
1.2 Supported Products
The information in the guide applies to GW1NS/GW1NSR/GW1NSER
series of FPGA products: GW1NS-4, GW1NS-4C, GW1NSR-4,
GW1NSR-4C, GW1NSER-4C.
1.1 Related Documents
You can find the related documents at www.gowinsemi.com:
1. DS821, GW1NS series FPGA Products Data Sheet
2. UG823, GW1NS series of FPGA Products Package and Pinout Manual
3. UG824, GW1NS-4&4C Pinout
4. DS861, GW1NSR series FPGA Products Data Sheet
5. DS881, GW1NSER series FPGA Products Data Sheet
6. UG864, GW1NSR-4 Pinout
7. UG865, GW1NSR-4C Pinout
8. DS881, GW1NSER series FPGA Products Data Sheet
9. UG884, GW1NSER series of FPGA Products Package and Pinout
Manual

1 About This Guide
1.2 Terminology and Abbreviations
DBUG371-1.0E
2(22)
10. UG883, GW1NSER-4C Pinout
11. UG290, Gowin FPGA Products Programming and Configuration Guide
12. SUG100, Gowin Software User Guide
1.2 Terminology and Abbreviations
The terminology and abbreviations used in this manual are as shown
in Table 1-1.
Table 1-1 Terminology and Abbreviations
Terminology and Abbreviations
Full Name
FPGA
Field Programmable GateArray
MIPI
Mobile Industry Processor Interface
LVDS
Low Voltage Differential Signaling
GPIO
Gowin Programmable Input/output
MCU
Microprogrammed Control Unit
USB
Universal Serial Bus
SoC
System On Chip
JTAG
Joint Test Action Group
SRAM
Static Random Access Memory
RS232
Recommend Standard 232
ARM
Advanced RISC Machines
B-SRAM
Block SRAM
SPI
Serial Peripheral Interface
PLL
Phase-locked Loop
QN48
QFN48
1.3 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly by the following ways.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Development Board Introduction
2.1 Overview
DBUG371-1.0E
3(22)
2Development Board Introduction
Take GW1NS-4C for an instance, this chapter mainly introduces the
composition, functions and features of the development board. Compared
to the GW1NS-4C, the GW1NS-4 has no built-in Cortex-M3 processor, and
the GW1NSER-4C offers one-time programming and authentication code
features.
2.1 Overview
Figure 2-1 DK-START-GW1NS4&GW1NSR4& GW1NSER4_QN48 V1.1
The development board adopts the GW1NS-4 SoC FPGA. SoC FPFA
is embedded with an ARM Cortex-M3 hard core processor. When the ARM
Cortex-M3 hard-core processor is employed as the core, the needs of the
Min. memory can be met. FPGA logic resources and other embedded
resources can flexibly facilitate the peripheral control functions, which
provide excellent calculation functions and exceptional system response
interrupts. They also offer high performance, low power consumption,

2 Development Board Introduction
2.2 A Development Board Suite
DBUG371-1.0E
4(22)
flexible usage, instant start-up, affordability, nonvolatile, high security, and
abundant package types, among other benefits.
The development board offers abundant external interfaces, including
MIPI/LVDS interfaces, GPIO interfaces, etc. There are also button, LED
and other resources for developers or fans to learn to use.
2.2 A Development Board Suite
A development board suite includes the following items:
DK-START-GW1NS4&GW1NSR4&GW1NSER4_QN48 V1.1
USB Cable
Quick Start Guide
Figure 2-2A Development Board Suite
①DK-START-GW1NS4&GW1NSR4&GW1NSER4_QN48 V1.1
②USB Cable
③Quick Start Guide

2 Development Board Introduction
2.3 PCB Components
DBUG371-1.0E
5(22)
2.3 PCB Components
Figure 2-3 PCB Components
KEY
2.5V 1.2V
GPIO
LVDS/MIPI
INPUT
1.8V3.3V
OSC
LVDS/MIPI
OUTPUT
RESET
J-Link
(MCU Debug)
USB/J-Link
Select
Download
5V IN
UART
FPGA

2 Development Board Introduction
2.4 System Block Diagram
DBUG371-1.0E
6(22)
2.4 System Block Diagram
Figure 2--4 System Block Diagram
J-Link
LDO
1.2V/1.8V/2.5V/
3.3V
1*BUTTON
OSC
50MHz
FT232HL
GPIO
1*LED
MINIUSB
4*SWITCH
5V
5 Pairs LVDS/MIPI INPUT
4Pairs
LVDS/MIPI
OUTPUT
1*UART
1*SPI Flash
FPGA
2.5 Features
The structure and feature of the development board are as follows:
5. FPGA
Adopts QN48 package
Up to 38 user I/O
Embedded flash, data not easily lost if power down
Abundant LUT4 resources
Multiple modes and capacities of B-SRAM
6. FPGA Configuration Modes
JTAG
AUTO BOOT
7. Clock resource
50MHz Clock Crystal Oscillator

2 Development Board Introduction
2.6 Development Board Specification
DBUG371-1.0E
7(22)
8. Key switch and slide switch
One reset button
One key switch
9. LED
One power indicator (green)
1 LEDs (green)
One Key indicator (green)
10. Memory
1Mbit embedded Flash
64Mbit external SPI FLASH
11. MIPI/LVDS
Five pairs of LVDS differential input; Four pairs of LVDS differential
output
12. GPIO
Three IOs
13. RS232
One RS232
14. LDO Power
3.3 V, 2.5V, 1.8V, and1.2V supported
2.6 Development Board Specification
Table 2-1 Development Board Specification
No.
Item
Functional Description
Technical Condition
Remark
s
1
FPGA
Core chip
–
–
2
Download
Support an USB
interface; Support
JTAG,AUTOBOOT
USB to JTAG chip integrated on board
–
3
Power
Supply
3.3 V, 2.5V, 1.8V, and
1.2 V output via LDO
circuit
Input power: 5V
Provide power for FPGA, download
circuit and other circuits via 5V–3.3 V
circuit;
Provide power for FPGAvia 5V to 2.5V
circuit;
Provide power for FPGA via 5V–1.8V
circuit;
Provide power for FPGAvia 5 V–1.2 V
circuit.
–
4
Key
Available for testing
1
–

2 Development Board Introduction
2.6 Development Board Specification
DBUG371-1.0E
8(22)
No.
Item
Functional Description
Technical Condition
Remark
s
Switches
5
Reset button
Reset for FPGA
1
–
6
LED
Test indicator, Key
indicator, Power
indicator
Four Test indicators, green
One Power indicator, green
One Key indicator, green
–
7
Crystal
Oscillator
Provide 50MHz clock
for FPGA
Package5032
–
8
Memory
FLASH
1Mbit embedded Flash
64Mbit external SPI FLASH
–
9
GPIO
I/O, convenient for user
extension and test
3
–
10
MIPI/LVDS
MIPI/LVDS, used for
testing
Five pairs of input, Four pairs of output
–
11
RS232
Used for testing
One RS232
–
12
Protection
USB interface: ESD
protection;
Power interface:
Inverse current and
over current protection
USB interface ESD protection: ±15kV
non-contact discharge, ±8kV contact
discharge;
Schottky diode is connected between
positive and negative anodes of power
interface;
2A self-recovery fuses are connected
at power inlet
–
13
Voltage
–
Input Voltage: 5V
–
14
Humidity
–
95%
–
15
Temperature
–
Operating range: –20°~70°
–

3 Development Board Circuit
3.1 FPGA Module
DBUG371-1.0E
9(22)
3Development Board Circuit
3.1 FPGA Module
Overview
For the resources of GW1NS series of FPGAProducts, please refer to
DS821, GW1NS series of FPGAProducts Data Sheet.
For the resources of GW1NSR series of FPGA Products, please refer
to DS861, GW1NSR series of FPGA products.
For the resources of GW1NSER series of FPGAProducts, please refer
to DS881, GW1NSER series of SecureFPGA Products Data Sheet.
I/O BANK Introduction
For the I/O BANK information and package and pinout information,
please refer to UG823, GW1NS series of FPGA Products Package and
Pinout User Guide, UG861, GW1NSR series of FPGA Products Package
and Pinout User Guide, and UG884, GW1NSER series of FPGA Products
Package and Pinout User Guide.
3.2 Download & Debug
3.2.1 Overview
The development board provides a USB interface and a J-Link
interface. The .fs file can be downloaded to the internal SRAM or internal
FLASH as needed.
Note!
When downloaded to SRAM, the data stream file will be lost if the device is powered
down, and it will need to be downloaded again after power-on.
If downloaded to flash, the data stream file will not be lost if the device is powered
down.

3 Development Board Circuit
3.2 Download & Debug
DBUG371-1.0E
10(22)
3.2.2 USB
Figure 3-1 Connection Diagram for FPGA USB
TMS
TCK
TDI
TDO
USB 转JTAG
芯片
USB_D+
USB_D- 7
6
3
4
U1
U17
GW1NS4/GW1NSR4/GW1NSER4
J6
MINI USB
插座
3.2.3 J- LINK
Figure 3-2 FPGA J-LINK Connection Diagram
TMS
TCK
TDI
TDO
20PIN_2.54mm间距
双列排针
7
6
3
4
U1
J8
GW1NS4/GW1NSR4/GW1NSER4
3.2.4 Procedure
1. FPGA and MCU Download Mode:
Plug the USB cable to the development board USB interface (J6).
Note!
Before downloading, switch the SW3, SW4, SW5, and SW6 on the development
board to FT232 side.
2. MCU Debugging Mode
Connect to J8 with the J-Link simulator.
Note!
Before Debugging, switch the SW3, SW4, SW5, and SW6 on the development board
to J-Link side;

3 Development Board Circuit
3.3 Power Supply
DBUG371-1.0E
11(22)
3.2.5 Pins Distribution
Table 3-1 FPGA Download Pins Distribution
Signal Name
Pin No.
BANK
Description
I/O Level
TMS
6
0
JTAG Signal
3.3 V /2.5 V /1.2V
TCK
7
0
JTAG Signal
3.3 V /2.5 V /1.2V
TDI
3
0
JTAG Signal
3.3 V /2.5 V /1.2V
TDO
4
0
JTAG Signal
3.3 V /2.5 V /1.2V
MODE0
10
0
Mode selection pin
3.3 V /2.5 V /1.2V
JTAGSEL_N
8
0
JTAGSEL_N
3.3 V /2.5 V /1.2V
DONE
9
0
One DONE indicator
3.3 V /2.5 V /1.2V
3.3 Power Supply
3.3.1 Overview
DC5V is input by USB interface. The TI LDO power supply chip is used
to step down voltage from 5V to 3.3V, 2.5V, 1.8V and 1.2V, which can
meet the power demand of the development board.

3 Development Board Circuit
3.3 Power Supply
DBUG371-1.0E
12(22)
3.3.2 Power System Distribution
Figure 3-3 Power System Distribution
USB
Interface
DC5V Input
TPS7A7001
LDO
1.2V
TPS7A7001
LDO
3.3V
TPS7A7001
LDO
2.5V
USB2JTAG
（FT232）
UART&KEY&LED&
RST&CLK
FPGA VCCX
VCCO2(LVDS)
FPGA VCCO0&1
（LVDS）
FPGA VCC
FPGA VCCO2
VCCO0&1
(MIPI)
TPS7A7001
LDO
1.8V
FPGA VCCO3
FPGA VCCO0&1
(Flash)

3 Development Board Circuit
3.4 Clock, Reset
DBUG371-1.0E
13(22)
3.3.3 Pins Distribution
Table 3-2 FPGA Power Pins Distribution
Signal Name
Pin No.
BANK
Description
I/O Level
VCCO0
5
0
I/O Bank Voltage
2.5V/1.8V/1.2V
VCCO1
38
1
I/O Bank Voltage
2.5V/1.8V/1.2V
VCCO2
36
2
I/O Bank Voltage
2.5V/1.2V
VCCO3
12, 24
3
I/O Bank Voltage
1.8V
VCCX
25
-
Auxiliary voltage
2.5V
VCC
11, 37
-
Core voltage
1.2V
VSS
26
-
GND
-
3.4 Clock, Reset
3.4.1 Overview
The development board provides a 50MHz crystal oscillator connected
to the PLL input pin. This can be employed as the input clock for the PLL
in FPGA. Frequency division and multiplication of PLL can output the clock
required by the user.
3.4.2 Clock, Reset
Figure 3-4 Clock, Reset
22
23
KEY2
50MHz
ADM811
3.3V
F_RST_N
F_CLK
U1
U2
X2
GW1NS4/GW1NSR4/GW1NSER4
SN74
AVC4
T245
U26