GOWIN DK-START-GW2A18 User manual

DK-START-GW2A18
User Guide
DBUG354-1.0E,08/28/2018

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Revision History
Date
Version
Description
08/28/2018
1.0E
Initial version published.

Contents
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Contents
Contents ...............................................................................................................i
1 About This Guide.............................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Supported Products ............................................................................................................ 1
1.3 Related Documents ............................................................................................................1
1.4 Abbreviations and Terminology...........................................................................................1
1.5 Support and Feedback .......................................................................................................2
2 Development Board Description ....................................................................3
2.1 Overview.............................................................................................................................3
2.2 A Development Board Suite................................................................................................ 4
2.3 PCB Components ............................................................................................................... 5
2.4 System Architecture............................................................................................................6
2.5 Features..............................................................................................................................6
3 Development Board Circuit ............................................................................9
3.1 FPGA Module .....................................................................................................................9
3.1.1 Introduction ...................................................................................................................... 9
3.1.2 I/O Distribution ...............................................................................................................10
3.2 Download Module .............................................................................................................12
3.2.1 Introduction ....................................................................................................................12
3.2.2 Pins Distribution............................................................................................................. 13
3.3 Power Supply....................................................................................................................13
3.3.1 Introduction ....................................................................................................................13
3.3.2 Power System Distribution ............................................................................................ 15
3.4 Clock, Reset .....................................................................................................................16
3.4.1 Introduction ....................................................................................................................16

Contents
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3.4.2 Pins Distribution............................................................................................................. 16
3.5 DDR3 ................................................................................................................................ 16
3.5.1 Introduction ....................................................................................................................17
3.5.2 Pins Distribution............................................................................................................. 17
3.6 Ethernet interface .............................................................................................................19
3.6.1 Introduction ....................................................................................................................19
3.6.2 Pins Distribution............................................................................................................. 19
3.7 LVDS interfaces ................................................................................................................20
3.7.1 Introduction ....................................................................................................................20
3.7.2 Pins Distribution............................................................................................................. 22
3.8 SD Card ............................................................................................................................22
3.8.1 Introduction ....................................................................................................................22
3.8.2 Pins Distribution............................................................................................................. 24
3.9 GPIO .................................................................................................................................24
3.9.1 Introduction ....................................................................................................................24
3.9.2 Pins Distribution............................................................................................................. 25
3.10 LED .................................................................................................................................26
3.10.1 Introduction ..................................................................................................................27
3.10.2 Pins Distribution........................................................................................................... 27
3.11 Key ..................................................................................................................................27
3.11.1 Introduction ..................................................................................................................27
3.11.2 Pins Distribution ...........................................................................................................28
3.12 Switch .............................................................................................................................28
3.12.1 Introduction ..................................................................................................................28
3.12.2 Pins Distribution........................................................................................................... 29
4 Gowin YunYuan Software .............................................................................30

List of Figures
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List of Figures
Figure 2-1 PCB Components............................................................................................................. 5
Figure 2-2System Architecture...........................................................................................................6
Figure 3-1 GW2A I/O Bank Distribution ............................................................................................. 10
Figure 3-2 View of GW2A-18 PG256 Pins Distribution (Top View).................................................... 11
Figure 3-3 Connection Diagram for FPGA Downloading and Configuration ..................................... 13
Figure 3-4 Power System Distribution ...............................................................................................15
Figure 3-5 Connection Diagram for Clock and Reset ........................................................................16
Figure 3-6 Connection Diagram of FPGA and DDR3 ........................................................................ 17
Figure 3-7 Connection Diagram of FPGA and Ethernet ....................................................................19
Figure 3-8 LVDS TX Interface............................................................................................................ 21
Figure 3-9 LVDS RX Interface ...........................................................................................................21
Figure 3-10 Connection Diagram of SD Card.................................................................................... 23
Figure 3-11 20pin Interface ................................................................................................................24
Figure 3-12 30pin Interface................................................................................................................ 25
Figure 3-13 LED Connection Diagram............................................................................................... 27
Figure 3-14 GPIO Circuit ...................................................................................................................28
Figure 3-15 GPIO Circuit ...................................................................................................................29

List of Tables
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List of Tables
Table 1-1 Abbreviations and Terminology .......................................................................................... 2
Table 3-1GW2A-LV18PG256 FPGA Resources List .........................................................................9
Table 3-2 FPGA I/O Bank Voltage and Functions.............................................................................. 11
Table 3-3 FPGA Download and Pins Distribution ..............................................................................13
Table 3-4 Clock and Reset Pins Distribution......................................................................................16
Table 3-5 DDR3 Pins Distribution ......................................................................................................17
Table 3-6 Ethernet Pins Distribution................................................................................................... 19
Table 3-7 LVDS TX Interface Pins Distribution ..................................................................................22
Table 3-8 LVDS RX Interface Pins Distribution ..................................................................................22
Table 3-9 20pin Interface Pins Distribution ........................................................................................ 25
Table 3-10 30pin Interface Pins Distribution ...................................................................................... 26
Table 3-11 LED Pins Distribution .......................................................................................................27
Table 3-12 Key Pins Distribution ........................................................................................................28
Table 3-13 Pins Distribution of the Switch Module............................................................................. 29

1About This Guide
1.1Purpose
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1About This Guide
1.1 Purpose
The DK-START-GW2A18 development board (hereinafter referred to
as development board) user manual consists of the following four parts:
1. A brief introduction to the features and hardware resources of the
development board;
2. An introduction to the development board architecture and hardware
resources;
3. An introduction to the hardware circuit functions, circuits, and pins
distribution;
4. An introduction to the use of the Gowin YunYuan software.
1.2 Supported Products
The information presented in this guide applies to the following Gowin
FPGA products:
GW2A-LV18PG256.
1.3 Related Documents
The latest user guides are available on the GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
1. GW2A series of FPGA Products Data Sheet
2. GW2A-18 Pinout
3. GW2A series of FPGA Products Package and Pinout
1.4 Abbreviations and Terminology
The abbreviations and terminology used in this manual are set out in
Table 1-1 below.

1About This Guide
1.5Support and Feedback
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Table 1-1 Abbreviations and Terminology
Abbreviations and Terminology
Full Name
B-SRAM
Block SRAM
DDR
Double-Data-Rate Synchronous Dynamic
Random Access Memory
DSP
Digital Signal Processing
FLASH
Flash Memory
FPGA
Field Programmable Gate Array
GPIO
General Purpose Input Output
LDO
Low Dropout Regulator
LUT4
4-input Look-up Tables
LVDS
Low-Voltage Differential Signaling
S-SRAM
Shadow SRAM
1.5 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly using the information provided below.
Website: www.gowinsemi.com
E-mail: [email protected]
+Tel: [phone]

2Development Board Description
2.1Overview
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2Development Board Description
2.1 Overview
Figure 2-1 DK-START-GW2A18
DK-START-GW2A18 applies to high speed data storage, high-speed
communication test, FPGA functions evaluation, the verification of
hardware reliability, software learning and debugging, etc.
The development board uses the GW2A-LV18PG256 FPGA device,
which is the first generation products of Gowin Arora ® family. The GW2A
series of FPGA products offer a range of comprehensive features and rich
internal resources like high-performance DSP resources, a high-speed

2Development Board Description
2.2A Development Board Suite
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LVDS interface, and abundant BSRAM memory resources. These
embedded resources combine a streamlined FPGA architecture with a
55nm process to make the GW2A series of FPGA products ideal for
high-speed and low-cost applications.
DK-START-GW2A18 includes a DDR3 chip with 2Gbit storage
space,16 bits data bus width, and the highest data speed of 1600MT/s. Its
two Gigabit Ethernet interfaces support 10M,100M,1000M Ethernet
communication. It has abundant peripheral interfaces, including LVDS
interfaces, a SD card slot, and GPIO interfaces. Besides that, it also offers
an external Flash, slide switches, key switches, external clocks, etc.
2.2 A Development Board Suite
A development board suite includes the following items:
1. DK-START-GW2A
2. 5V power (Input: 100-240V~50/60Hz 0.5A, output: DC 5V 2A)
3. USB Mini B cable
4. Quick Start
Figure 2-2 A Development Board Suite
1
3
高云DK-START-GW2A18 开
发板
5V电源
INPUT:100-240V~50/60Hz 0.5A
OUTPUT:DC 5V 2A
USB Mini-B 下载线
快速应用手册
23
4
1
2
3
4

2Development Board Description
2.3PCB Components
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2.3 PCB Components
Figure 2-1 PCB Components
1.2V电源 2.5V电源
以太网
接口芯片*2
1.0V电源
DDR3
1.5V电源 3.3V电源备用电源
电源插座
电源开关
20PIN
GPIO 插针
30PIN
GPIO 插针
MODE
BANK7
电压选择
LED*4
USB MINI B
开关*4
USB转
JTAG芯片
LVDS RX
LVDS TX
FPGA
按键*4
外部
时钟
复位
按键
配置
FLASH
以太网
接口*2
SD卡座

2Development Board Description
2.4System Architecture
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2.4 System Architecture
Figure 2-2System Architecture
DDR3
(2Gbit)
LED
开关晶振
JTAG
以太网
接口1
以太网
接口2
20PIN GPIO
Header
30PIN GPIO
Header
配置
FLASH
X16
X24
SD卡
X31 X4 X10 X10
X29
X7
X1 X4 X4 X4
X4
按键
LVDS
TX
LVDS
RX
2.5 Features
The key features of DK-START-GW2A is as follows:
1. The FPGA device
GW2A-LV18PG256C8/I7
Max. user I/O 207
2. Download and Boot
Integrates the download module; can be downloaded with the USB
Mini B cable
External Flash boot
The blue DONE light is on after loading
3. Power
External 5V 2A Power supply

2Development Board Description
2.5Features
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The blue POWER light is on after power on
The development board generates 3.3V, 2.5V, 1.5V, 1.2V, 1.0V,
and 0.75V (required by DDR3)
4. Clock system
50MHz crystal oscillator Input
External signals input
5. Memory device
2Gbit DDR3 SDRAM
64Mbit FLASH
6. Ethernet interface
Two Ethernet interfaces
Supports 10M/100M/1000M
RJ45 connector with built-in transformer
7. LVDS interfaces;
One LVDS interface for receiving, including five pairs of differential
signals.
One LVDS interface for sending, including five pairs of differential
signals.
The receiving/sending functions can be modified by changing the
resistance.
Note！
For the V2.0 development board, J13 needs to be set as 2.5V when LVDS is used.
8. SD card slot
Eight contacts, push-push type
Card detection
9. Extension interface
20PIN double row pins, including 16 GPIO, one I/O Bank voltage
(can be adjusted as 3.3V, 2.5V, 1.2V), one 3.3V voltage, one 5V
voltage, and two ground pins.
30PIN double row pins, including 24 GPIO, one 2.5V I/O Bank
voltage, one 3.3V voltage, one 5V voltage, and three ground pins.
Note!
For the V2.0 development board, the BANK0 voltage and BANK1 voltage can be set
as 3.3V or 2.5V using J13.
10. Debugging module
Four keys
Four switches

2Development Board Description
2.5Features
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Four blue LEDs

3Development Board Circuit
3.1FPGA Module
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3Development Board Circuit
3.1 FPGA Module
3.1.1 Introduction
The resources of GW2A-LV18PG256 FPGA are set out in Table 3-1.
Table 3-1GW2A-LV18PG256 FPGA Resources List
Device
GW2A-LV18PG256
LUT4
20,736
Flip-Flop (FF)
15,552
Shadow SRAM
S-SRAM (bits)
41,472
Block SRAM
B-SRAM(bits)
828K
B-SRAM quantity
B-SRAM
46
18 x 18 Multiplier
48
PLLs+DLLs
4+4
Total number of I/O banks
8
Max. User I/O
207
Core voltage
1.0V
Note!
See GW2A series of FPGA Products Data Sheet for further details.

3Development Board Circuit
3.1FPGA Module
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3.1.2 I/O Distribution
GW2A series FPGA products includes eight I/O Bank. The I/O Bank
Distribution is as shown in Figure 3-1.
Figure 3-1 GW2A I/O Bank Distribution
IO Bank 6
GW2A
IO Bank 7
IO Bank 3 IO Bank 2
IO Bank 0IO Bank 1
IO Bank 4
IO Bank 5
The view of GW2A-18 PG256 pins distribution is as shown in Figure 3-2.

3Development Board Circuit
3.1FPGA Module
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Figure 3-2 View of GW2A-18 PG256 Pins Distribution (Top View)
The board I/O Bank and functions are as listed in Table 3-2.
Table 3-2 FPGA I/O Bank Voltage and Functions
I/O BANK No.
Supply voltage
Functions
BANK0
2.5V¹
LVDS_RX Interface
30PIN GPIO Interface
50MHz crystal oscillator
Input
LED
BANK1
2.5V¹
LVDS_TX Interface
30PIN GPIO Interface
BANK2
3.3V
Ethernet interface1
Ethernet interface2
JTAG Download
SD card slot
External Clock
BANK3
3.3V
Ethernet interface2
FLASH Configuration
SD card slot
Reset
MODE

3Development Board Circuit
3.2Download Module
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I/O BANK No.
Supply voltage
Functions
DONE
RECONFIG_N
READY
FASTRD_N
BANK4
1.5V
DDR3
Key
BANK5
1.5V
DDR3
BANK6
1.5V
DDR3
Switches
BANK7
3.3V, 2.5V, 1.2V
(Adjustable)
20PIN GPIO Interface
Note！
For the V2.0 development board, the BANK0 voltage and BANK1 voltage can be set as
3.3V or 2.5V using J13.
3.2 Download Module
3.2.1 Introduction
The development board offers a USB download interface. You can set
the MODE value to download the programs to the on-chip SRAM or
external Flash. When downloaded to SRAM, the data stream file will be lost
if the device is power down. When downloaded to Flash, the data stream
file will not be lost.
The MODE value configuration:
1. In any modes, you can download the data stream file to the on-chip
SRAM and run it immediately.
2. Set MODE as "000" to download the data stream file to the external
Flash. When power-on again, the device will read the FPGA
configuration data from the Flash automatically.
The connection diagram for downloading and configuration is as
follows:

3Development Board Circuit
3.3Power Supply
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Figure 3-3 Connection Diagram for FPGA Downloading and Configuration
FLASH_SPI_MISO
FLASH_SPI_MOSI
FLASH_SPI_CS_N
FLASH_SPI_CLK
P10 R10 M9 L10
JTAG_TCK
JTAG_TDO
JTAG_TDI
JTAG_TMS
USB 转
JTAG芯片
USB_D+
USB_D-
C6
A7
A6
B8
配置
FLASH
3.2.2 Pins Distribution
Table 3-3 FPGA Download and Pins Distribution
Signal Name
FPGA Pin No.
BANK
I/O
Description
JTAG_TCK
A7
2
3.3V
JTAG Signal
JTAG_TDO
C6
2
3.3V
JTAG Signal
JTAG_TDI
A6
2
3.3V
JTAG Signal
JTAG_TMS
B8
2
3.3V
JTAG Signal
FLASH_SPI_MISO
P10
3
3.3V
FLASH signals
configuration
FLASH_SPI_MOSI
R10
3
3.3V
FLASH signals
configuration
FLASH_SPI_CS_N
M9
3
3.3V
FLASH signals
configuration
FLASH_SPI_CLK
L10
3
3.3V
FLASH signals
configuration
3.3 Power Supply
3.3.1 Introduction
5V power (Input: 100-240V~50/60MHz 0.5A, output: DC +5V 2A) The
development board generates 3.3V, 2.5V, 1.5V, 1.2V, 1.0V, and 0.75V
(required by DDR3).
One redundant power location is reserved on the development board.
A LDO can be welded to generate 3.3V, 1.5V, and 1.0V. The rated current