GOWIN GW1NSER Series User manual

GW1NSER series of SecureFPGA
Package & Pinout User Guide
UG884-1.01E, 04/16/2020

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Disclaimer
GOWINSEMI assumes no liability and provides no warranty (either expressed or implied)
and is not responsible for any damage incurred to your hardware, software, data, or
property resulting from usage of the materials or intellectual property except as outlined in
the GOWINSEMI Terms and Conditions of Sale. GOWINSEMI may make changes to this
document at any time without prior notice. Anyone relying on this documentation should
contact GOWINSEMI for the current documentation and errata.

Revision History
Date
Version
Description
10/8/2019
1.0E
Initial version published.
04/16/2020
1.01E
Quantity of GW1NSER-4C QN48P/QN48G Pins modified.

Contents
UG884-1.01E
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Contents
Contents.................................................................................................................i
List of Figures.....................................................................................................ii
List of Tables......................................................................................................iii
1About This Guide ..........................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents ............................................................................................................1
1.3 Terminology and Abbreviations...........................................................................................2
1.4 Support and Feedback .......................................................................................................2
2Overview ........................................................................................................3
2.1 PB-Free Package ...............................................................................................................3
2.2 Package and Max. User I/O Information ............................................................................4
2.3 Power Pin ........................................................................................................................... 4
2.4 Pin Quantity ........................................................................................................................5
2.4.1 Quantity of GW1NSER-4C Pins ......................................................................................5
2.5 Pin Definitions..................................................................................................................... 6
2.6 I/O BANK Introduction ........................................................................................................9
3View of Pin Distribution ..............................................................................10
3.1 View of GW1NSER-4C Pins Distribution..........................................................................10
3.1.1 View of QN48P Pins Distribution ................................................................................... 11
3.1.2 View of QN48G Pins Distribution...................................................................................12
4Package Diagrams ......................................................................................13
4.1 QN48P / QN48G Package Outline (6mm x 6mm) ............................................................14

List of Figures
UG884-1.01E
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List of Figures
Figure 2-1 GW1NSER series of SecureFPGA products I/O Bank Distribution ................................. 9
Figure 3-1 View of GW1NSER-4C QN48P Pins Distribution (Top View)........................................... 11
Figure 3-2 View of GW1N-4 QN48G Pins Distribution (Top View) ....................................................12
Figure 4-1 Package Outline of QN48P / QN48G ...............................................................................14

List of Tables
UG884-1.01E
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List of Tables
Table 1-1 Terminology and Abbreviations .......................................................................................... 2
Table 2-1 Package, Max. User I/O Information, and LVDS Paris ......................................................4
Table 2-2 GW1NSER Power Pins......................................................................................................4
Table 2-3 Quantity of GW1NSER-4CPins ..........................................................................................5
Table 2-4 Definition of the Pins in the GW1NSER series of SecureFPGA products .........................6
Table 3-1 Other pins in GW1NSER-4C QN48P.................................................................................11
Table 3-2 Other pins in GW1NSER-4C QN48G ................................................................................12

1 About This Guide
1.1 Purpose
UG884-1.01E
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1About This Guide
1.1 Purpose
This manual contains an introduction to the GW1NSER series of
SecureFPGA products together with a definition of the pins, list of pin
numbers, distribution of pins, and package diagrams.
1.2 Related Documents
The user guides are available on the GOWINSEMI Website. You can
find the related documents at www.gowinsemi.com:
1. DS881, GW1NSER series of SecureFPGA products Data Sheet
2. UG290, Gowin FPGA Products Programming and Configuration User
Guide
3. UG884, GW1NSER series of SecureFPGA products Package and
Pinout
4. UG883, GW1NSER-4C Pinout

1 About This Guide
1.3 Terminology and Abbreviations
UG884-1.01E
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1.3 Terminology and Abbreviations
The terminology and abbreviations used in this manual are as shown in
Table 1-1.
Table 1-1 Terminology and Abbreviations
Terminology and Abbreviations
Full Name
FPGA
Field Programmable Gate Array
GPIO
Gowin Programmable IO
QN48P
QFN48P
QN48G
QFN48G
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly by the following ways.
Website: www.gowinsemi.com
E-mail:[email protected]

2 Overview
2.1 PB-Free Package
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2Overview
GW1NSER series of SecureFPGA products provide a Root of Trust
based on SRAM PUF technology. Each device is factory provisioned with a
unique key pair that is never exposed outside of the device or to the
internal development space. The Intrinsic ID BroadKey-Pro security library
is provided with GOWIN SecureFPGA devices allowing easy integration of
common security features into user applications. The GOWIN
SecureFPGA feature set is widely applicable and can used for a variety of
consumer, industrial IoT, edge, and server management applications.
2.1 PB-Free Package
The GW1NSER series of SecureFPGA products are PB free in line
with the EU ROHS environmental directives. The substances used in the
GW1NSER series of SecureFPGA products are in full compliance with the
IPC-1752 standards.

2 Overview
2.2 Package and Max. User I/O Information
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2.2 Package and Max. User I/O Information
Table 2-1 Package, Max. User I/O Information, and LVDS Paris
Package
Pitch (mm)
Size (mm)
GW1NSER-4C
QN48P
0.4
6 x 6
38(4)
QN48G
0.4
6 x 6
38(4)
Note!
In this manual, abbreviations are employed to refer to the package types. See
1.3Terminology and Abbreviations.
The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The data in
this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS) are used as
I/O. When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO,
and TMS) can be used as GPIO simultaneously, and the Max. user I/O plus one.
2.3 Power Pin
Table 2-2 GW1NSER Power Pins
VCC
VCCO0
VCCO1
VCCO2
VCCO3
VSS