GOWIN DK START GW1NZ-LV1FN32C6I5 User manual

DK_START_GW1NZ-LV1FN32C6I5_V3.1
User Guide
DBUG393-1.0E, 07/22/2021

Copyright © 2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
，, Gowin, and GOWINSEMI are trademarks of Guangdong Gowin
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Disclaimer
GOWINSEMI assumes no liability and provides no warranty (either expressed or implied)
and is not responsible for any damage incurred to your hardware, software, data, or
property resulting from usage of the materials or intellectual property except as outlined in
the GOWINSEMI Terms and Conditions of Sale. All information in this document should be
treated as preliminary. GOWINSEMI may make changes to this document at any time
without prior notice. Anyone relying on this documentation should contact GOWINSEMI for
the current documentation and errata.

Revision History
Date
Version
Description
07/22/2021
1.0E
Initial version published.

Contents
DBUG393-1.0E
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Contents
Contents ...............................................................................................................i
List of Figures....................................................................................................iii
List of Tables......................................................................................................iv
1 About This Guide.............................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents ............................................................................................................1
1.3 Terminology and Abbreviations........................................................................................... 1
1.4 Support and Feedback .......................................................................................................2
2 Introduction......................................................................................................3
2.1 Overview.............................................................................................................................3
2.2 Development Kit .................................................................................................................4
2.3 PCB Components ...............................................................................................................5
2.4 System Block Diagram .......................................................................................................5
2.5 Features.............................................................................................................................. 6
2.6 Development Board Description.........................................................................................7
3 Development Board Circuit ............................................................................8
3.1 FPGA Module .....................................................................................................................8
3.2 Download............................................................................................................................8
3.2.1 Overview..........................................................................................................................8
3.2.2 USB Download Circuit .....................................................................................................9
3.2.3 Download Flow ................................................................................................................ 9
3.2.4 Pinout............................................................................................................................... 9
3.3 Power Supply...................................................................................................................... 9
3.3.1 Overview..........................................................................................................................9
3.4 Clock, Reset .....................................................................................................................10
3.4.1 Overview........................................................................................................................10
3.4.2 Clock, Reset Circuit .......................................................................................................10

Contents
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3.4.3 Pinout.............................................................................................................................10
3.5 LED ................................................................................................................................... 11
3.5.1 Overview........................................................................................................................ 11
3.5.2 LED Circuit..................................................................................................................... 11
3.5.3 Pinout............................................................................................................................. 11
3.6 Switches Module...............................................................................................................12
3.6.1 Overview........................................................................................................................12
3.6.2 Switches Circuit .............................................................................................................12
3.6.3 Pinout.............................................................................................................................12
3.7 GPIO .................................................................................................................................13
3.7.1 Overview........................................................................................................................13
3.7.2 GPIO Circuit...................................................................................................................13
3.7.3 Pinout.............................................................................................................................13
4 Considerations...............................................................................................15
5 Gowin Software..............................................................................................16

List of Figures
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List of Figures
Figure 2-1 DK_START_GW1NZ-LV1FN32C6I5_V3.1 Development Board......................................3
Figure 2-2 A Development Kit ............................................................................................................ 4
Figure 2-3 PCB Components............................................................................................................. 5
Figure 2-4 System Block Diagram ..................................................................................................... 5
Figure 3-1 FPGA USB Download Diagram........................................................................................ 9
Figure 3-2 Clock, Reset .....................................................................................................................10
Figure 3-3 LED Circuit .......................................................................................................................11
Figure 3-4 Switches Circuit ................................................................................................................12
Figure 3-5 GPIO Circuit .....................................................................................................................13

List of Tables
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List of Tables
Table 1-1 Terminology and Abbreviations .......................................................................................... 1
Table 2-1 Development Board Description ........................................................................................ 7
Table 3-1 FPGA Download Pinout .....................................................................................................9
Table 3-2 FPGA Clock and Reset Pinout ........................................................................................... 10
Table 3-3 LED Pinout .........................................................................................................................11
Table 3-4 Switches Pinout.................................................................................................................. 12
Table 3-5 GPIO Pinout ....................................................................................................................... 13

1 About This Guide
1.1 Purpose
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1About This Guide
1.1 Purpose
The DK_START_GW1NZ-LV1FN32C6I5_V3.1 user manual consists
of the following four parts:
1. A brief introduction to the features and hardware resources of the
development board;
2. An introduction to the functions, circuits, and pinouts of each module;
3. Considerations for the use of development board;
4. An introduction to the usage of the FPGA development software.
1.2 Related Documents
The latest user guides are available on the GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
1. DS841, GW1NZ series of FPGA Products Data Sheet
2. UG843, GW1NZ series of FPGA Products Package and Pinout User
Guide
3. UG842, GW1NZ-1 Pinout
4. UG290, Gowin FPGA Products Programming and Configuration Guide
5. SUG100, Gowin Software User Guide
1.3 Terminology and Abbreviations
The terminology and abbreviations used in this manual are as shown
in Table 1-1.
Table 1-1 Terminology and Abbreviations
Terminology and Abbreviations
Meaning
FPGA
Field Programmable Gate Array

1 About This Guide
1.4 Support and Feedback
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Terminology and Abbreviations
Meaning
LED
Light Emitting Diode
GPIO
Gowin Programmable Input/Output
LUT4
4-input Look-up Tables
SSRAM
Shadow Static Random Access Memory
BSRAM
Block Static Random Access Memory
PLL
Phase-locked Loop
LVDS
Low-Voltage Differential Signaling
DSP
Digital Signal Processing
SPMI
System Power Management Interface
FN32
QFN32 package
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly by the following ways.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Introduction
2.1 Overview
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2Introduction
2.1 Overview
Figure 2-1 DK_START_GW1NZ-LV1FN32C6I5_V3.1 Development Board
This development board adopts the GW1NZ-1 series of FPGA device.
The GW1NZ series of FPGA products are the first generation products in
the LittleBee® family. It has the characteristics of low power consumption,
instant on, low cost, non-volatile, high security, various packages, and
flexible usage. They can be widely used in communication, industry control,
consumption, video control, etc.
GOWINSEMI provides a new generation of FPGA hardware

2 Introduction
2.2 Development Kit
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development environment that supports FPGA synthesis, placement &
routing, bitstream generation and download, etc.
The development board offers USB download interface, GPIO
interfaces, SPMI, keys, LEDs, etc., which is useful for both developers and
learners.
2.2 Development Kit
The development board kit includes the following items:
DK_START_GW1NZ-LV1FN32C6I5_V3.1 development board
5V power (Input: 100-240V~50/60Hz 0.5A, output: DC 5V 2A)
USB Mini-B cable
Figure 2-2 A Development Kit
1
23
①DK_START_GW1NZ-LV1FN32C6I5_V3.1
development board
②5V power supply
③USB Mini-B cable

2Introduction
2.3 PCB Components
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2.3 PCB Components
Figure 2-3 PCB Components
Power
Outlet
Reset
Key
Power
Switch
LED*2
GPIO
DONE
Voltage
Selection
OSC
FPGADial Switch
SPMI
Test Pin
SPMI/JTAG
Selection
Level
Conversion
Chip
USB
Download
USB-to-JTAG Chip Power Chip*3
2.4 System Block Diagram
Figure 2-4 System Block Diagram
LED
Crystal
Oscillator
USB
DONE
Light
20PIN GPIO
Header
X17
Reset
X9 X4
X1
X1 X2
X4
Dial
Switch Slide Switch
X1
GW1NZ-LV1FN32C6/I5

2Introduction
2.5Features
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2.5 Features
The structure and features of the development board are as follows:
1. FPGA
QFN32 package
25 user I/Os
Embedded flash, data not easily lost if power down
Abundant LUT4 resources
Multiple modes and capacities of SSRAM
Supports LV and UV
Embedded SPMI
2. FPGA Configuration Mode
JTAG
AUTO BOOT
DUAL BOOT
3. Clock resource
12MHz Clock Crystal Oscillator
50MHz Clock Crystal Oscillator
4. Key
One reset key
5. Switches
1 9-bit dip switch
4 slide switch
6. LED
1 power indicator (green)
1 DONE indicator
2 LEDs (green)
7. Memory device
64Kbit built-in Flash
8. GPIO
17 I/Os
9. LDO Power
Inverse voltage protection, overcurrent protection
Supports 5V, 3.3 V, 1.8 V, and 2V power supply

2Introduction
2.6Development Board Description
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2.6 Development Board Description
Table 2-1 Development Board Description
No.
Name
Functional Description
Technical Condition
Note
1
FPGA
Core chip
–
–
2
Download
Supports JTAG and
AUTOBOOT
USB download interface
–
3
Power
Supply
Provides 5V input; 3.3 V,
1.8V and 0.9V/ 1.2 V
output via LDO circuit
Input power: 5V
Provides power for
download circuit and other
circuits via the 5V to 3.3 V
circuit;
Provides power for FPGA
via 5V to 1.8V circuit;
Provides power for FPGA
via 3.3V to 0.9V/1.2V
circuit.
–
4
Switches
Available for SPMI test
4
–
5
Dip switch
Available for
multiplexing IO test
1
–
6
Reset key
FPGA reset
1
–
7
LED
Test indicator, DONE
indicator, Power
indicator
2 test indicators, green;
1 DONE indicator, green
1 Power indicator, green
–
8
Crystal
Oscillator
Provide 12MHz/ 50MHz
clock for FPGA
Package5032
–
9
GPIO
I/O for user to extend
and test
17
–
10
Select Bank
voltage
Available for FPGA bank
voltage and core voltage
test
3
–
11
Voltage
–
Input Voltage: 5V
–
12
Humidity
–
95%
–
13
Temperature
–
Operating range: –20°~70°
–

3 Development Board Circuit
3.1 FPGA Module
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3Development Board Circuit
3.1 FPGA Module
Overview
For the resources of GW1NZ series of FPGA Products, see DS841,
GW1NZ Series of FPGA Products Data Sheet.
I/O BANK Introduction
For the I/O BANK, package, and pinout information, see UG843,
GW1NZ Series of FPGA Products Package and Pinout User Guide.
3.2 Download
3.2.1 Overview
The development board provides an USB download interface. The
bitstream file can be downloaded to the internal SRAM, or internal flash as
needed.
Note!
When downloaded to SRAM, the bitstream file will be lost if the device is powered
down, and it will need to be downloaded again after power-on.
If downloaded to flash, the bitstream file will not be lost if the device is powered down.

3 Development Board Circuit
3.3 Power Supply
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3.2.2 USB Download Circuit
Figure 3-1 FPGA USB Download Diagram
TMS
TCK
TDI
TDO
USB-to-JTAG
chip
USB_D+
USB_D- 6
7
3
1
U1
U5
GW1NZ-LV1FN32C6/I5
3.2.3 Download Flow
1. SRAM: Scan the device and download bitstream after power on. When
Done is on, it indicates it is successful.
2. Internal Flash: Power on and download. After downloading the
bitstream file successfully, it can power down to reset and load the bit
file from the internal Flash. When the Done is on, it indicates that the
download has been successful.
3.2.4 Pinout
Table 3-1 FPGA Download Pinout
Name
Pin No.
BANK
Description
I/O Level
TDI
3
0
JTAG Signal
1.8V / 3.3V
TCK
6
0
JTAG Signal
1.8V / 3.3V
TMS
7
0
JTAG Signal
1.8V / 3.3V
TDO
1
0
JTAG Signal
1.8V / 3.3V
3.3 Power Supply
3.3.1 Overview
The development board is powered via a power adapter. The input
parameter is 100-240V~50/60MHz 0.8A, and the output is DC +5V 2A.
DK_START_GW1NZ-LV1FN32C6I5_V3.1 development board uses
LDO power supply chip to step down voltage from 5V to 3.3V, 1.8V, and
0.9V. The power supply current can support up to 2A. The input voltage is
5V, which can meet the required power of the development board.

3 Development Board Circuit
3.4 Clock, Reset
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3.4 Clock, Reset
3.4.1 Overview
The development board provides a 12MHz/50MHz 1 crystal oscillator
connected to the GCLK input pin. This can be employed as the global clock.
Frequency division and multiplication of PLL can provide clocks required by
users.
Note!
DK_START_GW1NZ-LV1FN32C6I5_V3.1 development board provides 50MHz clock input.
The crystal oscillator input provided by the development board depends on the FPGA
device on the board.
3.4.2 Clock, Reset Circuit
Figure 3-2 Clock, Reset
3.4.3 Pinout
Table 3-2 FPGA Clock and Reset Pinout
Name
Pin No.
BANK
Description
I/O Level
FPGA_CLK
19
1
Active crystal
oscillator Input
1.8V/3.3V
FPGA_RST2_N
11
1
Reset Signal,
active-low
1.8V/3.3V

3 Development Board Circuit
3.5 LED
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3.5 LED
3.5.1 Overview
There are two green LEDs on the development board. You can test
and verify the development board through LEDs. To use them, the LED1
and LED2 of S1 must be set to ON.
You can test the LEDs in the following ways:
When the FPGA corresponding pin output signal is logic low , the LED
is lit;
If the signal is high, LED is off.
3.5.2 LED Circuit
Figure 3-3 LED Circuit
3.5.3 Pinout
Table 3-3 LED Pinout
Name
Pin No.
BANK
Description
I/O Level
F_LED1
14
1
LED 1
1.8V/3.3V
F_LED2
12
1
LED 2
1.8V/3.3V

3 Development Board Circuit
3.6 Switches Module
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3.6 Switches Module
3.6.1 Overview
There are four slide switches on the development board available for
SPMI test. Set to SPMI, JTAG is multiplexed to SPMI; Set to JTAG, it is
JTAG download.
3.6.2 Switches Circuit
Figure 3-4 Switches Circuit
3.6.3 Pinout
Table 3-4 Switches Pinout
Signal Name
Pin No.
BANK
Description
I/O Level
SPMI_TCK
6
0
SPMI
1.8V/3.3V
SPMI_TDO
1
0
SPMI
1.8V/3.3V
SPMI_TMS
7
0
SPMI
1.8V/3.3V
SPMI_TDI
3
0
SPMI
1.8V/3.3V

3Development Board Circuit
3.7 GPIO
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3.7 GPIO
3.7.1 Overview
One 2.54mm DC3-20P socket is reserved on the development board
for function extension and testing
3.7.2 GPIO Circuit
Figure 3-5 GPIO Circuit
3.7.3 Pinout
Table 3-5 GPIO Pinout
Signal Name
Pin No.
20P Socket
Pin No.
BANK
Description
I/O Level
H_A_IO1
32
1
0
General I/O
1.8V/3.3V
H_A_IO2
31
2
0
General I/O
1.8V/3.3V
H_A_IO3
30
3
0
General I/O
1.8V/3.3V
H_A_IO4
29
4
0
General I/O
1.8V/3.3V
H_A_IO5
2
5
0
General I/O
1.8V/3.3V