Hitachi SH7032 User manual

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SuperH™ RISC Engine
SH7032 and SH7034
HD6417032, HD6477034,
HD6437034, HD6417034
HD6437034B, HD6417034B
Hardware Manual
ADE 602 062E
Rev. 6.0
9/18/02
Hitachi, Ltd.

Cautions
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patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
ha e recei ed the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes e ery attempt to ensure that its products are of high quality and reliability.
Howe er, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply oltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. E en within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor de ices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written appro al from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.

Preface
The SH7032 and SH7034 are microprocessors that integrate peripheral functions necessary for
system configuration with a 32-bit internal architecture SH -DSP CPU as its core.
The SH7032 and SH7034's on-chip peripheral functions include an interrupt controller, timers,
serial communication interfaces, a user break controller (UBC), a bus state controller (BSC), a
direct memory access controller (DMAC), and I/O ports, making it ideal for use as a
microcomputer in electronic devices that require high speed together with low power
consumption.
Intended Readership: This manual is intended for users undertaking the design of an application
system using the SH7032 and SH7034. Readers using this manual require a
basic knowledge of electrical circuits, logic circuits, and microcomputers.
Purpose: The purpose of this manual is to give users an understanding of the hardware
functions and electrical characteristics of the SH7032 and SH7034. Details
of execution instructions can be found in the SH- , SH-2, SH-DSP
Programming Manual, which should be read in conjunction with the present
manual.
Using this Manual:
• For an overall understanding of the SH7032 and SH7034's functions
Follow the Table of Contents. This manual is broadly divided into sections on the CPU, system
control functions, peripheral functions, and electrical characteristics.
• For a detailed understanding of CPU functions
Refer to the separate publication SH- , SH-2, SH-DSP Programming Manual.
Note on bit notation: Bits are shown in high-to-low order from left to right.
Related Material: The latest information is available at our Web Site. Please make sure that you
have the most up-to-date information available.
http://www.hitachisemiconductor.com/

User's Manuals on the SH7032 and SH7034:
Manual Title ADE No.
SH7032 and SH7034 Hardware Manual This manual
SH-1, SH-2, SH-DSP Programming Manual ADE- 02-085
Users manuals for development tools:
Manual Title ADE No.
C/C++ Complier, Assembler, Optimized Linkage Editor User's Manual ADE-702-304
Simulator Debugger Users Manual ADE-702-2
Hitachi Embedded Workshop Users Manual ADE-702-275
Application Note:
Manual Title ADE No.
C/C++ Complier ADE-502-04

Organization of This Manual
Table describes how this manual is organized. Figure shows the relationships between the
sections within this manual.
Table 1 Manual Organization
Category Section Title Abbrevi- ation Contents
Overview 1. Overview — Features, internal block diagram, pin
layout, pin functions
CPU 2. CPU CPU Register configuration, data structure.
instruction features, instruction types,
instruction lists
Operating
Modes 3. Operating Modes — MCU mode, PROM mode
Internal
Modules 4. Exception Handling — Resets, address errors, interrupts, trap instructions, illegal instructions
5. Interrupt
Controller INTC NMI interrupts, user break interrupts, IRQ interrupts, on-chip module interrupts
. User Break
Controller UBC Break address and break bus cycle selection
Clock 7. Clock Pulse
Generator CPG Crystal pulse generator, duty correction circuit
Buses 8. Bus State
Controller BSC Division of memory space, DRAM interface, refresh, wait state control, parity
control
9. Direct Memory
Access
Controller
DMAC Auto request, external request, on-chip
peripheral module request, cycle steal
mode, burst mode
Timers 10. 1 -Bit Integrated
Timer Pulse Unit ITU Waveform output mode, input capture function, counter clear function, buffer
operation, PWM mode, complementary
PWM mode, reset synchronized mode,
synchronized operation, phase counting
mode, compare match output mode
11. Programmable
Timing Pattern
Controller
TPC Compare match output triggers, non-
overlap operation
12. Watchdog Timer WDT Watchdog timer mode, interval timer mode
Data
Processing 13. Serial Communication
Interface
SCI Asynchronous mode, synchronous mode,
multiprocessor communication function
14. A/D Converter A/D Single mode, scan mode, activation by
external trigger

Table 1 Manual Organization (cont)
Category Section Title Abbrevi- ation Contents
Pins 15. Pin Function
Controller PFC Pin function selection
1 . Parallel I/O
Ports I/O I/O ports
Memory 17. ROM ROM PROM mode, high-speed programming
system
18. RAM RAM On-chip RAM
Power-Down
State 19. Power-Down State — Sleep mode, standby mode
Electrical
Char act er i s t i c s 20. Electrical Characteristics — Absolute maximum ratings, AC characteristics, DC characteristics,
operation timing

4. Exception handling
5. Interrupt controller (INTC)
. User break controller (UBC)
On-chip modules
7. Clock pulse generator (CPG)
8. Bus state controller (BSC)
9. Direct memory access
controller (DMAC)
Buses
10. 1 -bit integrated timer
pulse unit (ITU)
Timers
13. Serial communication
interface (SCI)
14. A/D converter
Data processing
15. Pin function
controller (PFC)
1 . Parallel I/O ports
Pins
17. ROM
18. RAM
Memory
19. Power-down state
20. Electrical characteristics
1. Overview
2. CPU
3. Operating modes
11. Programmable timing 
pattern controller (TPC)
12. Watchdog timer (WDT)
Figure 1 Manual Organization

Addresses of On-Chip Peripheral Module Registers
The on-chip peripheral module registers are located in the on-chip peripheral module space (area
5: H'5000000–H'5FFFFFF), but since the actual register space is only 5 2 bytes, address bits
A23–A9 are ignored. 32k shadow areas in 5 2 byte units that contain exactly the same contents as
the actual registers are thus provided in the on-chip peripheral module space.
In this manual, register addresses are specified as though the on-chip peripheral module registers
were in the 5 2 bytes H'5FFFE00–H'5FFFFFF. Only the values of the A27–A24 and A8–A0 bits
are valid; the A23–A9 bits are ignored. When area H'5000000–H'5000 FF is accessed, for
example, the result will be the same as when area H'5FFFE00–H'5FFFFFF is accessed. For more
details, see Section 8.3.5, Area Descriptions: Area 5.

List of Items Revised or Added for This Version
Section Page Description Edition
1.1 SuperH
Microcomputer
Features
Table 1.2 Product
Lineup
, 7 SH7034, SH7032: 2 to 1 . MHz device deleted.
Product
Number On-C ip ROM Operating Voltage Operating Frequency Temperature Range Model Marking Model No. 2Package
SH7032 ROMless 5.0 V 2 to 20 MHz -20 to +75°C HD 417032F20 HD 417032F20 112-pin plastic
-40 to +85°C HD 417032FI20 HD 417032FI20 QFP (FP-112)
3.3 V 2 to 12.5 MHz -20 to +75°C HD 417032VF12 HD 417032VF12
-40 to +85°C HD 417032VFI12 HD 417032VFI12
5.0 V 2 to 20 MHz -20 to +75°C HD 417032X20 HD 417032TE20 120-pin plastic
-40 to +85°C HD 417032XI20 HD 417032TEI20 TQFP (TFP-120)
3.3 V 2 to 12.5 MHz -20 to +75°C HD 417032VX12 HD 417032VTE12
-40 to +85°C HD 417032VXI12 HD 417032VTEI12
SH7034 PROM 5.0 V 2 to 20 MHz -20 to +75°C HD 477034F20 HD 477034F20 112-pin plastic
-40 to +85°C HD 477034FI20 HD 477034FI20 QFP (FP-112)
3.3 V 2 to12.5 MHz -20 to +75°C HD 4 7 70 3 4 V F1 2 HD 4 7 70 3 4 V F1 2
-40 to +85°C HD 4 7 70 3 4 V FI 1 2 HD 4 7 70 3 4 V FI 1 2
5.0 V 2 to 20 MHz -20 to +75°C HD 477034X20 HD 4 7 70 3 4 TE 2 0 120-pin plastic
-40 to +85°C HD 477034XI20 HD 4 7 70 3 4 TE I 2 0 TQFP (TFP-120)
3.3 V 2 to 12.5 MHz -20 to +75°C HD 4 7 70 3 4 V X 1 2 HD 4 7 70 3 4 V TE 1 2
-40 to +85°C HD 4 7 70 3 4 V X I 1 2 HD 4 7 70 3 4 V TE I 1 2
Mask 5.0 V 2 to 20 MHz -20 to +75°C HD 437034AF20 HD 437034AF20 112-pin plastic
ROM -40 to +85°C HD 437034AFI20 HD 437034AFI20 QFP (FP-112)
3.3 V 2 to 12.5 MHz -20 to +75°C HD 437034AVF12 HD 437034AF12
-40 to +85°C HD 437034AVFI12 HD 437034AFI12
5.0 V 2 to 20 MHz -20 to +75°C HD 437034AX20 HD 437034ATE20 120-pin plastic
-40 to +85°C HD 437034AXI20 HD 437034ATEI20 TQFP (TFP-120)
3.3 V 2 to 12.5 MHz -20 to +75°C HD 437 0 3 4 A VX 1 2 HD 437034ATE12
-40 to +85°C HD 437034AVXI12 HD 437034ATEI12
ROMless 5.0 V 2 to 20 MHz -20 to +75°C HD 417034F20 HD 417034F20 112-pin plastic
-40 to +85°C HD 417034FI20 HD 417034FI20 QFP (FP-112)
3.3 V 2 to 12.5 MHz -20 to +75°C HD 417034VF12 HD 417034VF12
-40 to +85°C HD 417034VFI12 HD 417034VFI12
5.0 V 2 to 20 MHz -20 to +75°C HD 417034X20 HD 417034TE20 120-pin plastic
-40 to +85°C HD 417034XI20 HD 417034TEI20 TQFP (TFP-120)
3.3 V 2 to 12.5 MHz -20 to +75°C HD 417034VX12 HD 417034VTE12
-40 to +85°C HD 417034VXI12 HD 417034VTEI12
Product
Number On-C ip ROM Operating Voltage Operating Frequency Temperature Range Model Marking Model No. 2Package
SH7034B*1Mask 3.3 V 4 to 12.5 MHz -20 to +75°C HD 437034BVF12 437034B(***)F 112-pin plastic
ROM -40 to +85°C HD 437034BVFW12 437034B(***)FW QFP (FP-112)
-20 to +75°C HD 437034BVX12 437034B(***)X 120-pin plastic
-40 to +85°C HD 437034BVXW12 437034B(***)XW TQFP (TFP-120)
ROMless 3.3 V 4 to 20 MHz -20 to +75°C HD 417034BVF20 HD 417034BVF20 112-pin plastic
-40 to +85°C HD 417034BVFW20 HD 417034BVFW20 QFP (FP-112)
-20 to +75°C HD 417034BVX20 417034BVTE20 120-pin plastic
-40 to +85°C HD 417034BVXW20 417034BVTEW20 TQFP (TFP-120)
Notes: *1 The electrical characteristics of the SH7034B mask ROM version and SH7034 PROM
version are different.
*2 For mask ROM versions, (***) is the ROM code.
1.3.2 Pin Functions
Table 1.3 Pin
Functions
12 Note amended
*2 Can be used in the SH7034 PROM version.

Section Page Description Edition
2.1.2 Control
Registers
Figure 2.2 Control
Registers
18 Description amended
Bits I3–I0: Interrupt mask bits.
2.1.4 Initial Values
of Registers
Table 2.1 Initial
Values of Registers
19 Description amended
SR Bits I3–I0 are 1111(H'F), reserved bits are 0, and other
bits are undefined
3.1 Types of
Operating Modes and
Their Selection
Table 3.1 Operating
Mode Selection
49 Note amended
*2 Only modes 0 and 1 are available in the SH7032 and SH7034
ROMless version.
8.11.3 Maximum
Number of States
from BREQ Input to
Bus Release
Figure 8.47 Bus
Release Procedure
174 Description amended
tBACD2
tBRQS
tBACD1
9.1.4 Register
Configuration
Table 9.2 DMAC
Registers
179 *4 added
*4 Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9
are ignored. For details on the register addresses, see section
8.3.5, Area Descriptions.
9.3.4 DMA Transfer
Types 200 Description amended
Line 3
⋅⋅⋅ destination or source must be the SCI or A/D converter
(table 9.4). ⋅⋅⋅
10.1.4 Register
Configuration
Table 10.3 Register
Configuration
230 *2 description amended
*2 Only 0 can be written to clear flags.
10.4.5 Reset-
Synchronized PWM
Mode
Procedure for
Selecting Reset-
Synchronized PWM
Mode (figure 10.31):
2 8 Description amended
4. Set bits CMD1 and CMD0 in TFCR to select reset-synchronized
PWM mode. TIOCA3, TIOCB3, TIOCA4, TIOCB4, TOCXA4, and
TOCXB4 become PWM output pins.

Section Page Description Edition
10.4.
Complementary
PWM Mode
Procedure for
Selecting
Complementary
PWM Mode (Figure
10.33):
271 Description amended
3. Set bits CMD1 and CMD0 in TMDB to select complementary PWM
mode. TIOCA3, TIOCB3, TIOCA4, TIOCB4, TOCXA4, and
TOCXB4 become PWM pins.
10. .15 ITU
Operating Modes
Table 10.18 ITU
Operating Modes
(Channel 0)
301 Table amended
Register Setting
TSNC TMDR TFCR TOCR TIOR0 TCR0
Operating
Mode Sync MDF FDIR PWM Comp PWM
Reset
Sync
PWM Buffer
Output
Level
Select IOA IOB Clear Select Clock Select
Synch-
ronized
preset
SYNC0
= 1 ——√——— —√√ √√

PWM √— — PWM0
= 1 ——— — —√*√√
Output
compare A
function
√— — PWM0
= 0 — — — — IOA2 = 0, others:
don’t care
√√√
Table 10.19 ITU
Operating Modes
(Channel 1)
302 Table amended
Register Setting
TSNC TMDR TFCR TOCR TIOR1 TCR1
Operating
Mode Sync MDF FDIR PWM Comp PWM
Reset
Sync
PWM Buffer
Output
Level
Select IOA IOB Clear Select Clock Select
Synch-
ronized
preset
SYNC1
= 1 ——√——— —√√ √√

PWM √— — PWM1
= 1 ——— — —√*√√
Output
compare A
function
√— — PWM1
= 0 — — — — IOA2 = 0, others:
don’t care
√√√
Table 10.20 ITU
Operating Modes
(Channel 2)
303 Table amended
Register Setting
TSNC TMDR TFCR TOCR TIOR2 TCR2
Operating
Mode Sync MDF FDIR PWM Comp PWM
Reset
Sync
PWM Buffer
Output
Level
Select IOA IOB Clear Select Clock Select
Synch-
ronized
preset
SYNC2
= 1 ——√——— —√√ √√

PWM √— — PWM2
= 1 ——— — —√*√√
Output
compare A
function
√— — PWM2
= 0 — — — — IOA2 = 0, others:
don’t care
√√√
12.1.4 Register
Configuration
Table 12.2 WDT
Registers
337 *4 added
Initial Address
4
Name Abbreviation R/W Value Write
1
Read
2
Timer control/status register TCSR R/(W)*
3
H'18 H'5FFFFB8 H'5FFFFB8
Timer counter TCNT R/W H'00 H'5FFFFB9
Reset control/status register RSTCSR R/(W)*
3
H'1F H'5FFFFBA H'5FFFFBB
Notes: *1 Write by word transfer. A byte or longword write cannot be used.
*2 Read by byte transfer. The correct value cannot be obtained by a word or longword
read.
*3 Only 0 can be written in bit 7, to clear the flag.
*4 Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions

Section Page Description Edition
12.2.2 Timer
Control/Status
Register (TCSR)
338 Note added
Note: * Only 0 can be written, to clear the flag.
13.2. Serial Control
Register 359 Initial value added
Internal clock, SCK pin used for input pin (input signal
is ignored) or output pin (output level is undefined)*2
(Initial value)
Internal clock, SCK pin used for serial clock output*2
(Initial value)
13.2.8 Bit Rate
Register (BRR)
Table 13.3 Bit Rates
and BRR Settings in
Asynchronous Mode
3 7 Note added
Note: Settings with an error of 1% or less are recommended.
Table 13.4 Bit
Rates and BRR
Settings in
Synchronous Mode
3 8 Note deleted
15.2 Register
Configuration
Table 15.2 Pin
Function Controller
Registers
427 Note added
Name Abbreviation R/W Initial Value Address*Access Size
Port A I/O register PAIOR R/W H'0000 H'5FFFFC4 8, 1 , 32
Port A control register 1 PACR1 R/W H'3302 H'5FFFFC8 8, 1 , 32
Port A control register 2 PACR2 R/W H'FF95 H'5FFFFCA 8, 1 , 32
Port B I/O register PBIOR R/W H'0000 H'5FFFFC 8, 1 , 32
Port B control register 1 PBCR1 R/W H'0000 H'5FFFFCC 8, 1 , 32
Port B control register 2 PBCR2 R/W H'0000 H'5FFFFCE 8, 1 , 32
Column address strobe
pin control register CASCR R/W H'5FFF H'5FFFFEE 8, 1 , 32
Note: *Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
1 .2.1 Register
Configuration
Table 1 .1 Port A
Register
442 Note added
Name Abbreviation R/W Initial Value Address*Access Size
Port A data register PADR R/W H'0000 H'5FFFFC0 8, 1 , 32
Note: *Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
1 .3.1 Register
Configuration
Table 1 .3 Port B
Register
443 Note added
Name Abbreviation R/W Initial Value Address*Access Size
Port B data register PBDR R/W H'0000 H'5FFFFC2 8, 1 , 32
Note: *Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
1 .4.1 Register
Configuration
Table 1 .5 Port C
Register
445 Note added
Name Abbreviation R/W Initial Value Address*Access Size
—
Note: *Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
Port C data register PCDR R/W H'5FFFFD0 8, 1 , 32

Section Page Description Edition
19.1.2 Register
Table 19.2 Standby
Control Register
(SBYCR)
4 0 Note added
Name Abbreviation R/W Initial Value Address*Access size
Standby control register SBYCR R/W H'1F H'5FFFFBC 8, 1 , 32
Note: *Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
20.1.2 DC
Characteristics
Table 20.2 DC
Characteristics
4 7 1 . MHz deleted
Table 20. 2 DC
Characteristics Table of 1 . MHz deleted
Table 20.3
Permitted Output
Current Values
471 1 . MHz deleted
20.1.3 AC
Characteristics
(1) Clock Timing
Table 20.4 Clock
Timing
472 1 . MHz deleted
(2) Control Signal
Timing
Table 20.5 Control
Signal Timing
474 1 . MHz deleted
(3) Bus Timing
Table 20. Bus
Timing (1)
478,
479 Description amended
Read data access time 1* t
ACC1
t
cyc
– 30*
4
— ns 20.8, 20.11, 20.12
Read data access time 2* t
ACC2
t
cyc
× (n+2) –
30*
3
— ns 20.9, 20.10,
20.13–20.15
Read data access time from
CAS 2*
t
CAC2
t
cyc
× (n+1) –
25*
3
—ns
Read data access time from
RAS 1*
t
RAC1
t
cyc
× 1.5 – 20 — ns 20.11, 20.12
Read data access time from
RAS 2*
t
RAC2
t
cyc
× (n+2.5)
– 20*
3
—ns
20.13–20.15
20.13–20.15

Data setup time for CAS t
DS
0*5— ns 20.11, 20.13
CAS setup time for RAS t
CSR
10 — ns 20.1 –20.18
Row address hold time t
RAH
10 — ns 20.11, 20.13
Table 20.7 Bus
Timing (2) Table deleted
Table 20.7 Bus
Timing (2) 494 Description amended
Read data access time 1*
4
t
ACC1
t
cyc
– 44 — ns 20.21, 20.24, 20.25
Read data access time 2*
4
t
ACC2
t
cyc
× (n+2) – 44*
2
— ns 20.22, 20.23,
20.2 –20.28

Section Page Description Edition
(4) DMAC Timing
Table 20.8 DMAC
Timing
507 1 . MHz deleted
(5) 1 -bit Integrated
Timer Pulse Unit
Timing
Table 20.9 1 -bit
Integrated Timer
Pulse Unit Timing
509 1 . MHz deleted
( ) Programmable
Timing Pattern
Controller and I/O
Port Timing
Table 20.10
Programmable
Timing Pattern
Controller and I/O
Port Timing
510 1 . MHz deleted
(7) Watchdog Timer
Timing
Table 20.11
Watchdog Timer
Timing
511 1 . MHz deleted
(8) Serial
Communication
Interface Timing
Table 20.12 Serial
Communication
Interface Timing
512 1 . MHz deleted
(9) A/D Converter
Timing
Table 20.13 A/D
Converter Timing
513 1 . MHz deleted
20.1.4 A/D
Converter
Characteristics
Table 20.14 A/D
Converter
Characteristics
51 1 . MHz deleted
20.2 SH7034B 3.3 V
12.5 MHz Version
and 20 MHz
Version*1 Electrical
Characteristics
517 12.5 MHz added

Section Page Description Edition
20.2.1 Absolute
Maximum Ratings
Table 20.15
Absolute Maximum
Ratings
517 Notes amended
Item Symbol Rating Unit
Power supply voltage VCC –0.3 to +4. V
Input voltage (except port C) Vin –0.3 to VCC + 0.3 V
Input voltage (port C) Vin –0.3 to AVCC + 0.3 V
Analog power supply voltage AVCC –0.3 to +4. V
Analog reference voltage AVref –0.3 to AVCC + 0.3 V
Analog input voltage VAN –0.3 to AVCC + 0.3 V
Operating temperature Topr –20 to +75*2˚C
Storage temperature Tstg –55 to +125 ˚C
Caution: Operating the chip in excess of the absolute maximum rating may result in permanent
damage.
Notes: *1 ROMless products only for 20 MHz version
*2 Regular-specification products; for wide-temperature-range products, Topr = –40 to
+85°C
Table 20.1 DC
Characteristics 518, 519 12.5 MHz added
Conditions: VCC = 3.3 V ±0.3V, AVCC = 3.3 V ±0.3V, AVCC = VCC ±0.3V, AVref = 3.0 V to
AVCC, VSS = AVSS = 0 V, φ = 2.5 to 20 MHz*, Ta = –20 to +75°C*2
Notes: * ROMless products only for 20 MHz version
*2 Regular-specification products; for wide-temperature-range products, Ta = –40 to
+85°C
Current Ordinary ICC — 25 — mA f = 12.5 MHz
consumption operation — 35 0 mA f = 20 MHz
Sleep — 20 — mA f = 12.5 MHz
— 30 40 mA f = 20 MHz
Standby — 0.1 5 µA Ta ≤ 50°C
——10 µA50°C < Ta
Table 20.17
Permitted Output
Current Values
521 12.5 MHz added
12.5 MHz 20 MHz
Item Symbol Min Typ Max Min Typ Max Unit
Output low-level
permissible current
(per pin)
IOL ——10 ——10mA
Output low-level
permissible current
(total)
∑ IOL ——80 ——80mA
Output high-level
permissible current
(per pin)
–IOH ——2.0 ——2.0mA
Output high-level
permissible current
(total)
–∑ IOH ——25 ——25mA
Caution: To ensure reliability of the chip, do not exceed the output current values given in table
20.18.

Section Page Description Edition
20.2.3 AC
Characteristics
(1) Clock Timing
Table 20.18 Clock
Timing
522 12.5 MHz added and description amended
12.5 MHz 20 MHz
Item Symbol Min Max Min Max Unit Figures
EXTAL input high level
pulse width tEXH 22 — 15 — ns 20.45
EXTAL input low level
pulse width tEXL 22 — 15 — ns
EXTAL input rise time tEXr —10 —5 ns
EXTAL input fall time tEXf —10 —5 ns
Clock cycle time tcyc 80 500 50 250 ns 20.45, 20.4
Clock high pulse width tCH 30 — 20 — ns 20.4
Clock low pulse width tCL 30 — 20 — ns
Clock rise time tCr —10 —5 ns
Clock fall time tCf —10 —5 ns
Reset oscillation settling
time tOSC1 10 — 10 — ms 20.47
Software standby
oscillation settling time tOSC2 10 — 10 — ms
(2) Control Signal
Timing
Table 20.19 Control
Signal Timing
524 12.5 MHz added and description amended
12.5 MHz 20 MHz
Item Symbol Min Max Min Max Unit Figure
RES setup time tRESS 320 — 200 — ns 20.48
RES pulse width tRESW 20 — 20 — tcyc
NMI reset setup time tNMIRS 320 — 200 — ns
NMI reset hold time tNMIRH 320 — 200 — ns
NMI setup time tNMIS 1 0 — 100 — ns 20.49
NMI hold time tNMIH 80 — 50 — ns
IRQ0–IRQ7 setup time
(edge detection) tIRQES 1 0 — 100 — ns
IRQ0–IRQ7 setup time
(level detection) tIRQLS 1 0 — 100 — ns
IRQ0–IRQ7 hold time tIRQEH 80 — 50 — ns
IRQOUT output delay
time tIRQOD — 80 — 50 ns 20.50
Bus request setup time tBRQS 80 — 50 — ns 20.51
Bus acknowledge delay
time 1 tBACD1 — 80 — 50 ns
Bus acknowledge delay
time 2 tBACD2 — 80 — 50 ns
Bus 3-state delay time tBZD — 80 — 50 ns
(3) Bus Timing
Table 20.20 Bus
Timing (1)
528 Description amended
Read data access time 2*t
ACC2
t
cyc
× (n+2) –
30*3— ns 20.53, 20.54, 20.57–20.59
(3) Bus Timing
Table 20.20 Bus
Timing (2)
530 to
532 Newly added

Section Page Description Edition
(4) DMAC Timing
Table 20.21 DMAC
Timing
54 12.5 MHz added
12.5 MHz 20 MHz
Item Symbol Min Max Min Max Unit Figure
DREQ0, DREQ1 setup time tDRQS 80 — 27 — ns 20. 5
DREQ0, DREQ1 hold time tDRQH 30 — 30 — ns
DREQ0, DREQ1 Pulse width tDRQW 1.5 — 1.5 — tcyc 20.
(5) 1 -bit Integrated
Timer Pulse Unit
Timing
Table 20.22 1 -bit
Integrated Timer
Pulse Unit Timing
547 12.5 MHz added
12.5 MHz 20 MHz
Item Symbol Min Max Min Max Unit Figure
Output compare delay time tTOCD — 100 — 100 ns 20. 7
Input capture setup time tTICS 50 — 35 — ns
Timer clock input setup time tTCKS 50 — 50 — ns 20. 8
Timer clock pulse width
(single edge) tTCKWH/L 1.5 — 1.5 — tcyc
Timer clock pulse width
(both edges) tTCKWL/L 2.5 — 2.5 — tcyc
() Programmable
Timing Pattern
Controller and I/O
Port Timing
Table 20.23
Programmable
Timing Pattern
Controller and I/O
Port Timing
548 Description amended
Conditions: VCC = 3.3 V ±0.3V, AVCC = 3.3 V ±0.3V, AVCC = VCC ±0.3V, AVref = 3.0 V to
AVCC, VSS = AVSS = 0 V, φ = 2.5 to 20 MHz*, Ta = –20 to +75°C*2
Notes: * ROMless products only for 20 MHz version
*2 Regular-specification products; for wide-temperature-range products, Ta = –40 to
+85°C
(7) Watchdog Timer
Timing
Table 20.24
Watchdog Timer
Timing
549 Description amended
Conditions: VCC = 3.3 V ±0.3V, AVCC = 3.3 V ±0.3V, AVCC = VCC ±0.3V, AVref = 3.0 V to
AVCC, VSS = AVSS = 0 V, φ = 2.5 to 20 MHz*, Ta = –20 to +75°C*2
Notes: * ROMless products only for 20 MHz version
*2 Regular-specification products; for wide-temperature-range products, Ta = –40 to
+85°C
(8) Serial
Communication
Interface Timing
Table 20.25 Serial
Communication
Interface Timing
550 Description amended
Conditions: VCC = 3.3 V ±0.3V, AVCC = 3.3 V ±0.3V, AVCC = VCC ±0.3V, AVref = 3.0 V to
AVCC, VSS = AVSS = 0 V, φ = 2.5 to 20 MHz*, Ta = –20 to +75°C*2
Notes: * ROMless products only for 20 MHz version
*2 Regular-specification products; for wide-temperature-range products, Ta = –40 to
+85°C
(9) A/D Converter
Timing
Table 20.2 A/D
Converter Timing
551 Description amended
Conditions: VCC = 3.3 V ±0.3V, AVCC = 3.3 V ±0.3V, AVCC = VCC ±0.3V, AVref = 3.0 V to
AVCC, VSS = AVSS = 0 V, φ = 2.5 to 20 MHz*, Ta = –20 to +75°C*2
Notes: * ROMless products only for 20 MHz version
*2 Regular-specification products; for wide-temperature-range products, Ta = –40 to
+85°C

Section Page Description Edition
20.2.4 A/D
Converter
Characteristics
Table 20.27 A/D
Converter
Characteristics
554 12.5 MHz added
12.5 MHz 20 MHz
Item Min Typ Max Min Typ Max Unit
Resolution 101010 101010bit
Conversion time — — 11.2 — — .7 µS
Analog input capacitance — — 20 — — 20 pF
Permissible signal-source impedance — — 1 — — 1 kΩ
Nonlinearity error*——±4.0 — — ±4.0 LSB
Offset error*——±4.0 — — ±4.0 LSB
Full-scale error*——±4.0 — — ±4.0 LSB
Quantization error*——±0.5 — — ±0.5 LSB
Absolute accuracy — — ±.0 — — ±.0 LSB
Note: *Reference value
A.2.17 Timer Status
Registers 0–4
(TSR0–TSR4)
Table A.18 TSR0–
TSR4 Bit Functions
581 Bit amended
Bit Bit name Value Description
2 Overflow flag (OVF) 0 Clear conditions: 0 is written in OVF after
reading OVF = 1 (Initial value)
1 Set conditions: TCNT value overflows (H'FFFF
? H'0000) or underflows (H'FFFF ? H'0000)
1 Input capture/compare match
flag B (IMFB) 0 Clear conditions: 0 is written in IMFB after reading IMFB = 1 (Initial value)
1 Set conditions: (1) When GRB is functioning as
the output compare register, and TCNT = GRB;
(2) When GRB is functioning as the input
capture register, and the TCNT value is
transferred to GRB by the input capture signal
0 Input capture/compare match
flag A (IMFA) 0 Clear conditions: 0 is written in IMFA after reading IMFA = 1 (Initial value)
1 Set conditions: (1) When GRA is functioning as
the output compare register, and TCNT = GRA;
(2) When GRA is functioning as the input
capture register, and the TCNT value is
transferred to GRA by the input capture signal
A.2.23 Timer Output
Control Register
(TOCR)
Table A.24 TOCR
Bit Functions
587 Table amended
Bit Bit name Value Description
1 Output level select 4 (OLS4) 0 Reverse output of TIOCA3, TIOCA4, TIOCB4
1 Direct output of TIOCA3, TIOCA4, TIOCB4
(Initial value)
0 Output level select 3 (OLS3) 0 Reverse output of TIOCB3, TOCXA4, TOCXB4
1 Direct output of TIOCB3, TOCXA4, TOCXB4
(Initial value)

Section Page Description Edition
A.3 Register Status
in Reset and Power-
Down States
Table A.77 Register
Status in Reset and
Power-Down States
44 *2 added
Watchdog timer (WDT) TCNT Initialized Initialized Held Held
TCSR *1
RSTCR*2Initialized
Serial communication SMR Initialized Initialized Initialized Held
interface (SCI) BRR
SCR
TDR
TSR Held
SSR Initialized
RDR
RSR Held
Notes: *1 Bits 7–5 (OVF, WT/IT, TME) are initialized, bits 2–0 (CKS2–CKS0) are held.
*2 Not initialized in the case of a reset by the WDT.