Hitachi H8/3664 User manual

Hitachi Single-Chip Microcomputer
H8/3664 Series
H8/3664
HD6433664
H8/3663
HD6433663
H8/3662
HD6433662
H8/3661
HD6433661
H8/3660
HD6433660
H8/3664F-ZTAT™
HD64F3664
Hardware Manual
ADE-602-202A
Rev. 2.0
9/25/00
Hitachi, Ltd.

Cautions
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patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.

Preface
The H8/3664 Series of single-chip microcomputers has the high-speed H8/300H CPU at its core,
with many necessary peripheral functions on-chip. The H8/300H CPU instruction set is
compatible with the H8/300 CPU.
The H8/3664 Series includes such peripheral functions as four timers, an I2C bus interface, a serial
communication interface, and a 10-bit A/D converter, so that they can be used as an embedded
microcomputer for a sophisticated control system.
This manual describes the hardware of the H8/3664 Series. For details on the H8/3664 Series
instruction set, refer to the H8/300H Series Programming Manual.
Notes:
When using an on-chip emulator (E10T) for H8/3664 program development and debugging, the
following restrictions must be noted.
1. The NMI pin is reserved for the E10T, and cannot be used.
2. Pins P85, P86, and P87 cannot be used. (In order to use these pins, additional hardware must
be provided on the user board.)
3. Area H'7000 to H'7FFF is used by the E10T, and is not available to the user.
4. Area H'F780 to H'FB7F must on no account be accessed.
5. When the E10T is used, address breaks can be set as available to the user, or for use by the
E10T. If address breaks are set as being used by the E10T, the address break control registers
must not be accessed.
6. When the E10T is used, NMI is an input/output pin (open-drain in output mode), P85 and P87
are input pins, and P86 is an output pin.

Main Revisions and Additions in this Edition
Page Item Description
4 Figure 1.1 Block Diagram TEST pin is amended to TEST pin
43 2.9.2 Notes on Bit Manipulation Example 1 description added
54 3.4.2 Interrupt Edge Select Register 2 (IEGR2) Bit 5 description amended
79 Figure 5.9 Pin Connection when not Using
Subclock Figure amended
88 Table 6.3 Transition Mode after the SLEEP
Instruction Execution and Interrupt Handling *1 description changed
102 Figure 7.4 User Program Mode Figure amended
122 7.9 Flash Memory and Power-Down States
Table 7.10 Flash Memory Operating States Description amended
179 Figure 11.2 Increment Timing with Internal Clock Figure amended
281 14.5.1 Data Transfer Format 1st line, reference figure No.
amended
322 Figure 15.5 I2C Bus Timing R/W is amended to R/W
322 to
324 15.3.2 Master Transmit Operation
Figure 15.6 Example of Master Transmit Mode
Operation Timing (MLS = WAIT = 0)
Description changed
Figure amended
324 to
326 15.3.3 Master Receive Operation
Figure 15.7 Example of Master Receive Mode
Operation Timing (1) (NLS = ACKB = 0, WAIT = 1)
Figure 15.7 Example of Master Receive Mode
Operation Timing (2) (NLS = ACKB = 0, WAIT = 1)
Description changed
Figure amended
326 15.3.4 Slave Receive Operation R/W is amended to R/W
327 Figure 15.8 Example of Slave Receive Mode
Operation Timing (1) (MLS = ACKB = 0) R/W is amended to R/W
328 15.3.5 Slave Transmit Operation Description amended
329 Figure 15.10 Example of Slave Transmit Mode
Operation Timing (MLS = 0) R/W is amended to R/W
332 Figure 15.13 Flowchart for Master Transmit Mode
(Example) Flowchart changed
333 Figure 15.14 Flowchart for Master Receive Mode
(Example) Flowchart changed

Page Item Description
339,
340 15.4 Usage Notes
• Notes on Start Condition Issuance for
Retransmission
Figure 15.17 Flowchart and Timing of Start
Condition Instruction Issuance for Retransmission
Description added
348 16.2.3 A/D Control Register (ADCR) Bit 7 Note added
367 Table 18.2 DC Characteristics (2) Conditions changed
370 Table 18.4 I2C Bus Interface Timing Symbol in SCL and SDA output fall
time amended
372,
373 Table 18.6 A/D Converter Characteristics Min Value in AVcc amended Test Condition of Conversion time
(single mode) amended
373 Table 18.7 Watchdog Timer Characteristics Unit amended
376 to
388 18.3 Electrical Characteristics (Mask ROM Version) Added
411 to
417 A.3 Number of Execution States Added
423 B.2 Register Bits Bit name in ABRKSR amended

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Contents
Section 1 Overview............................................................................................................ 1
1.1 Features .............................................................................................................................. 1
1.2 Internal Block Diagram......................................................................................................4
1.3 Pin Arrangement ................................................................................................................ 5
1.4 Pin Functions...................................................................................................................... 7
Section 2 CPU...................................................................................................................... 11
2.1 Features .............................................................................................................................. 11
2.2 Address Space and Memory Map ...................................................................................... 12
2.3 Register Configuration ....................................................................................................... 15
2.3.1 General Registers.................................................................................................. 16
2.3.2 Program Counter (PC) .......................................................................................... 17
2.3.3 Condition Code Register (CCR) ........................................................................... 17
2.4 Data Formats ...................................................................................................................... 19
2.4.1 General Register Data Formats ............................................................................. 19
2.4.2 Memory Data Formats .......................................................................................... 21
2.5 Instruction Set .................................................................................................................... 22
2.5.1 Instruction Set Overview ...................................................................................... 22
2.5.2 Basic Instruction Formats...................................................................................... 32
2.6 Addressing Modes and Effective Address Calculation...................................................... 33
2.6.1 Addressing Modes................................................................................................. 33
2.6.2 Effective Address Calculation............................................................................... 35
2.7 Basic Bus Cycle.................................................................................................................. 39
2.7.1 Access to On-Chip Memory (RAM, ROM).......................................................... 39
2.7.2 Access to On-Chip Peripheral Modules................................................................ 40
2.8 CPU States.......................................................................................................................... 41
2.8.1 Overview............................................................................................................... 41
2.9 Application Notes............................................................................................................... 42
2.9.1 Notes on Data Access to Empty Areas.................................................................. 42
2.9.2 Notes on Bit Manipulation.................................................................................... 43
2.9.3 Notes on Use of the EEPMOV Instruction ........................................................... 48
Section 3 Exception Handling........................................................................................ 49
3.1 Overview............................................................................................................................ 49
3.1.1 Exception Handling Types.................................................................................... 49
3.2 Reset................................................................................................................................... 49
3.2.1 Reset Sequence...................................................................................................... 49
3.2.2 Reset by Watchdog Timer..................................................................................... 50
3.2.3 Interrupt Immediately after Reset ......................................................................... 50

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3.3 Interrupts ............................................................................................................................ 51
3.3.1 Interrupt and Vector Address................................................................................ 51
3.4 Interrupt Control Registers.................................................................................................53
3.4.1 Interrupt Edge Select Register 1 (IEGR1) ............................................................ 53
3.4.2 Interrupt Edge Select Register 2 (IEGR2) ............................................................ 54
3.4.3 Interrupt Enable Register 1 (IENR1) .................................................................... 55
3.4.4 Interrupt Flag Register 1 (IRR1)........................................................................... 56
3.4.5 Wakeup Interrupt Flag Register (IWPR) .............................................................. 57
3.5 Interrupt Sources ................................................................................................................ 58
3.5.1 External Interrupts................................................................................................. 58
3.5.2 Internal Interrupts.................................................................................................. 58
3.5.3 Interrupt Operations.............................................................................................. 59
3.5.4 Interrupt Response Time....................................................................................... 62
3.6 Trap Instruction.................................................................................................................. 62
3.7 Application Notes............................................................................................................... 62
3.7.1 Notes on Stack Area Use ...................................................................................... 62
3.7.2 Notes on Rewriting Port Mode Registers.............................................................. 63
Section 4 Address Break.................................................................................................. 67
4.1 Overview............................................................................................................................ 67
4.1.1 Block Diagram...................................................................................................... 67
4.1.2 Register Configuration.......................................................................................... 68
4.2 Register Descriptions.......................................................................................................... 68
4.2.1 Address Break Control Register (ABRKCR)........................................................ 68
4.2.2 Address Break Status Register (ABRKSR) .......................................................... 70
4.2.3 Break Address Registers (BARH, BARL)............................................................ 71
4.2.4 Break Data Registers (BDRH, BDRL) ................................................................. 72
4.3 Operation............................................................................................................................ 72
Section 5 Clock Pulse Generators.................................................................................. 75
5.1 Overview............................................................................................................................ 75
5.1.1 Block Diagram...................................................................................................... 75
5.1.2 System Clock and Subclock.................................................................................. 75
5.2 System Clock Generator..................................................................................................... 76
5.3 Subclock Generator............................................................................................................ 78
5.4 Prescalers............................................................................................................................ 79
5.5 Usage Notes........................................................................................................................ 80
5.5.1 Note on Oscillators................................................................................................ 80
5.5.2 Notes on Board Design ......................................................................................... 80
Section 6 Power-down Modes........................................................................................ 81
6.1 Overview............................................................................................................................ 81
6.1.1 Register Configuration.......................................................................................... 81

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6.2 Register Descriptions.......................................................................................................... 82
6.2.1 System Control Register 1 (SYSCR1).................................................................. 82
6.2.2 System Control Register 2 (SYSCR2).................................................................. 83
6.2.3 Module Standby Control Register 1 (MSTCR1) .................................................. 85
6.3 Mode Transition Conditions............................................................................................... 87
6.4 Sleep Mode......................................................................................................................... 90
6.4.1 Transition to the Sleep Mode................................................................................ 90
6.4.2 Clearing the Sleep Mode....................................................................................... 90
6.5 Standby Mode .................................................................................................................... 90
6.5.1 Transition to the Standby Mode............................................................................ 90
6.5.2 Clearing the Standby Mode................................................................................... 91
6.5.3 Oscillator Settling Time after the Standby Mode is Cleared ................................ 91
6.6 Subsleep Mode ................................................................................................................... 92
6.6.1 Transition to the Subsleep Mode .......................................................................... 92
6.6.2 Clearing the Subsleep Mode ................................................................................. 92
6.7 Subactive Mode.................................................................................................................. 93
6.7.1 Transition to the Subactive Mode ......................................................................... 93
6.7.2 Clearing the Subactive Mode................................................................................ 93
6.8 Active Mode....................................................................................................................... 94
6.8.1 Transition to the Active Mode .............................................................................. 94
6.8.2 Transition from the Active Mode to Other Modes................................................ 94
6.8.3 Operating Frequency in the Active Mode............................................................. 94
6.9 Direct Transition ................................................................................................................ 95
6.9.1 Direct Transition Time.......................................................................................... 95
6.10 Module Standby Mode....................................................................................................... 96
Section 7 ROM.................................................................................................................... 97
7.1 Features .............................................................................................................................. 97
7.2 Overview............................................................................................................................ 98
7.2.1 Block Diagram...................................................................................................... 98
7.2.2 On-board Programming Mode.............................................................................. 99
7.2.3 Block Configuration.............................................................................................. 103
7.2.4 Pin Configuration.................................................................................................. 103
7.2.5 Register Configuration.......................................................................................... 104
7.3 Register Descriptions.......................................................................................................... 104
7.3.1 Flash Memory Control Register 1 (FLMCR1)...................................................... 104
7.3.2 Flash Memory Control Register 2 (FLMCR2)...................................................... 106
7.3.3 Erase Block Register 1 (EBR1) ............................................................................ 107
7.3.4 Flash Memory Power Control Register (FLPWCR)............................................. 108
7.3.5 Flash Memory Enable Register (FENR)............................................................... 108
7.4 Boot Mode.......................................................................................................................... 109
7.4.1 Automatic SCI Bit Rate Adjustment..................................................................... 111
7.4.2 Programming Control Program Area.................................................................... 111

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7.4.3 Notes on Use of Boot Mode.................................................................................. 112
7.5 User Program Mode ........................................................................................................... 112
7.6 Programming/Erasing Flash Memory................................................................................ 113
7.6.1 Program/Program-Verify ...................................................................................... 114
7.6.2 Erase/Erase-Verify................................................................................................ 117
7.6.3 Interrupts during Flash Memory Programming/Erasing....................................... 117
7.7 Protection............................................................................................................................ 119
7.7.1 Hardware Protection.............................................................................................. 119
7.7.2 Software Protection............................................................................................... 120
7.7.3 Error Protection..................................................................................................... 120
7.8 Interrupt Handling when Programming/Erasing Flash Memory........................................ 121
7.9 Flash Memory and Power-Down States............................................................................. 122
7.10 Flash Memory Programmer Mode ..................................................................................... 122
7.10.1 Socket Adapter Pin Correspondence Diagram...................................................... 123
7.10.2 Programmer Mode Operation................................................................................ 125
7.10.3 Memory Read Mode.............................................................................................. 126
7.10.4 Auto-Program Mode ............................................................................................. 129
7.10.5 Auto-Erase Mode.................................................................................................. 131
7.10.6 Status Read Mode.................................................................................................. 133
7.10.7 Status Polling ........................................................................................................ 134
7.10.8 Programmer Mode Transition Time...................................................................... 134
7.10.9 Notes on Memory Programming........................................................................... 135
Section 8 RAM.................................................................................................................... 137
8.1 Overview............................................................................................................................ 137
8.1.1 Block Diagram...................................................................................................... 137
Section 9 I/O Ports ............................................................................................................. 139
9.1 Overview............................................................................................................................ 139
9.2 Port 1 .................................................................................................................................. 140
9.2.1 Overview............................................................................................................... 140
9.2.2 Register Configuration and Description................................................................ 140
9.2.3 Port Data Register 1 (PDR1)................................................................................. 141
9.2.4 Port Control Register 1 (PCR1) ............................................................................ 141
9.2.5 Port Pull-Up Control Register 1 (PUCR1)............................................................ 141
9.2.6 Port Mode Register 1 (PMR1) .............................................................................. 142
9.2.7 Pin Functions......................................................................................................... 144
9.2.8 MOS Input Pull-Up............................................................................................... 145
9.3 Port 2 .................................................................................................................................. 146
9.3.1 Overview............................................................................................................... 146
9.3.2 Register Configuration and Description................................................................ 146
9.3.3 Port Data Register 2 (PDR2)................................................................................. 146
9.3.4 Port Control Register 2 (PCR2) ............................................................................ 147