HP 16550A Service manual

User’s Reference
Publication number 16550-97006
August 1997
For Safety information, Warranties, and Regulatory
information, see the pages behind the Index
•Copyright Hewlett-Packard Company 1992 – 1998
All Rights Reserved
HP 16550A
100-MHz State/500-MHz Timing
Logic Analyzer

ii

In This Book
The User’s Reference contains field and
feature definitions. Use this manual for
information on what the menu fields do,
what they are used for, and how the
features work.
The manual is divided into chapters
covering general product information,
probing, and separately tabbed chapters
for each analyzer menu. Also, chapters
on error messages and instrument
specifications are provided.
In the Configuration menu you have the
choice of configuring an analyzer as
either a State analyzer or a Timing
analyzer. Some menus in the analyzer
will change depending on the analyzer
type you choose. For example, since a
Timing analyzer does not use external
clocks, the clock assignment fields in the
Format menu will not be available.
If a menu field is only available to a
particular analyzer type, the field is
designated (Timing only) or (State only)
after the field name. If no designation is
shown, the field is available for both
types.
GeneralInformation
1
Probing
2
The Configuration Menu
3
The Format Menu
4
The Trigger Menu
5
The Listing Menu
6
The Waveform Menu
7
The Chart Menu
8
The Compare Menu
9
The Mixed Display Menu
10
ErrorMessages
11
Specifications and
Characteristics
12
Installation and Testing
13
Index
iii

iv

Table of Contents
1 General Information
Configuration Capabilities 1–3
Key Features 1–4
Accessories Supplied 1–5
Accessories Available 1–6
2 Probing
General Purpose Probing System Description 2–7
Assembling the Probing System 2–11
3 The Configuration Menu
Name Field 3–3
Type Field 3–4
Unassigned Pods List 3–5
Activity Indicators 3–7
4 The Format Menu
State Acquisition Mode Field (State only) 4–4
Timing Acquisition Mode Field (Timing only) 4–5
Clock Inputs Display 4–13
Pod Field 4–14
Pod Clock Field (State only) 4–15
Pod Threshold Field 4–19
Master and Slave Clock Field (State only) 4–20
Setup/Hold Field (State only) 4–22
Symbols Field 4–24
Label Assignment Fields 4–24
Rolling Labels and Pods 4–24
Label Polarity Fields 4–25
Bit Assignment Fields 4–26
Contents–1

5 The Trigger Menu
Trigger Sequence Levels 5–6
Modify Trigger Field 5–8
Pre-defined Trigger Macros 5–11
Using Macros to Create a Trigger Specification 5–13
Timing Trigger Macro Library 5–14
State Trigger Macro Library 5–16
Modifying the User-level Macro 5–19
Resource Terms 5–26
Assigning Resource Term Names and Values 5–28
Label and Base Fields 5–32
Arming Control Field 5–33
Acquisition Control 5–36
Trigger Position Field 5–37
Sample Period Field 5–38
Branches Taken Stored / Not Stored Field 5–38
Count Field (State only) 5–39
6 The Listing Menu
Markers Field 6–4
Pattern Markers 6–5
Find X-pattern / O-pattern Field 6–6
Pattern Occurrence Fields 6–7
From Trigger / Start / X Marker Field 6–8
Specify Patterns Field 6–9
Label / Base Roll Field 6–12
Stop Measurement Field 6–13
Clear Pattern Field 6–16
Contents
Contents–2

Time Markers 6–17
Trig to X / Trig to O Fields 6–18
Statistics Markers 6–19
States Markers (State only) 6–21
Trig to X / Trig to O Fields 6–22
Data Roll Field 6–23
Label and Base Fields 6–24
Label / Base Roll Field 6–24
7 The Waveform Menu
Acquisition Control Field 7–5
Accumulate Field 7–6
States Per Division Field (State only) 7–7
Seconds Per Division Field (Timing only) 7–8
Delay Field 7–9
Sample Period Display (Timing only) 7–10
Markers Field 7–12
Pattern Markers 7–13
X-pat / O-pat Occurrence Fields 7–14
From Trigger / Start / X Marker Field 7–15
X to O Display Field (Timing only) 7–16
Center Screen Field 7–17
Specify Patterns Field 7–18
Label / Base Roll Field 7–21
Stop Measurement Field 7–22
Clear Pattern Field 7–25
Time Markers 7–26
Trig to X / Trig to O Fields 7–27
Marker Label / Base and Display 7–28
Contents
Contents–3

Statistics Markers 7–29
States Markers (State only) 7–31
Trig to X / Trig to O Fields 7–32
Marker Label / Base and Display 7–33
Waveform Display 7–34
Blue Bar Field 7–36
Channel Mode Field 7–38
Module and Label Fields 7–40
Action Insert/Replace Field 7–41
Delete and Delete All Fields 7–42
Waveform Size Field 7–43
8 The Chart Menu
Selecting the Axes for the Chart 8–6
Y-axis Label Value Field 8–7
X-axis Label / State Type Field 8–8
Scaling the Axes 8–9
Min and Max Scaling Fields 8–10
Markers / Range Field 8–11
Pattern Markers 8–12
Find X-pattern / O-pattern Field 8–13
Pattern Occurrence Fields 8–14
From Trigger / Start / X Marker Fields 8–15
Specify Patterns Field 8–16
Label / Base Roll Field 8–18
Stop Measurement Field 8–19
Clear Pattern Field 8–22
Contents
Contents–4

Time Markers 8–23
Trig to X / Trig to O Fields 8–24
Statistics Markers 8–25
States Markers 8–27
Trig to X / Trig to O Fields 8–28
9 The Compare Menu
Reference Listing Field 9–5
Difference Listing Field 9–6
Copy Listing to Reference Field 9–8
Find Error Field 9–9
Compare Full / Compare Partial Field 9–10
Mask Field 9–11
Specify Stop Measurement Field 9–12
Data Roll Field 9–15
Bit Editing Field 9–16
Label and Base Fields 9–17
Label / Base Roll Field 9–17
10 The Mixed Display Menu
The Mixed Display Menu 10–2
Intermodule Configuration 10–3
Inserting Waveforms 10–4
Interleaving State Listings 10–5
Time-Correlated Displays 10–7
Markers 10–8
Contents
Contents–5

11 Error Messages
Error Messages 11–3
Warning Messages 11–6
Advisory Messages 11–9
12 Specifications and Characteristics
Specifications 12–3
Characteristics 12–4
13 Installation and Testing
To inspect the module 13–3
To prepare the mainframe 13–3
To configure a one-card module 13–5
To configure a two-card module 13–6
To install the module 13–8
To test the module 13–10
To perform the self-tests 13–10
To clean the logic analyzer module 13–12
Index
Contents
Contents–6

1
General Information

Logic Analyzer Description
The HP 16550A State/Timing Analyzer module is part of a new
generation of general-purpose logic analyzers. The HP 16550A
module is used with the HP 16500B/C mainframe, which is designed
as a stand-alone instrument for use by digital and microprocessor
hardware and software designers. The HP 16500B/C mainframe has
HP-IB and RS-232-C interfaces for hard copy printouts and control by
a host computer.
The HP 16550A State/Timing Analyzer module has 96 data channels,
and six clock/data channels. A second HP 16550A card can be added
to expand the module to 204 data and clock/data channels.
Memory depth is 4 Kbytes in all pod pair groupings, or 8 Kbytes on
just one pod (half channels). All resource terms can be assigned to
either configured analyzer machine.
Measurement data is displayed as data listings or waveforms, and can
be plotted on a chart or compared to a reference image.
The 100-MHz state analyzer has master, slave, and demultiplexed
clocking modes available. Measurement data can be stamped with
either state or time tags. For triggering and data storage, the state
analyzer uses 12 sequence levels with two-way branching, 10 pattern
resource terms, 2 range terms, and 2 timers/counters.
The 500-MHz timing analyzer has conventional, transitional, and glitch
timing modes with variable width, depth, and speed selections.
Sequential triggering uses 10 sequence levels with two-way branching,
10 pattern resource terms, 2 range terms, 2 timers/counters and 2
edge/glitch terms.
Defining a trigger specification is as easy as picking a predefined
macro from a trigger macro library. Trigger macros can be used by
themselves or in combination with each other.
1–2

Configuration Capabilities
The HP 16550A can be configured as a single- or two-card module. The
number of data channels range from 102 channels using just one HP 16550A,
up to 204 channels when a second HP 16550A is connected. A half-channel
acquisition mode is available which reduces the channel width by half, but
doubles memory depth from 4K-deep to 8K-deep per channel.
The configuration guide below illustrates the channel width and memory
depth combinations in all acquisition modes with a one or two card module.
State Analyzer
•Unused clock channels can be used as data channels
•Time or State tags reduces memory by half. However, full depth is
retained if you leave one pod pair unassigned.
•Maximum of 6 clocks in a two-card module.
Timing Analyzer
•Unused clock channels can be used as data channels
General Information
Configuration Capabilities
1–3

Key Features
•100-MHz state and 500-MHz timing acquisition speed.
•96 data/6 clock channels, expandable to 198 data/6 clock channels.
•Lightweight passive probes for easy hookup and compatibility with
previous HP logic analyzers and preprocessors.
•Variable setup/hold time, 3.5 ns window.
•External arming to/from other modules through the intermodule bus.
•4 Kbytes deep memory on all channels with 8 Kbytes in half channel
modes.
•Marker measurements.
•12 levels of trigger sequencing for state and 10 levels of sequential
triggering for Timing.
•Both state and timing analyzers can use 10 pattern resource terms, two
range terms, and two timer/counters to qualify and trigger on data. The
timing analyzer also has two edge terms available.
•Predefined trigger macros for easy configuration of trigger specifications.
•100-MHz time and number-of-states tagging.
•Full programmability.
•Mixed State/Timing and State/State (interleaved) display.
•Compare, Chart, and Waveform displays.
General Information
KeyFeatures
1–4

Accessories Supplied
The table below lists the accessories supplied with your logic analyzer. If any
of these accessories are missing, contact your nearest Hewlett-Packard Sales
Office. If you need additional accessories, refer to the Accessories for HP
Logic Analyzers brochure.
Table 1-1 AccessoriesSupplied
Accessory HP Part No. Quantity
Probe tip assemblies 01650-61608 6
Probe cables 16550-61601 3
Grabbers (20 perpack) 5090-4356 6
Extra probe leads (5 perpack) 5959-9333 1 pkg
Probe cable and podlabels 01650-94310 1
Probe cable ID clip 16500-41201 1
Operating system disks Call 1
User’s Reference Call 1
General Information
Accessories Supplied
1–5

Accessories Available
There are a number of accessories available that will make your measurement
tasks easier and more accurate. You will find these listed in Accessories for
HP Logic Analyzers.
Preprocessor Modules
The preprocessor module accessories enable you to quickly and easily
connect the logic analyzer to your microprocessor under test.
Included with each preprocessor module is a 3.5-inch disk which contains a
configuration file and an inverse assembler file. When you load the
configuration file, it configures the logic analyzer for making state
measurements on the microprocessor for which the preprocessor is designed.
Configuration files from other analyzer modules can also be loaded. For
information on translating other configuration files into the analyzer, refer to
"Preprocessor File Configuration Translation and Pod Connections" in the
Probing chapter.
The inverse assembler file is a software routine that will display captured
information in a specific microprocessor’s mnemonics. The DATA field in the
State Listing is replaced with an inverse assembly field. The inverse
assembler software is designed to provide a display that closely resembles
the original assembly language listing of the microprocessor’s software. It also
identifies the microprocessor bus cycles captured, such as Memory Read,
Interrupt Acknowledge, or I/O write.
A list of preprocessor modules is found in Accessories for HP Logic
Analyzers. Descriptions of the preprocessor modules are found with the
preprocessor module accessories.
General Information
Accessories Available
1–6

2
Probing

Probing
This chapter contains a description of the probing system for the logic
analyzer. It also contains the information you need for connecting the
probe system components to each other, to the logic analyzer, and to
the system under test.
Probing Options
You can connect the logic analyzer to your system under test in one of
the following ways:
•The standard general purpose probing (provided).
•HP E2445A User-Definable Interface (optional).
•Direct connection to a 20-pin, 3M-Series type header connector
using the termination adapter (optional).
•Microprocessor and bus-specific interfaces (optional).
General-Purpose Probing
General-purpose probing involves connecting the logic analyzer
probes directly to your target system without using any interface.
General purpose probing does not limit you to specific hook up
schemes, as for example, the probe interface does. General-purpose
probing uses grabbers that connect to both through hole and surface
mount components.
General-purpose probing is the standard probing option provided with
the logic analyzer. There is a full description of its components and
use later in this chapter.
2–2

The HP E2445A User-Definable Interface
The optional HP E2445A User-Definable Interface allows you to
connect the logic analyzer to the microprocessor in your target
system. The HP E2445A includes a breadboard that you custom-wire
for your system.
You will find additional information about the HP E2445A in the
Accessories for HP Logic Analyzers brochure.
The Termination Adapter
The optional termination adapter allows you to connect the logic
analyzer probe cables directly to test ports on your target system
without the probes.
The termination adapter is designed to connect to a 20-pin (2x10),
4-wall, low-profile header connector, 3M-Series 3592 or equivalent.
Termination Adapter
Probing
2–3

Microprocessor and Bus-Specific Interfaces
There are a number of microprocessor and bus-specific interfaces
available as optional accessories which are listed in Microprocessor
and Bus Interfaces and Software Accessories for HP Logic
Analyzers. Microprocessors are supported by Universal Interfaces or
Preprocessor Interfaces, or in some cases both.
Preprocessor interfaces are aimed at hardware turn-on and
hardware/software integration, and will provide the following:
•All clocking and demultiplexing circuits needed to capture the
system’s operation.
•Additional status lines to further decode the operation of the CPU.
•Inverse assembly software to translate logic levels captured by the
logic analyzer into microprocessor mnemonics.
•Bus interfaces to support bus analysis for HP-IB, RS-232-C, RS-449,
SCSI, VME, VXI, ISA, EISA, MCA, FDDI, Futurebus+, JTAG, SBus,
PCI, and PCMCIA.
Universal Interfaces are aimed at initial hardware turn-on, and will
provide fast, reliable, and convenient connections to the
microprocessor system. Universal Interfaces do not provide inverse
assembly of software instructions.
Probing
2–4