HP 16555A User manual

Service Guide
Publication number 16555-97012
First edition, October 1996
For Safety information, Warranties, and Regulatory
information, see the pages at the end of the book.
Copyright Hewlett-Packard Company 1987–1996
All Rights Reserved.
HP 16555A/D 110-MHz State/
500-MHz Timing Logic Analyzers

Printed in USA July 2004
Notice
Hewlett-Packard to Agilent Technologies Transition
This manual may contain references to HP or Hewlett-Packard. Please note that Hewlett-
Packard’s former test and measurement, semiconductor products and chemical analysis
businesses are now part of Agilent Technologies. To reduce potential confusion, the only
change to product numbers and names has been in the company name prefix: where a
product name/number was HP XXXX the current name/number is now Agilent XXXX. For
example, model number HP8648 is now model number Agilent 8648.
Contacting Agilent Sales and Service Offices
The sales and service contact information in this manual may be out of date. The latest
service and contact information for your location can be found on the Web at:
http://www.agilent.com/find/assist
If you do not have access to the Internet, contact your field engineer or the nearest sales
and service office listed below. In any correspondence or telephone conversation, refer to
your instrument by its model number and full serial number.
United States
(tel) 1 800 452 4844
(fax) 1 800 829 4433
Latin America
(tel) [phone]
(fax) [phone]
New Zealand
(tel) 0 800 738 378
(fax) 64 4 495 8950
Canada
(tel) [phone]
(fax) [phone]
Japan
(tel) (81) 426 56 7832
(fax) (81) 426 56 7840
Asia Pacific
(tel) (852) 3197 7777
(fax) (852) 2506 9284
Europe
(tel) (31 20) 547 2323
(fax) (31 20) 547 2390
Australia
(tel) 1 800 629 485
(fax) (61 3) 9210 5947

HP 16555A/D 110-MHz State/500-MHz Timing
Logic Analyzers
The HP 16555A/D are 110-MHz State/500-MHz Timing Logic Analyzer modules for
the HP 16500B/C Logic Analysis Systems. The HP 16555A/D offer high performance
measurement capability. The HP 16555D has twice the memory depth of the
HP 16555A.
Features
Some of the main features of the HP 16555A/D are as follows:
•64 data channels
•4 clock/data channels
•1016K memory depth per channel for the HP 16555A, 2032K memory depth per
channel for the HP 16555D
•110 MHz maximum state acquisition speed
•500 MHz maximum timing acquisition speed
•Expandable to 204 channels
Service Strategy
The service strategy for this instrument is the replacement of defective assemblies.
This service guide contains information for finding a defective assembly by testing
and servicing the HP 16555A/D state and timing analyzer modules.
This module can be returned to Hewlett-Packard for all service work, including
troubleshooting. Contact your nearest Hewlett-Packard Sales Office for more details.
ii

The HP 16555A/D Logic Analyzer
iii

In This Book
This book is the service guide for the HP 16555A/D 110-MHz State/500-MHz Timing Logic
Analyzer module. Place this service guide in the 3-ring binder supplied with your
HP 16500B Logic Analysis System Service Manual or HP 16500C Logic Analysis System
Service Manual.
This service guide is divided into eight chapters.
Chapter 1 contains information about the module and includes accessories for the module,
specifications and characteristics of the module, and a list of the equipment required for
servicing the module.
Chapter 2 tells how to prepare the module for use.
Chapter 3 gives instructions on how to test the performance of the module.
Chapter 4 contains calibration instructions for the module.
Chapter 5 contains self-tests and flowcharts for troubleshooting the module.
Chapter 6 tells how to replace the module and assemblies of the module and how to return
them to Hewlett-Packard.
Chapter 7 lists replaceable parts, shows an exploded view, and gives ordering information.
Chapter 8 explains how the analyzer works and what the self-tests are checking.
iv

Contents
1 General Information
Accessories 1-2
Operating System 1-2
Specifications 1-3
Characteristics 1-4
Supplemental Characteristics 1-4
Recommended Test Equipment 1-7
2 Preparing For Use
To inspect the module 2-2
To prepare the mainframe 2-3
To configure a one-card module 2-4
To configure a multicard module 2-5
To install the module 2-10
To turn on the system 2-11
To test the module 2-11
To install the ferrites 2-12
3 Testing Performance
To perform the self-tests and make the test connectors 3-3
To test the threshold accuracy 3-9
To test the single-clock, single-edge, state acquisition 3-18
To test the multiple-clock, multiple-edge, state acquisition 3-30
To test the single-clock, multiple-edge, state acquisition 3-41
To test the time interval accuracy 3-51
To perform the multicard test 3-57
Performance Test Record 3-67
4 Calibrating
5 Troubleshooting
To use the flowcharts 5-2
To run the self-tests 5-7
To run the Board Verification tests 5-8
To run the Acquisition IC Verification tests 5-10
To test the cables 5-13
To test the auxiliary power 5-17
6 Replacing Assemblies
To remove the module 6-2
To replace the circuit board 6-3
To replace the module 6-3
To replace the probe cable 6-5
To replace the Reference Clock cable 6-6
To return assemblies 6-7
v

7 Replaceable Parts
Replaceable Parts Ordering 7-2
Replaceable Parts List 7-3
Exploded View 7-5
8 Theory of Operation
Block-Level Theory 8-2
Self-Tests Description 8-6
Contents
vi

1
Accessories 1-2
Operating System 1-2
Specifications 1-3
Characteristics 1-4
Supplemental Characteristics 1-4
Recommended Test Equipment 1-7
General Information

General Information
This chapter lists the accessories, the specifications and characteristics, and the
recommended test equipment.
Accessories
The following accessories are supplied with the HP 16555A/D Logic Analyzer.
Accessories Supplied HP Part Number
Probe Tip Assembly, Qty 4 01650-61608
Grabbers, Qty 4 packages 5090-4356
Extra Probe Leads, Qty 1 package 5959-9333
Extra Probe Grounds, Qty 4 packages 5959-9334
Probe Cables, Qty 2 16555-61606
Probe Cable and Pod Labels, Qty 1 01650-94310
Double Probe Adapter, Qty 1 16542-61607
Ferrite Core Assembly, Qty 2 16555-60001
Accessories Available
The accessories available for the HP 16555A/D are listed in the Accessories for HP Logic
Analyzers brochure.
Operating System
With HP 16500B Mainframe
The HP 16555D Logic Analyzer requires operating system version v3.10 or higher.
For the HP 16555A, the version of the operating system software depends on the
programmable logic device that is the CPU interface. To verify the version of the
programmable device, first locate the device, which is at the front of the HP 16555A board. If
the programmable device has part number 16555-80001, then the device requires operating
system version v2.xx, and the maximum state acquisition speed is 100 MHz. If the device has
part number 16555-80002 or higher, then the device requires operating system v3.00 or
higher, and the maximum state acquisition speed is 110 MHz for single-clock, single-edge
clocking mode. You should always use the latest release, and must use version numbers that
are compatible with your device.
With HP 16500C Mainframe
The HP 16555A/D Logic Analyzer requires operating system version v1.00 or higher.
1–2

Specifications
The specifications are the performance standards against which the product is tested.
Minimum State Clock Pulse Width 13.5 ns
Threshold Accuracy ±(100 mV + 3% of threshold setting)
Clock Scheme:
Single Clock, Single Edge:
Setup/Hold Time: 1 0.0/3.5 ns through 3.5/0.0 ns,
adjustable in 500-ps increments
Maximum State Speed 110 MHz 2
Minimum Master-to-Master Clock Time 19.09 ns 2
Single Clock, Multiple Edges:
Setup/Hold Time: 1 0.0/4.0 ns through 4.0/0.0 ns,
adjustable in 500-ps increments
Maximum State Speed 100 MHz
Minimum Master-to-Master Clock Time 110.0 ns
Multiple Clocks, Multiple Edges:
Setup/Hold Time: 1 0.0/4.5 ns through 4.5/0.0 ns,
adjustable in 500-ps increments
Maximum State Speed 100 MHz
Minimum Master-to-Master Clock Time 110.0 ns
1Specified for an input signal VH = −0.9 V, VL = −1.7 V, and threshold = −1.3 V.
2An HP 16555A in an HP 16500B mainframe using operatingsystem v2.xx has maximum state speed of 100MHz andminimum
Master-to-Master Clock Time of 10.0 ns for single-clock, single-edge clocking. 110-MHz single-clock state acquisition mode is
available withHP 16500B mainframe operating system v3.00 or higher orHP 16500C mainframeoperatingsystem v1.00 or higher
(refer to "Operating System"). The maximum state acquisition speedis 100 MHz for all other clocking modes.
General Information
Specifications
1–3

Characteristics
The characteristics are not specifications, but are included as additional information.
Full Channel Half Channel *
Maximum State Clock Rate 110 MHz Not applicable
Maximum Conventional Timing Rate 250 MHz 500 MHz
Channel Count per Card 68 34
Channel Count per Three-Card Module 204 102
Memory Depth (HP 16555A) 1016K 2088K
Memory Depth (HP 16555D) 2032K 4177K
* Half channel mode is only available for timing analysis.
Supplemental Characteristics
Probes
Input Resistance 100 kΩ, ±2%
Input Capacitance ~ 8 pF
Minimum Voltage Swing 500 mV, peak-to-peak
Maximum Input Voltage ±40 V, CAT I
Threshold Range ±6.0 V, adjustable in 50-mV increments
Clock In/Out
Clock Output 850 mV @100 MHz, terminated into 50 Ω.
Clock Input 1.0 V @100 MHz, ±20 Vdc offset (clock input port
is terminated internally to 50 Ω).
State Analysis
State/Clock Qualifiers 4
Time Tag Resolution*8 ns
Maximum Time Count Between States 34 seconds
Maximum State Tag Count*4.29 x 109
Timing Analysis
Sample Period Accuracy 0.01 % of sample period
Channel-to-Channel Skew 2 ns, typical
Time Interval Accuracy ±[sample period + channel-to-channel skew
+(0.01%)(time reading)]
General Information
Characteristics
1–4

Triggering
Sequencer Speed 125 MHz, maximum
State Sequence Levels 12
Timing Sequence Levels 10
Maximum Occurrence Counter Value 1,048,575
Pattern Recognizers 10
Maximum Pattern Width 68 channels in a one-card configuration.
204 channels in a three-card configuration.
Range Recognizers 2
Range Width 32 bits each
Timers 2
Timer Value Range 400 ns to 500 seconds
Glitch/Edge Recognizers 2 (timing only)
Maximum Glitch/Edge Width 68 channels in a one-card configuration.
204 channels in a three-card configuration.
*Maximum state clock rate with time or statetags on is 110 MHz. When all pods are assigned to a state ortiming machine,
time or state tags halve thememory depth.
Measurement and Display Functions
Arming Each module can be armed by the RUN key, by the external PORT IN, or by
another module via the Intermodule Bus (IMB).
Displayed Waveforms 24 lines maximum, with scrolling across 96 waveforms.
Measurement Functions
Run/Stop Functions Run Starts acquisition of data in specified trace mode.
Stop In single trace mode or the first run of a repetitive acquisition, STOP halts
acquisition and displays the current acquisition data. For subsequent runs in repetitive
mode, STOP halts acquisition of data and does not change the current display.
Trace Mode Single mode acquires data once per trace specification. Repetitive mode
repeats single mode acquisitions until stop is pressed or until the time interval between
two specified patterns is less than or greater than a specified value, or within or not within
a specified range.
Indicators
Activity Indicators Provided in the Configuration and Format menus for identifying
high, low, or changing states on the inputs.
Markers Two markers (X and 0) are shown as dashed lines on the display.
Trigger Displayed as a vertical dashed line in the Timing Waveform display and as line 0
in the State Listing display.
General Information
Supplemental Characteristics
1–5

Data Entry/Display
Labels Channels may be grouped together and given a 6-character name. Up to
126 labels in each analyzer may be assigned with up to 32 channels per label.
Display Modes State listing, State Waveforms, Chart, Compare Listing, Compare
Difference Listing, Timing Waveforms, and Timing Listings. State Listing, Timing
Waveforms and Oscilloscope Waveforms can be time-correlated on the same displays.
Timing Waveform Pattern readout of timing waveforms at X or 0 marker.
Bases Binary, Octal, Decimal, Hexadecimal, ASCII (display only), Two’s Complement,
and User-defined symbols.
Symbols 1,000 maximum. Symbols can be downloaded over RS-232 or HP-IB.
Marker Functions
Time Interval The X and 0 markers measure the time interval between one point on a
timing waveform and trigger, two points on the same timing waveform, two points on
different waveforms, or two states (time tagging on).
Delta States (state analyzer only) The X and 0 markers measure the number of
tagged states between one state and trigger or between two states.
Patterns The X and 0 markers can be used to locate the nth occurrence of a specified
pattern from trigger, or from the beginning of data. The 0 marker can also find the nth
occurrence of a pattern from the X marker.
Statistics X and 0 marker statistics are calculated for repetitive acquisitions. Patterns
must be specified for both markers and statistics are kept only when both patterns can be
found in an acquisition. Statistics are minimum X to 0 time, maximum X to 0 time,
average X to 0 time, and ratio of valid runs to total runs.
Auxiliary Power
Power Through Cables 1/3 amp at 5 V maximum per cable
Operating Environment
Temperature Instrument, 0 °C to 55 °C (+32 °F to 131 °F).
Probe lead sets and cables,
0 °C to 65 °C (+32 °F to 149 °F).
Humidity Instrument, probe lead sets, and cables, up to
95% relative humidity at +40 °C(+122 °F).
Altitude To 4600 m (15,000 ft).
Vibration Operating: Random vibration 5 to 500 Hz,
10 minutes per axis, ≈ 0.3 g (rms).
Non-operating: Random vibration 5 to 500 Hz,
10 minutes per axis, ≈ 2.41 g (rms);
and swept sine resonant search, 5 to 500 Hz,
0.75 g (0-peak), 5 minute resonant dwell
at 4 resonances per axis.
General Information
Supplemental Characteristics
1–6

Recommended Test Equipment
Equipment Required
Equipment Critical Specifications Recommended
Model/Part Use*
Pulse Generator 110 MHz, 3.5 ns pulse width,
< 600 psrise time HP 8131A Option 020 P,T
Digitizing Oscilloscope ≥6 GHz bandwidth, < 58 ps rise time HP 54750A mainframe
with HP 54751A plugin
module
P
Function Generator Accuracy ≤(5)(10−6) ×frequency,
DC offset voltage ±6.3 V HP 3325B Option 002 P
Digital Multimeter 0.1 mV resolution, 0.005% accuracy HP 3458A P
BNC-Banana Cable HP 11001-60001 P
BNC Tee BNC (m)(f)(f) HP 1250-0781 P
Cable BNC (m-m) 48 inch HP 10503A P
SMA Coax Cable (Qty 3) ≥18 GHzbandwidth HP 8120-4948 P
BNC Coax Cable BNC (m-m), >2 GHz bandwidth HP 8120-1840 P
Adapter (Qty 4) SMA(m)-BNC(f) HP 1250-1200 P
Adapter SMA(f)-BNC(m) HP 1250-2015 P
Coupler BNC (m-m) HP 1250-0216 P
20:1 Probes (Qty 2) HP 54006A P
BNC Test Connector, 17x2
(Qty 1)** P
BNC Test Connector, 6x2
(Qty 4)** P,T
*A = Adjustment P = Performance Tests T = Troubleshooting
**Instructions for making these test connectors are inchapter 3, "TestingPerformance."
General Information
Recommended Test Equipment
1–7

1–8

2
To inspect the module 2-2
To prepare the mainframe 2-3
To configure a one-card module 2-4
To configure a multicard module 2-5
To install the module 2-10
To turn on the system 2-11
To test the module 2-11
To install the ferrites 2-12
Preparing for Use

Preparing For Use
This chapter gives you instructions for preparing the logic analyzer module for use.
Power Requirements
All power supplies required for operating the logic analyzer are supplied through the
backplane connector in the mainframe.
Operating Environment
The operating environment is listed in chapter 1. Note the non-condensing humidity
limitation. Condensation within the instrument can cause poor operation or
malfunction. Provide protection against internal condensation.
The logic analyzer module will operate at all specifications within the temperature
and humidity range given in chapter 1. However, reliability is enhanced when
operating the module within the following ranges:
•Temperature: +20 °C to +35 °C (+68 °F to +95 °F)
•Humidity: 20% to 80% non-condensing
Storage
Store or ship the logic analyzer in environments within the following limits:
•Temperature: -40 °C to +75 °C
•Humidity: Up to 90% at 65 °C
•Altitude: Up to 15,300 meters (50,000 feet)
Protect the module from temperature extremes which cause condensation on the
instrument.
To inspect the module
1Inspect the shipping container for damage.
If the shipping container or cushioning material is damaged, keep them until you have
checked the contents of the shipment and checked the instrument mechanically and
electrically.
2Check the supplied accessories.
Accessories supplied with the module are listed in chapter 1, "Accessories Supplied."
3Inspect the product for physical damage.
Check the module and the supplied accessories for obvious physical or mechanical defects. If
you find any defects, contact your nearest Hewlett-Packard Sales Office. Arrangements for
repair or replacement are made, at Hewlett-Packard’s option, without waiting for a claim
settlement.
2–2

To prepare the mainframe
CAUTION Turn off the mainframe power before removing, replacing, or installing the module.
CAUTION Electrostatic discharge can damage electronic components. Use grounded wriststraps and
mats when performing any service to this module.
1Turn off the mainframe power switch, then unplug the power cord. Disconnect any
input or output connections.
2Plan your module configuration.
If you are installing a one-card module, use any available slot in the mainframe.
If you are installing a multicard module, use adjacent slots in the mainframe.
3Loosen the thumb screws.
Cards or filler panels below the slots intended for installation do not have to be removed.
Starting from the top, loosen the thumb screws on filler panels and cards that need to be
moved.
4Starting from the top, pull the cards and filler panels that need to be moved halfway
out.
CAUTION All multicard modules will be cabled together. Pull these cards out together.
5Remove the cards and filler panels.
Remove the cards or filler panels that are in the slots intended for the module installation.
Push all other cards into the card cage, but not completely in. This is to get them out of the
way for installing the module.
Some modules for the Logic Analysis System require calibration if you move them to a
different slot. For calibration information, refer to the manuals for the individual modules.
Preparing for Use
To prepare the mainframe
2–3

To configure a one-card module
•When shipped separately, the module is configured as a one-card module. The
cables should be connected as shown in the figure.
•To configure a multicard module into one-card modules, remove the cables
connecting the cards. Then connect the free end of the 2x10 cable to the
connector labeled "Master" (J6) on each card (see figure below).
CAUTION If you pull on the flexible ribbon part of the 2x10 cable, you might damage the cable
assembly. Using your thumb and finger, grasp the ends of the cable connector. Apply
pressure to the ends of the cable connector to disengage the metal locking tabs of the
connector from the cable socket on the board. Then pull the connector from the cable
socket.
Save unused cables forfutureconfigurations.
PreparingforUse
To configure a one-card module
2–4

To configure a multicard module
1Plan the configuration. Multicard modules can only be connected as shown in the
illustration. Select the card that will be the master card, and set the remaining cards
aside.
Do notcombine HP 16555A cardsand HP 16555D cards together in a multicard module. A
multicard module with both HP 16555A and HP 16555Dcards will not operate.
2Obtain two 2x25 cables from the accessory pouch that match the number of
expanders being configured. The illustration shows the cables that are available and
which cable is used in each expander configuration.
Preparing for Use
To configure a multicard module
2–5