Infineon Technologies XC800 User manual

User’s Manual, V 0.1, Jan 2005
Microcontrollers
Never stop thinking.
XC800
Microcontroller Family
Architecture and Instruction Set

Edition 2005-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
©Infineon Technologies AG 2005.
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User’s Manual, V 0.1, Jan 2005
Microcontrollers
Never stop thinking.
XC800
Microcontroller Family
Architecture and Instruction Set

XC800
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XC800
User’s Manual, V 0.1 I-1 2005-01
1 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Foreword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3.1 Memory Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3.1.1 Memory Extension Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3.1.2 Memory Extension Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.3 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.3.1 Internal Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.3.2 Internal Data Memory XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.3.3 External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.4.1 Special Function Register Extension by Mapping . . . . . . . . . . . . . . . . 7
1.3.4.2 Special Function Register Extension by Paging . . . . . . . . . . . . . . . . . 8
1.4 Bit Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 CPU Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.1 CPU Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.1 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.2 Data Pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.3 Accumulator (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.4 B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.5 Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.6 Extended Operation Register (EO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.7 Memory Extension Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.8 Power Control Register (PCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.9 UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.10 Timer/Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.11 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 On-Chip Debug Support Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3 Basic Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.1 Interrupt Source and Vector Address . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.2 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5 Service Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3CPUTiming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3.1 Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3.2 Accessing External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2.1 Accessing External Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2.2 Accessing External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
XC800
Table of Contents Page

XC800
User’s Manual, V 0.1 I-2 2005-01
4 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4.2 Introduction to the Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4.3 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.3.1 Affected Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.3.2 Instruction Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3.3 Instruction Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table of Contents Page

XC800
Fundamental Structure
User’s Manual, V 0.1 1-1 2005-01
1 Fundamental Structure
1.1 Foreword
This manual provides an overview of the architecture and functional characteristics of
the XC800 microcontroller family. It also includes a complete description of the XC800
core instruction set. For detailed information on the different derivatives of the XC800 8-
bit microcontrollers, refer to the respective user’s manuals.
1.2 Introduction
The Infineon XC800 microcontroller family has a CPU which is functionally upward
compatible to the 8051. While the standard 8051 core is designed around a 12-clock
machine cycle, the XC800 core uses a two-clock period machine cycle.
The instruction set consists of 45% one-byte, 41% two-byte, and 14% three-byte
instructions. Each instruction takes 1, 2 or 4 machine cycles to execute. In case of
access to slower memory, the access time may be extended by wait states.
The XC800 microcontrollers support via the dedicated JTAG interface or the standard
UART interface, a range of debugging features including basic stop/start, single-step
execution, breakpoint support and read/write access to the data memory, program
memory and special function registers.
The key features of the XC800 microcontrollers are listed below.
Features:
• Two clocks per machine cycle
•Program memory download option
• Up to 1 Mbyte of external data memory; up to 256 bytes of internal data memory
• Up to 1 Mbyte of program memory
• Wait state support for slow memory
• Support for synchronous or asynchronous program and data memory
• 15-source, 4-level interrupt controller
• Up to eight data pointers
• Power saving modes
• Dedicated debug mode via the standard JTAG interface or UART
• Two 16-bit timers (Timer 0 and Timer 1)
• Full-duplex serial port (UART)

XC800
Fundamental Structure
User’s Manual, V 0.1 1-2 V 1.0, 2005-01
1.3 Memory Organization
The memory partitioning of the XC800 microcontrollers is typical of the Harvard
architecture where data and program areas are held in separate memory space. The
on-chip peripheral units are accessed using an internal Special Function Register (SFR)
memory area that occupies 128 bytes of address, which can be mapped or paged to
increase the number of addressable SFRs.
A typical memory map of the code space consists of internal ROM/Flash, on-chip Boot
ROM, an on-chip XRAM and/or external memory. The memory map of the data space is
typical of the standard 8051 architecture: the internal data memory consists of 128 bytes
of directly addressable Internal RAM (IRAM), 128 bytes of indirect addressable IRAM
and an ‘external’ RAM (XRAM). External data memory may be supported outside of the
internal range. Figure 1-1 provides a general overview of the XC800 memory space and
a typical memory map in user mode.
Figure 1-1 XC800 Memory Space and Typical Memory Map in user mode
Extension Stack RAM
Memory Extension
Stack Pointer
(MEXSP)
Special Function
Registers
Indirect
Address Direct Address
80
H
FF
H
00
H
Code Space Internal Data Space
Internal RAM
7F
H
Internal RAM
0' 0000
H
XRAM
External Data Space
0' FFFF
H
0' F000
H
1' 0000
H
1' FFFF
H
2' 0000
H
2' FFFF
H
3' 0000
H
3' FFFF
H
4' 0000
H
4' FFFF
H
5' 0000
H
5' FFFF
H
6' 0000
H
6' FFFF
H
7' 0000
H
7' FFFF
H
8' 0000
H
8' FFFF
H
9' 0000
H
9' FFFF
H
A' 0000
H
A' FFFF
H
B' 0000
H
B' FFFF
H
C' 0000
H
C' FFFF
H
D' 0000
H
D' FFFF
H
E' 0000
H
E' FFFF
H
F' 0000
H
F' FFFF
H
Bank 1
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank A
Bank B
Bank C
Bank D
Bank E
Bank F
Bank 0
XRAM
Bank 2
0' C000
H
Bank 1
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank A
Bank B
Bank C
Bank D
Bank E
Bank F
Bank 2
Internal Memory
Notes:
!XC800 supportsmemoryextension ofup to 1 Mbyte
program memoryand 1 Mbyte external data memory.
This is accomplished by sixteen 64K bank blocks. At any
one time,only one bank of the respective memory is
active.
!In case ofimplemented memoryextension,an additional
extension stack RAM is added on-chip and located from
80
H
to FF
H
. This memory is notaccessible by software.
!The smallestmemory space withoutmemory extension
is such that only Bank 0 is available.
!In general,the data space where the corresponding
code space is occupied by internal memory is reserved.
!Ifsupported by available pins,external memory may be
located atregions notoccupied by internal memory.
Program Memory: In general,#EA = 1 selects dynamic
fetch from internal and external programmemory;#EA=
0 selects to alwaysfetch from external program memory
instead of Internal Memory.
Data Memory: External data is accessed by the MOVX
instruction.
!This memory mapping is general for user mode. Refer to
respective user’s manuals for exact mappings for
specific device.
Reserved
Boot ROM Reserved

XC800
Fundamental Structure
User’s Manual, V 0.1 1-3 2005-01
In derivatives with memory extension, an additional 128 bytes of memory extension
stack RAM is available from 80Hto FFH. Access to this memory is only possible by the
hardware, so the memory is effectively transparent to the user. By default after reset, the
memory extension stack pointer (MEXSP) points to 7FH. It is pre-incremented by call
instructions and post-decremented by return instructions.
1.3.1 Memory Extension
The standard amount of addressable program or external data memory in an 8051
system is 64 Kbytes. The XC800 core supports memory expansion of up to 1 Mbyte and
this is enabled by the availability of a Memory Management Unit (MMU) and a Memory
Extension Stack. The MMU adds a set of Memory Extension registers (MEX1, MEX2,
and MEX3) to control access to the extended memory space by different addressing
modes. The Memory Extension Stack is used by the hardware to ‘push’ and ‘pop’ values
of MEX1.
Program Code is always fetched from the 64-Kbyte block pointed to by the 4-bit Current
Bank (CB) register bit field. It is updated from a 4-bit Next Bank (NB) bit field upon
execution of long jump (LJMP) and call instructions. CB and NB together constitute the
MEX1register. The programmersimply writes the new bank number toNB before a jump
or call instruction.
Interrupt service routines are always executed from code in the 64-Kbyte block pointed
to by the Interrupt Bank (IB) register bit field. Further, memory constant data reads (in
code space) and external data accesses may take place in banks other than the current
bank. These banks are pointed to by the Memory Constant Bank pointer (MCB) and
XRAM Bank pointer (MX). These bit fields are located in MEX2 and MEX3 registers.
1.3.1.1 Memory Extension Stack
Interrupts and Calls in Memory Extension mode make use of a Memory Extension Stack,
which is updated at the same time as the standard stack.
The Memory Extension Stack is addressed using the SFR Memory Extension Stack
Pointer MEXSP. This read/write register provides for a stack depth of up to 128 bytes
(Bit 7 is always 0). The SFR is pre-incremented by each call instruction that is executed,
and post-decremented by return instructions. MEXSP is by default reset to 7FHso that
the first increment selects the bottom of the stack. No indication of stack overflow is
provided.
1.3.1.2 Memory Extension Effects
The following instructions can change the 64-Kbyte block pointed to: MOVC, MOVX,
LJMP, LCALL, ACALL, RET, and RETI.

XC800
Fundamental Structure
User’s Manual, V 0.1 1-4 V 1.0, 2005-01
Relative jumps (SJMP etc.) and absolute jumps within 2-Kbyte regions (AJMPs),
however, will in no way change the current bank. In other words, these instructions do
not deselect the active 64-Kbyte bank block.
Move Constant Instructions (MOVC)
MOVC instructions access data bytes in either the Current bank (CB19 – CB16) or a
‘Memory Constant’ bank, defined by the MCB19 – MCB16 bit field in MEX3 and MEX2.
The bank selection is done by the MCM bit in MEX2 (MEX2.7).
Move External Data Instructions (MOVX)
MOVX instructions can either access data in the Current bank or a ‘Data Memory’ bank,
defined by the MX19 – MX16 bits in MEX3. The bank selection is done by the MXM bit
in MEX3 (MEX3.3).
Long Jump Instructions (LJMP)
When a jump to another bank of the Memory Extension is required, the Next Bank bits
NB19 – NB16 in MEX1 (MEX1.3 – MEX1.0) must be set to the appropriate bank address
before the LJMP instruction is executed. When the LJMP is encountered in the code, the
Next Bank bits (NB19 – 16) are copied to the Current Bank bits CB19 – CB16 in MEX1
(MEX1.7 – MEX1.4) and appear on address bus at the beginning of the next program
fetch cycle.
Note: The Next Bank Bits (NB19 – 16) are not changed by the jump.
CALL Instructions (LCALL and ACALL)
Whenever an LCALL occurs, the MMU carries out the following sequence of actions:
1. The Memory Extension Stack Pointer is incremented.
2. The MEX1 register bits are made available on data bus.
3. The MEXSP register bits [6:0] are made available on address lines.
4. The Memory Extension Stack read and write signals are set for a write operation.
5. A write is performed to the Memory Extension Stack.
6. The Next Bank bits NB19 – NB16 (MEX1.3 – MEX1.0) are copied to the CB19 – CB16
bits (MEX1.7 – MEX.4).
Return Instructions (RET and RETI)
On leaving a subroutine, the MMU carries out the following sequence of actions:
1. The MEXSP register bits [6:0] are made available on address.
2. The Memory Extension Stack read and write signals are set for a read operation.
3. A read is performed on the Memory Extension Stack.
4. Memory Extension Stack data is written to the MEX1 register.
5. The Memory Extension Stack Pointer is decremented.

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Fundamental Structure
User’s Manual, V 0.1 1-5 2005-01
1.3.2 Program Memory
Up to 1 Mbyte of synchronous or asynchronous internal and/or external program
memory is supported. Program memory extension, if supported by the XC800 derivative,
is accomplished with a 4-bit Current Bank pointer (CB). The program code is fetched
from the 64-Kbyte block pointed to by CB. The minimum supported code space is
therefore 64 Kbytes.
If the internal program memory is used, the EA (External Access) pin must be held at
high level. With EA held high, the microcontroller executes instructions internally unless
the address (Program Counter) is outside the range of the internal program memory. In
this case, dynamic code fetch from internal and external program memory is supported
if the external memory bus is available on the derivative. If the EA pin is held at low level,
the microcontroller executes program code from external program memory, instead of
from internal memory. The general exception is for accesses to address ranges of the
active Boot ROM, internal XRAM and code-space data (e.g., Data Flash), where fetch is
always from the internal memory regardless of the status of EA pin.
Most XC800 derivatives include a section for Boot ROM code, the size of which depends
onthe derivative.Usually, the BootROM codeis executed firstafterreset where theBoot
ROM is mapped starting from base address 0000Hof the code space. The Boot ROM
code will switch the memory mapping so that before control is passed to the user code,
the standard memory map (of the derivative) is active where user code could run starting
from address 0000H.
For program memory implemented as RAM, the XC800 core supports write to program
memory with the instruction MOVC @(DPTR++),A. This is generally supported by the
XC800 derivatives for writes to internal memory only.
1.3.3 Data Memory
The data memory space consists of internal and external memory portions. The internal
data memory area is addressed using 8-bit addresses. The external data memory and
the internal XRAM data memory are addressable by 8-bit or 16-bit indirect address with
‘MOVX’, additionally with up to 4-bit for selection of extended memory bank (maximum
1Mbyte).
1.3.3.1 Internal Data Memory
The internal data memory is divided into two physically separate and distinct blocks: the
256-byte RAM and the 128-byte SFR area. While the upper 128 bytes of RAM and the
SFR area share the same address locations, they are accessed through different
addressing modes. The lower 128 bytes of RAM can be accessed through either direct
or register indirect addressing while the upper 128 bytes of RAM can be accessed
through register indirect addressing only. The special function registers are accessible
through direct addressing.

XC800
Fundamental Structure
User’s Manual, V 0.1 1-6 V 1.0, 2005-01
The 16 bytes of RAM that occupy addresses from 20Hto 2FHare bitaddressable. Bit 0
of the internal data byte at 20Hhas the bit address 00H, while bit 7 of the internal data
byte at 2FHhas the bit address 7FH.
By default after reset, the stack pointer points to address 07H. The stack may reside
anywhere in the internal RAM.
RAM occupying direct addresses from 30H to 7FHcan be used as scratch pad.
1.3.3.2 Internal Data Memory XRAM
The size of the internal XRAM is not fixed and varies depending on XC800 derivative.
The internal XRAM is mapped to both the external data space and the code space
because it can be accessed using both ‘MOVX’ and ‘MOVC’ instructions. When
accessed using the 8-bit MOVX instruction via register R0 or R1, the SFR XADDRH
must be initialized to specify the upper address byte.
The internal XRAM can be enabled or disabled. If disabled, external data memory can
be accessed in the address range of the internal XRAM, with activated external data
memory signals. If enabled, the external data memory signals are not generated when
the internal XRAM is accessed. Therefore, the corresponding ports can be used as
general purpose I/O in an application where there is no access to off-chip external data/
program memory.
1.3.3.3 External Data Memory
Up to 1 Mbyte of synchronous or asynchronous external data memory is supported.
External data memory extension, if supported by the XC800 derivative, is accomplished
with either the 4-bit Current Bank pointer (CB) or the 4-bit XRAM Bank pointer (MX),
selected by the MXM bit. The data is fetched from the 64-Kbyte block pointed to by CB
or MX. Some XC800 derivatives may not support external data memory.
1.3.4 Registers
All registers, except the program counter and the four general purpose register banks,
reside in the SFR area.
The lower 32 locations of the internal lower data RAM are assigned to four banks with
eight general purpose registers (GPRs) each. At any one time, only one of these banks
can be enabled by two bits in the program status word (PSW): RS0 (PSW.3) and RS1
(PSW.4). This allows fast context switching, which is useful when entering subroutines
or interrupt service routines. The eight general purpose registers of the selected register
bank may be accessed by register addressing. For indirect addressing modes, the
registers R0 and R1 are used as pointer or index register to address internal or external
memory.

XC800
Fundamental Structure
User’s Manual, V 0.1 1-7 2005-01
The Special Function Registers (SFRs) are mapped to the internal data space in the
range 80Hto FFH. The SFRs are accessible through direct addressing. The SFRs that
are located at addresses with address bit 0-2 equal to 0 (addresses 80H, 88H, 90H, ...,
F8H) are bitaddressable. Each bit of the bitaddressable SFRs has bit address
corresponding to the SFR byte address and its position within the SFR byte. For
example, bit 7 of SFR at byte address 80Hhas a bit address of 87H. The bit addresses
of the SFR bits span from 80Hto FFH.
As the 128-SFR range is less than the total number of registers required, register
extension mechanisms are implemented to increase the number of addressable SFRs.
These mechanisms include:
• Mapping
•Paging
1.3.4.1 Special Function Register Extension by Mapping
SFR extension is performed at the system level by mapping. The SFR area is extended
into two portions: the standard (non-mapped) SFR area and the mapped SFR area.
Each portion supports the same address range 80Hto FFH, bringing the number of
addressable SFRs to 256. To access SFRs in the mapped area, bit RMAP in SFR
SYSCON0 must be set by software. The mapped SFR area provides the same
addressing capabilities (direct addressing, bit addressing) as the standard SFR area. Bit
RMAP must be cleared by software to access the SFRs in the standard area. The
hardware does not automatically clear/set the bit.
SYSCON0
System Control Register 0 Reset Value: XXXX XXX0B
7 6 5 4 3 2 1 0
-RMAP
-rw
The functions of the shaded bits are not described here
Field Bits Type Description
RMAP 0rw Special Function Register Map Control
0 The access to the standard SFR area is
enabled.
1 The access to the mapped SFR area is
enabled.

XC800
Fundamental Structure
User’s Manual, V 0.1 1-8 V 1.0, 2005-01
1.3.4.2 Special Function Register Extension by Paging
The number of SFRs may be further extended for some on-chip peripherals at the
module level via a paging scheme. These peripherals have a built-in local SFR extension
mechanism for increasing the number of addressable SFRs. The control is via bit field
PAGE in the module page register MOD_PAGE. The bit field PAGE must be
programmed before accessing the SFR of the target module. Each module may contain
different number of pages and different number of SFRs per page, depending on the
requirement. Besides setting the correct RMAP bit value to select the standard or
mapped SFR area, the user must also ensure that a valid PAGE is selected to access
the desired SFR. The paging mechanism is illustrated in Figure 1-2.
Figure 1-2 SFR Extension by Paging
If an interrupt routine is initiated between the page register access and the module
register access, and the interrupt must access a register located in another page, the
current page setting can be saved, the new one programmed and finally, the old page
setting restored. This is possible with the storage fields STx (x = 0 - 3) for the save and
restore action of the current page setting, as illustrated in Figure 1-3. By indicating which
SFR0
SFR1
SFRx
…...
PAGE 0
SFR0
SFR1
SFRy
…...
PAGE 1
…...
SFR0
SFR1
SFRz
…...
PAGE q
MOD_PAGE.PAGE
SFR Address
(from CPU)
SFR Data
(to/from CPU)
rw
Module

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Fundamental Structure
User’s Manual, V 0.1 1-9 2005-01
storage register should be used in parallel with the new page value, a single write
operation can:
• Save the contents of PAGE in STx before overwriting with the new value
(this is done in the beginning of the interrupt routine to save the current page setting
and program the new page number); or
• Overwrite the contents of PAGE with the contents of STx, ignoring the value written to
the bit positions of PAGE
(this is done at the end of the interrupt routine to restore the previous page setting
before the interrupt occurred)
Figure 1-3 Storage Elements for Paging
With this mechanism, a certain number of interrupt routines (or other routines) can
perform page changes without reading and storing the previously usedpage information.
The use of only write operations makes the system simpler and faster. Consequently,
this mechanism significantly improves the performance of short interrupt routines.
The page register has the following definition:
MOD_PAGE
Page Register for module MOD Reset Value: 00H
7 6 5 4 3 2 1 0
OP STNR 0PAGE
w w r rw
PAGE
ST0
ST1
ST2
ST3
value update
from CPU
STNR

XC800
Fundamental Structure
User’s Manual, V 0.1 1-10 V 1.0, 2005-01
Field Bits Type Description
PAGE [2:0] rw Page Bits
When written, the value indicates the new page.
When read, the value indicates the currently active
page.
STNR [5:4] wStorage Number
This number indicates which storage bit field is the
target of the operation defined by bit field OP.
If OP = 10B,
the contents of PAGE are saved in STx before being
overwritten with the new value.
If OP = 11B,
the contents of PAGE are overwritten by the
contentsof STx.Thevalue written tothe bitpositions
of PAGE is ignored.
00 ST0 is selected.
01 ST1 is selected.
10 ST2 is selected.
11 ST3 is selected.
OP [7:6] wOperation
0X Manual page mode. The value of STNR is
ignored and PAGE is directly written.
10 New page programming with automatic page
saving. The value written to the bit field PAGE
is stored. In parallel, the previous contents of
PAGE are saved in the storage bit field STx
indicated by STNR.
11 Automatic restore page action. The value
written to the bit field PAGE is ignored and
instead, PAGE is overwritten by the contents
of the storage bit field STx indicated by STNR.
03 r Reserved
Returns 0 if read; should be written with 0.

XC800
Fundamental Structure
User’s Manual, V 0.1 1-11 2005-01
1.4 Bit Protection Scheme
The bit protection scheme prevents direct software writing of selected bits (i.e., protected
bits) by the PASSWD register. When the bit field MODE is 11B, writing 10011Bto the bit
field PASS opens access to writing of all protected bits and writing 10101Bto the bit field
PASS closes access to writing of all protected bits. Note that access is opened for
maximum 32 CCLKs if the “close access” password is not written. If “open access”
password is written again before the end of 32 CCLK cycles, there will be a recount of
32 CCLK cycles.
The bits or bit fields that are protected may differ for the XC800 derivatives.
PASSWD
Password Register Reset Value: 07H
7 6 5 4 3 2 1 0
PASS PROTECT
_S MODE
wh rh rw
Field Bits Type Description
MODE [1:0] rw Bit-Protection Scheme Control bit
00 Scheme Disabled
11 Scheme Enabled (default)
Others: Scheme Enabled
These two bits cannot be written directly. To change
the value between 11Band 00B, the bit field PASS
must be written with 11000B, only then will the
MODE[1:0] be registered.
PROTECT_S 2rh Bit-Protection Signal Status bit
This bit shows the status of the protection.
0 Software is able to write to all protected bits.
1 Software is unable to write to any protected
bits.
PASS [7:3] wh Password bits
The Bit-Protection Scheme recognizes only three
patterns.
11000BEnables writing of the bit field MODE.
10011BOpens access to writing of all protected bits.
10101BClosesaccesstowritingofallprotectedbits.

XC800
CPU Architecture
User’s Manual, V 0.1 2-1 2005-01
2 CPU Architecture
Figure 2-1 depicts the typical architecture of an XC800 family microcontroller. It
includes the main functional blocks and standard units. The units represented by dotted
boxes may not be available, depending on the derivative; these include peripheral units
and external memory bus. Memory sizes vary depending on the XC800 microcontroller
derivative.
Figure 2-1 Typical Architecture of XC800 Family Microcontroller
The CPU functional blocks are shown in Figure 2-2. The CPU consists mainly of the
instruction decoder, the arithmetic section, the program control section, the access
control section, and the interrupt controller. The CPU also provides modes for power
saving.
The instruction decoder decodes each instruction and accordingly generates the internal
signals required to control the functions of the individual units within the CPU. These
internal signals have an effect on the source and destination of signal transfers and
control the ALU processing.
ADC
Ports
CCU6
Timer 2
SSC
Watchdog
Timer
Boot ROM
Internal Data
RAM
XRAM
Flash
or
ROM
XC800 Core
T0 & T1 UART
System Control
Unit
V
AREF
V
AGND
OSC
& PLL
XTAL1
XTAL2
Internal Bus
V
DDP
V
SSP
V
DDC
V
SSC
RESET
External
Data
Memory
External
Code
Memory
CAN
MDU
1) OCDS: On-Chip Debug
Support
Standard JTAG I/O
Cordic
OCDS
1)

XC800
CPU Architecture
User’s Manual, V 0.1 2-2 2005-01
Figure 2-2 XC800 Core Block Diagram
The arithmetic section of the processor performs extensive data manipulation and
consists of the arithmetic/logic unit (ALU), A register, B register, and PSW register. The
ALU accepts 8-bit data words from one or two sources, and generates an 8-bit result
under the control of the instruction decoder. The ALU performs both arithmetic and logic
operations. Arithmetic operations include add, subtract, multiply, divide, increment,
decrement, BCD-decimal-add-adjust, and compare. Logic operations include AND, OR,
Exclusive OR, complement, and rotate (right, left, or swap nibble (left four)). Also
included is a Boolean unit performing the bit operations such as set, clear, complement,
jump-if-set, jump-if-not-set, jump-if-set-and-clear, and move to/from carry. The ALU can
perform the bit operations of logical AND or logical OR between any addressable bit (or
its complement) and the carry flag, and place the new result in the carry flag.
The program control section controls the sequence in which the instructions stored in
program memory are executed. The 16-bit program counter (PC) holds the address of
Register Interface
ALU
UART
Core SFRs
16-bit Registers &
Memory Interface
Opcode Decoder
State Machine &
Power Saving
Interrupt
Controller
Multiplier / Divider
Opcode &
Immediate
Registers
Timers / Counters
Internal Data
Memory
External SFRs
External Data
Memory
Program Memory
f
CCLK
Memory Wait
Reset
Legacy External Interrupts (IEN0, IEN1)
External Interrupts
Non-Maskable Interrupt

XC800
CPU Architecture
User’s Manual, V 0.1 2-3 2005-01
the next instruction to be executed. The conditional branch logic enables internal and
external events to the processor to cause a change in the program execution sequence.
The access control unit is responsible for the selection of the on-chip memory resources.
The interrupt requests from the peripheral units are handled by the interrupt controller
unit.