Intel 80C186EA User manual

80C186EA/80C188EA
Microprocessor
User’s Manual

80C186EA/80C188EA
Microprocessor
User’s Manual
1995

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© INTEL CORPORATION, 1995

iii
CONTENTS
CHAPTER 1
INTRODUCTION
1.1 HOW TO USE THIS MANUAL....................................................................................... 1-2
1.2 RELATED DOCUMENTS.............................................................................................. 1-3
1.3 ELECTRONIC SUPPORT SYSTEMS........................................................................... 1-4
1.3.1 FaxBack Service ...................................................................................................... 1-4
1.3.2 Bulletin Board System (BBS) ................................................................................... 1-5
1.3.2.1 How to Find
Ap BUILDER Software and Hypertext Documents
on the BBS ..................................................................................................... 1-5
1.3.3 CompuServe Forums ............................................................................................... 1-6
1.3.4 World Wide Web ...................................................................................................... 1-6
1.4 TECHNICAL SUPPORT................................................................................................ 1-6
1.5 PRODUCT LITERATURE.............................................................................................. 1-6
CHAPTER 2
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.1 ARCHITECTURAL OVERVIEW .................................................................................... 2-1
2.1.1 Execution Unit ...........................................................................................................2-2
2.1.2 Bus Interface Unit .....................................................................................................2-3
2.1.3 General Registers .....................................................................................................2-4
2.1.4 Segment Registers ...................................................................................................2-5
2.1.5 Instruction Pointer .....................................................................................................2-6
2.1.6 Flags .........................................................................................................................2-7
2.1.7 Memory Segmentation ..............................................................................................2-8
2.1.8 Logical Addresses ...................................................................................................2-10
2.1.9 Dynamically Relocatable Code ...............................................................................2-13
2.1.10 Stack Implementation .............................................................................................2-15
2.1.11 Reserved Memory and I/O Space ...........................................................................2-15
2.2 SOFTWARE OVERVIEW............................................................................................ 2-17
2.2.1 Instruction Set .........................................................................................................2-17
2.2.1.1 Data Transfer Instructions .............................................................................2-18
2.2.1.2 Arithmetic Instructions ...................................................................................2-19
2.2.1.3 Bit Manipulation Instructions .........................................................................2-21
2.2.1.4 String Instructions ..........................................................................................2-22
2.2.1.5 Program Transfer Instructions .......................................................................2-23
2.2.1.6 Processor Control Instructions ......................................................................2-27
2.2.2 Addressing Modes ..................................................................................................2-27
2.2.2.1 Register and Immediate Operand Addressing Modes ...................................2-27
2.2.2.2 Memory Addressing Modes ...........................................................................2-28
2.2.2.3 I/O Port Addressing .......................................................................................2-36
2.2.2.4 Data Types Used in the 80C186 Modular Core Family .................................2-37

CONTENTS
iv
2.3 INTERRUPTS AND EXCEPTION HANDLING............................................................ 2-39
2.3.1 Interrupt/Exception Processing ...............................................................................2-39
2.3.1.1 Non-Maskable Interrupts ...............................................................................2-42
2.3.1.2 Maskable Interrupts .......................................................................................2-43
2.3.1.3 Exceptions .....................................................................................................2-43
2.3.2 Software Interrupts ..................................................................................................2-45
2.3.3 Interrupt Latency .....................................................................................................2-45
2.3.4 Interrupt Response Time ........................................................................................2-46
2.3.5 Interrupt and Exception Priority ...............................................................................2-46
CHAPTER 3
BUS INTERFACE UNIT
3.1 MULTIPLEXED ADDRESS AND DATA BUS................................................................ 3-1
3.2 ADDRESS AND DATA BUS CONCEPTS..................................................................... 3-1
3.2.1 16-Bit Data Bus .........................................................................................................3-1
3.2.2 8-Bit Data Bus ...........................................................................................................3-5
3.3 MEMORY AND I/O INTERFACES................................................................................. 3-6
3.3.1 16-Bit Bus Memory and I/O Requirements ...............................................................3-7
3.3.2 8-Bit Bus Memory and I/O Requirements .................................................................3-7
3.4 BUS CYCLE OPERATION............................................................................................ 3-7
3.4.1 Address/Status Phase ............................................................................................3-10
3.4.2 Data Phase .............................................................................................................3-13
3.4.3 Wait States ..............................................................................................................3-13
3.4.4 Idle States ...............................................................................................................3-18
3.5 BUS CYCLES.............................................................................................................. 3-20
3.5.1 Read Bus Cycles ....................................................................................................3-20
3.5.1.1 Refresh Bus Cycles .......................................................................................3-22
3.5.2 Write Bus Cycles .....................................................................................................3-22
3.5.3 Interrupt Acknowledge Bus Cycle ...........................................................................3-25
3.5.3.1 System Design Considerations .....................................................................3-27
3.5.4 HALT Bus Cycle ......................................................................................................3-28
3.5.5 Temporarily Exiting the HALT Bus State .................................................................3-31
3.5.6 Exiting HALT ...........................................................................................................3-33
3.6 SYSTEM DESIGN ALTERNATIVES ........................................................................... 3-35
3.6.1 Buffering the Data Bus ............................................................................................3-36
3.6.2 Synchronizing Software and Hardware Events .......................................................3-38
3.6.3 Using a Locked Bus ................................................................................................3-39
3.6.4 Using the Queue Status Signals .............................................................................3-40
3.7 MULTI-MASTER BUS SYSTEM DESIGNS................................................................. 3-41
3.7.1 Entering Bus HOLD ................................................................................................3-41
3.7.1.1 HOLD Bus Latency ........................................................................................3-42
3.7.1.2 Refresh Operation During a Bus HOLD ........................................................3-43
3.7.2 Exiting HOLD ..........................................................................................................3-45
3.8 BUS CYCLE PRIORITIES........................................................................................... 3-46

v
CONTENTS
CHAPTER 4
PERIPHERAL CONTROL BLOCK
4.1 PERIPHERAL CONTROL REGISTERS........................................................................ 4-1
4.2 PCB RELOCATION REGISTER.................................................................................... 4-1
4.3 RESERVED LOCATIONS ............................................................................................. 4-4
4.4 ACCESSING THE PERIPHERAL CONTROL BLOCK.................................................. 4-4
4.4.1 Bus Cycles ...............................................................................................................4-4
4.4.2 READY Signals and Wait States .............................................................................4-4
4.4.3 F-Bus Operation .......................................................................................................4-5
4.4.3.1 Writing the PCB Relocation Register ...............................................................4-6
4.4.3.2 Accessing the Peripheral Control Registers ....................................................4-6
4.4.3.3 Accessing Reserved Locations .......................................................................4-6
4.5 SETTING THE PCB BASE LOCATION......................................................................... 4-6
4.5.1 Considerations for the 80C187 Math Coprocessor Interface ....................................4-7
CHAPTER 5
CLOCK GENERATION AND POWER MANAGEMENT
5.1 CLOCK GENERATION.................................................................................................. 5-1
5.1.1 Crystal Oscillator .......................................................................................................5-1
5.1.1.1 Oscillator Operation .........................................................................................5-2
5.1.1.2 Selecting Crystals ............................................................................................5-5
5.1.2 Using an External Oscillator ......................................................................................5-6
5.1.3 Output from the Clock Generator ..............................................................................5-6
5.1.4 Reset and Clock Synchronization .............................................................................5-6
5.2 POWER MANAGEMENT............................................................................................. 5-10
5.2.1 Idle Mode ................................................................................................................5-11
5.2.1.1 Entering Idle Mode ........................................................................................5-11
5.2.1.2 Bus Operation During Idle Mode ...................................................................5-13
5.2.1.3 Leaving Idle Mode .........................................................................................5-14
5.2.1.4 Example Idle Mode Initialization Code ..........................................................5-15
5.2.2 Powerdown Mode ...................................................................................................5-16
5.2.2.1 Entering Powerdown Mode ...........................................................................5-17
5.2.2.2 Leaving Powerdown Mode ............................................................................5-18
5.2.3 Power-Save Mode ..................................................................................................5-19
5.2.3.1 Entering Power-Save Mode ..........................................................................5-19
5.2.3.2 Leaving Power-Save Mode ...........................................................................5-21
5.2.3.3 Example Power-Save Initialization Code .......................................................5-21
5.2.4 Implementing a Power Management Scheme ........................................................5-23

CONTENTS
vi
CHAPTER 6
CHIP-SELECT UNIT
6.1 COMMON METHODS FOR GENERATING CHIP-SELECTS....................................... 6-1
6.2 CHIP-SELECT UNIT FEATURES AND BENEFITS ...................................................... 6-1
6.3 CHIP-SELECT UNIT FUNCTIONAL OVERVIEW ......................................................... 6-2
6.4 PROGRAMMING........................................................................................................... 6-6
6.4.1 Initialization Sequence ..............................................................................................6-6
6.4.2 Programming the Active Ranges ............................................................................6-12
6.4.2.1 UCS Active Range ........................................................................................6-12
6.4.2.2 LCS Active Range .........................................................................................6-13
6.4.2.3 MCS Active Range ........................................................................................6-13
6.4.2.4 PCS Active Range .........................................................................................6-15
6.4.3 Bus Wait State and Ready Control .........................................................................6-15
6.4.4 Overlapping Chip-Selects .......................................................................................6-16
6.4.5 Memory or I/O Bus Cycle Decoding ........................................................................6-17
6.4.6 Programming Considerations ..................................................................................6-17
6.5 CHIP-SELECTS AND BUS HOLD............................................................................... 6-18
6.6 EXAMPLES ................................................................................................................. 6-18
6.6.1 Example 1: Typical System Configuration ..............................................................6-18
CHAPTER 7
REFRESH CONTROL UNIT
7.1 THE ROLE OF THE REFRESH CONTROL UNIT......................................................... 7-2
7.2 REFRESH CONTROL UNIT CAPABILITIES................................................................. 7-2
7.3 REFRESH CONTROL UNIT OPERATION.................................................................... 7-2
7.4 REFRESH ADDRESSES............................................................................................... 7-4
7.5 REFRESH BUS CYCLES.............................................................................................. 7-5
7.6 GUIDELINES FOR DESIGNING DRAM CONTROLLERS............................................ 7-5
7.7 PROGRAMMING THE REFRESH CONTROL UNIT..................................................... 7-7
7.7.1 Calculating the Refresh Interval ................................................................................7-7
7.7.2 Refresh Control Unit Registers .................................................................................7-7
7.7.2.1 Refresh Base Address Register ......................................................................7-8
7.7.2.2 Refresh Clock Interval Register .......................................................................7-8
7.7.2.3 Refresh Control Register .................................................................................7-9
7.7.3 Programming Example ...........................................................................................7-10
7.8 REFRESH OPERATION AND BUS HOLD.................................................................. 7-12

vii
CONTENTS
CHAPTER 8
INTERRUPT CONTROL UNIT
8.1 FUNCTIONAL OVERVIEW............................................................................................ 8-1
8.2 MASTER MODE............................................................................................................ 8-2
8.2.1 Generic Functions in Master Mode ...........................................................................8-2
8.2.1.1 Interrupt Masking .............................................................................................8-3
8.2.1.2 Interrupt Priority ...............................................................................................8-3
8.2.1.3 Interrupt Nesting ..............................................................................................8-4
8.3 FUNCTIONAL OPERATION IN MASTER MODE ......................................................... 8-5
8.3.1 Typical Interrupt Sequence .......................................................................................8-5
8.3.2 Priority Resolution .....................................................................................................8-5
8.3.2.1 Priority Resolution Example ............................................................................8-6
8.3.2.2 Interrupts That Share a Single Source ............................................................8-7
8.3.3 Cascading with External 8259As ..............................................................................8-7
8.3.3.1 Special Fully Nested Mode ..............................................................................8-8
8.3.4 Interrupt Acknowledge Sequence .............................................................................8-9
8.3.5 Polling .......................................................................................................................8-9
8.3.6 Edge and Level Triggering ......................................................................................8-10
8.3.7 Additional Latency and Response Time .................................................................8-10
8.4 PROGRAMMING THE INTERRUPT CONTROL UNIT............................................... 8-11
8.4.1 Interrupt Control Registers ......................................................................................8-12
8.4.2 Interrupt Request Register ......................................................................................8-16
8.4.3 Interrupt Mask Register ...........................................................................................8-16
8.4.4 Priority Mask Register .............................................................................................8-17
8.4.5 In-Service Register .................................................................................................8-18
8.4.6 Poll and Poll Status Registers .................................................................................8-19
8.4.7 End-of-Interrupt (EOI) Register ...............................................................................8-21
8.4.8 Interrupt Status Register .........................................................................................8-22
8.5 SLAVE MODE ............................................................................................................. 8-23
8.5.1 Slave Mode Programming ......................................................................................8-25
8.5.1.1 Interrupt Vector Register ...............................................................................8-26
8.5.1.2 End-Of-Interrupt Register ..............................................................................8-27
8.5.1.3 Other Registers .............................................................................................8-28
8.5.2 Interrupt Vectoring in Slave Mode ...........................................................................8-29
8.5.3 Initializing the Interrupt Control Unit for Master Mode .............................................8-30
CHAPTER 9
TIMER/COUNTER UNIT
9.1 FUNCTIONAL OVERVIEW............................................................................................ 9-1
9.2 PROGRAMMING THE TIMER/COUNTER UNIT .......................................................... 9-6
9.2.1 Initialization Sequence ............................................................................................9-11
9.2.2 Clock Sources .........................................................................................................9-12
9.2.3 Counting Modes ......................................................................................................9-12
9.2.3.1 Retriggering ...................................................................................................9-13

CONTENTS
viii
9.2.4 Pulsed and Variable Duty Cycle Output ..................................................................9-14
9.2.5 Enabling/Disabling Counters ...................................................................................9-15
9.2.6 Timer Interrupts .......................................................................................................9-16
9.2.7 Programming Considerations ..................................................................................9-16
9.3 TIMING........................................................................................................................ 9-16
9.3.1 Input Setup and Hold Timings .................................................................................9-16
9.3.2 Synchronization and Maximum Frequency .............................................................9-17
9.3.2.1 Timer/Counter Unit Application Examples .....................................................9-17
9.3.3 Real-Time Clock .....................................................................................................9-17
9.3.4 Square-Wave Generator .........................................................................................9-17
9.3.5 Digital One-Shot ......................................................................................................9-17
CHAPTER 10
DIRECT MEMORY ACCESS UNIT
10.1 FUNCTIONAL OVERVIEW.......................................................................................... 10-1
10.1.1 The DMA Transfer ..................................................................................................10-1
10.1.1.1 DMA Transfer Directions ...............................................................................10-3
10.1.1.2 Byte and Word Transfers ..............................................................................10-3
10.1.2 Source and Destination Pointers ............................................................................10-3
10.1.3 DMA Requests ........................................................................................................10-3
10.1.4 External Requests ...................................................................................................10-4
10.1.4.1 Source Synchronization ................................................................................10-5
10.1.4.2 Destination Synchronization ..........................................................................10-5
10.1.5 Internal Requests ....................................................................................................10-6
10.1.5.1 Timer 2-Initiated Transfers.............................................................................10-6
10.1.5.2 Unsynchronized Transfers ............................................................................10-6
10.1.6 DMA Transfer Counts .............................................................................................10-7
10.1.7 Termination and Suspension of DMA Transfers .....................................................10-7
10.1.7.1 Termination at Terminal Count ......................................................................10-7
10.1.7.2 Software Termination ....................................................................................10-7
10.1.7.3 Suspension of DMA During NMI ...................................................................10-7
10.1.7.4 Software Suspension ....................................................................................10-7
10.1.8 DMA Unit Interrupts ................................................................................................10-8
10.1.9 DMA Cycles and the BIU ........................................................................................10-8
10.1.10 The Two-Channel DMA Unit ...................................................................................10-8
10.1.10.1 DMA Channel Arbitration ...............................................................................10-8
10.2 PROGRAMMING THE DMA UNIT ............................................................................ 10-10
10.2.1 DMA Channel Parameters ....................................................................................10-10
10.2.1.1 Programming the Source and Destination Pointers ....................................10-10
10.2.1.2 Selecting Byte or Word Size Transfers ........................................................10-14
10.2.1.3 Selecting the Source of DMA Requests ......................................................10-17
10.2.1.4 Arming the DMA Channel ............................................................................10-18
10.2.1.5 Selecting Channel Synchronization .............................................................10-18
10.2.1.6 Programming the Transfer Count Options ...................................................10-18
10.2.1.7 Generating Interrupts on Terminal Count ....................................................10-19

ix
CONTENTS
10.2.1.8 Setting the Relative Priority of a Channel ....................................................10-19
10.2.2 Suspension of DMA Transfers ..............................................................................10-20
10.2.3 Initializing the DMA Unit ........................................................................................10-20
10.3 HARDWARE CONSIDERATIONS AND THE DMA UNIT ......................................... 10-20
10.3.1 DRQ Pin Timing Requirements .............................................................................10-20
10.3.2 DMA Latency ........................................................................................................10-21
10.3.3 DMA Transfer Rates .............................................................................................10-21
10.3.4 Generating a DMA Acknowledge ..........................................................................10-22
10.4 DMA UNIT EXAMPLES............................................................................................. 10-22
CHAPTER 11
MATH COPROCESSING
11.1 OVERVIEW OF MATH COPROCESSING.................................................................. 11-1
11.2 AVAILABILITY OF MATH COPROCESSING.............................................................. 11-1
11.3 THE 80C187 MATH COPROCESSOR........................................................................ 11-2
11.3.1 80C187 Instruction Set ...........................................................................................11-2
11.3.1.1 Data Transfer Instructions .............................................................................11-3
11.3.1.2 Arithmetic Instructions ...................................................................................11-3
11.3.1.3 Comparison Instructions ................................................................................11-5
11.3.1.4 Transcendental Instructions ..........................................................................11-5
11.3.1.5 Constant Instructions .....................................................................................11-6
11.3.1.6 Processor Control Instructions ......................................................................11-6
11.3.2 80C187 Data Types ................................................................................................11-7
11.4 MICROPROCESSOR AND COPROCESSOR OPERATION...................................... 11-7
11.4.1 Clocking the 80C187 .............................................................................................11-10
11.4.2 Processor Bus Cycles Accessing the 80C187 ......................................................11-10
11.4.3 System Design Tips ..............................................................................................11-11
11.4.4 Exception Trapping ...............................................................................................11-13
11.5 EXAMPLE MATH COPROCESSOR ROUTINES...................................................... 11-13
CHAPTER 12
ONCE MODE
12.1 ENTERING/LEAVING ONCE MODE........................................................................... 12-1
APPENDIX A
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS
A.1 80C186 INSTRUCTION SET ADDITIONS................................................................... A-1
A.1.1 Data Transfer Instructions ......................................................................................A-1
A.1.2 String Instructions ...................................................................................................A-2
A.1.3 High-Level Instructions ...........................................................................................A-2
A.2 80C186 INSTRUCTION SET ENHANCEMENTS......................................................... A-8
A.2.1 Data Transfer Instructions ......................................................................................A-8
A.2.2 Arithmetic Instructions ............................................................................................A-9

CONTENTS
x
A.2.3 Bit Manipulation Instructions ...................................................................................A-9
A.2.3.1 Shift Instructions .............................................................................................A-9
A.2.3.2 Rotate Instructions .......................................................................................A-10
APPENDIX B
INPUT SYNCHRONIZATION
B.1 WHY SYNCHRONIZERS ARE REQUIRED................................................................. B-1
B.2 ASYNCHRONOUS PINS.............................................................................................. B-2
APPENDIX C
INSTRUCTION SET DESCRIPTIONS
APPENDIX D
INSTRUCTION SET OPCODES AND CLOCK CYCLES
INDEX

xi
CONTENTS
FIGURES
Figure Page
2-1 Simplified Functional Block Diagram of the 80C186 Family CPU................................2-2
2-2 Physical Address Generation.......................................................................................2-3
2-3 General Registers ........................................................................................................2-4
2-4 Segment Registers.......................................................................................................2-6
2-5 Processor Status Word ................................................................................................2-9
2-6 Segment Locations in Physical Memory.....................................................................2-10
2-7 Currently Addressable Segments...............................................................................2-11
2-8 Logical and Physical Address ....................................................................................2-12
2-9 Dynamic Code Relocation..........................................................................................2-14
2-10 Stack Operation..........................................................................................................2-16
2-11 Flag Storage Format ..................................................................................................2-19
2-12 Memory Address Computation...................................................................................2-29
2-13 Direct Addressing.......................................................................................................2-30
2-14 Register Indirect Addressing......................................................................................2-31
2-15 Based Addressing......................................................................................................2-31
2-16 Accessing a Structure with Based Addressing...........................................................2-32
2-17 Indexed Addressing....................................................................................................2-33
2-18 Accessing an Array with Indexed Addressing............................................................2-33
2-19 Based Index Addressing ............................................................................................2-34
2-20 Accessing a Stacked Array with Based Index Addressing.........................................2-35
2-21 String Operand...........................................................................................................2-36
2-22 I/O Port Addressing....................................................................................................2-36
2-23 80C186 Modular Core Family Supported Data Types................................................2-38
2-24 Interrupt Control Unit..................................................................................................2-39
2-25 Interrupt Vector Table.................................................................................................2-40
2-26 Interrupt Sequence.....................................................................................................2-42
2-27 Interrupt Response Factors........................................................................................2-46
2-28 Simultaneous NMI and Exception ..............................................................................2-47
2-29 Simultaneous NMI and Single Step Interrupts............................................................2-48
2-30 Simultaneous NMI, Single Step and Maskable Interrupt............................................2-49
3-1 Physical Data Bus Models............................................................................................3-2
3-2 16-Bit Data Bus Byte Transfers....................................................................................3-3
3-3 16-Bit Data Bus Even Word Transfers.........................................................................3-4
3-4 16-Bit Data Bus Odd Word Transfers...........................................................................3-5
3-5 8-Bit Data Bus Word Transfers.....................................................................................3-6
3-6 Typical Bus Cycle.........................................................................................................3-8
3-7 T-State Relation to CLKOUT........................................................................................3-8
3-8 BIU State Diagram .......................................................................................................3-9
3-9 T-State and Bus Phases ............................................................................................3-10
3-10 Address/Status Phase Signal Relationships..............................................................3-11
3-11 Demultiplexing Address Information...........................................................................3-12
3-12 Data Phase Signal Relationships...............................................................................3-14
3-13 Typical Bus Cycle with Wait States............................................................................3-15
3-14 ARDY and SRDY Pin Block Diagram.........................................................................3-15

CONTENTS
xii
FIGURES
Figure Page
3-15 Generating a Normally Not-Ready Bus Signal...........................................................3-16
3-16 Generating a Normally Ready Bus Signal..................................................................3-17
3-17 Normally Not-Ready System Timing ..........................................................................3-18
3-18 Normally Ready System Timings ...............................................................................3-19
3-19 Typical Read Bus Cycle .............................................................................................3-21
3-20 Read-Only Device Interface .......................................................................................3-22
3-21 Typical Write Bus Cycle..............................................................................................3-23
3-22 16-Bit Bus Read/Write Device Interface.....................................................................3-24
3-23 Interrupt Acknowledge Bus Cycle...............................................................................3-26
3-24 Typical 82C59A Interface...........................................................................................3-27
3-25 HALT Bus Cycle.........................................................................................................3-30
3-26 Returning to HALT After a HOLD/HLDA Bus Exchange............................................3-31
3-27 Returning to HALT After a Refresh Bus Cycle...........................................................3-32
3-28 Returning to HALT After a DMA Bus Cycle................................................................3-33
3-29 Exiting HALT (Powerdown Mode) ..............................................................................3-34
3-30 Exiting HALT (Active/Idle Mode).................................................................................3-35
3-31 DEN and DT/R Timing Relationships.........................................................................3-36
3-32 Buffered AD Bus System............................................................................................3-37
3-33 Qualifying DEN with Chip-Selects..............................................................................3-38
3-34 Queue Status Timing..................................................................................................3-41
3-35 Timing Sequence Entering HOLD..............................................................................3-42
3-36 Refresh Request During HOLD..................................................................................3-44
3-37 Latching HLDA ...........................................................................................................3-45
3-38 Exiting HOLD..............................................................................................................3-46
4-1 PCB Relocation Register..............................................................................................4-2
5-1 Clock Generator...........................................................................................................5-1
5-2 Ideal Operation of Pierce Oscillator..............................................................................5-2
5-3 Crystal Connections to Microprocessor........................................................................5-3
5-4 Equations for Crystal Calculations................................................................................5-4
5-5 Simple RC Circuit for Powerup Reset ..........................................................................5-7
5-6 Cold Reset Waveform ..................................................................................................5-8
5-7 Warm Reset Waveform................................................................................................5-9
5-8 Clock Synchronization at Reset..................................................................................5-10
5-9 Power Control Register ..............................................................................................5-12
5-10 Entering Idle Mode.....................................................................................................5-13
5-11 HOLD/HLDA During Idle Mode...................................................................................5-14
5-12 Entering Powerdown Mode ........................................................................................5-17
5-13 Powerdown Timer Circuit ...........................................................................................5-18
5-14 Power-Save Register .................................................................................................5-20
5-15 Power-Save Clock Transition.....................................................................................5-21
6-1 Common Chip-Select Generation Methods..................................................................6-2
6-2 Chip-Select Block Diagram...........................................................................................6-3
6-3 Chip-Select Relative Timings.......................................................................................6-4
6-4 UCS Reset Configuration.............................................................................................6-5

xiii
CONTENTS
FIGURES
Figure Page
6-5 UMCS Register Definition.............................................................................................6-7
6-6 LMCS Register Definition.............................................................................................6-8
6-7 MMCS Register Definition............................................................................................6-9
6-8 PACS Register Definition...........................................................................................6-10
6-9 MPCS Register Definition...........................................................................................6-11
6-10 MCS3:0 Active Ranges ..............................................................................................6-14
6-11 Wait State and Ready Control Functions...................................................................6-16
6-12 Using Chip-Selects During HOLD ..............................................................................6-18
6-13 Typical System...........................................................................................................6-19
7-1 Refresh Control Unit Block Diagram.............................................................................7-1
7-2 Refresh Control Unit Operation Flow Chart..................................................................7-3
7-3 Refresh Address Formation..........................................................................................7-4
7-4 Suggested DRAM Control Signal Timing Relationships...............................................7-6
7-5 Formula for Calculating Refresh Interval for RFTIME Register....................................7-7
7-6 Refresh Base Address Register...................................................................................7-8
7-7 Refresh Clock Interval Register....................................................................................7-9
7-8 Refresh Control Register............................................................................................7-10
7-9 Regaining Bus Control to Run a DRAM Refresh Bus Cycle......................................7-13
8-1 Interrupt Control Unit in Master Mode ..........................................................................8-2
8-2 Using External 8259A Modules in Cascade Mode.......................................................8-8
8-3 Interrupt Control Unit Latency and Response Time ...................................................8-11
8-4 Interrupt Control Register for Internal Sources...........................................................8-13
8-5 Interrupt Control Register for Noncascadable External Pins......................................8-14
8-6 Interrupt Control Register for Cascadable Interrupt Pins............................................8-15
8-7 Interrupt Request Register .........................................................................................8-16
8-8 Interrupt Mask Register..............................................................................................8-17
8-9 Priority Mask Register ................................................................................................8-18
8-10 In-Service Register.....................................................................................................8-19
8-11 Poll Register...............................................................................................................8-20
8-12 Poll Status Register....................................................................................................8-21
8-13 End-of-Interrupt Register............................................................................................8-22
8-14 Interrupt Status Register ............................................................................................8-23
8-15 Interrupt Control Unit in Slave Mode..........................................................................8-24
8-16 Interrupt Sources in Slave Mode................................................................................8-25
8-17 Interrupt Vector Register (Slave Mode Only)..............................................................8-27
8-18 End-of-Interrupt Register in Slave Mode....................................................................8-28
8-19 Request, Mask, and In-Service Registers..................................................................8-28
8-20 Interrupt Vectoring in Slave Mode..............................................................................8-29
8-21 Interrupt Response Time in Slave Mode....................................................................8-30
9-1 Timer/Counter Unit Block Diagram...............................................................................9-2
9-2 Counter Element Multiplexing and Timer Input Synchronization..................................9-3
9-3 Timers 0 and 1 Flow Chart...........................................................................................9-4
9-4 Timer/Counter Unit Output Modes................................................................................9-6
9-5 Timer 0 and Timer 1 Control Registers........................................................................9-7

CONTENTS
xiv
FIGURES
Figure Page
9-6 Timer 2 Control Register ..............................................................................................9-9
9-7 Timer Count Registers................................................................................................9-10
9-8 Timer Maxcount Compare Registers..........................................................................9-11
9-9 TxOUT Signal Timing.................................................................................................9-15
10-1 Typical DMA Transfer.................................................................................................10-2
10-2 DMA Request Minimum Response Time ...................................................................10-4
10-3 Source-Synchronized Transfers.................................................................................10-5
10-4 Destination-Synchronized Transfers..........................................................................10-6
10-5 Two-Channel DMA Module........................................................................................10-9
10-6 Examples of DMA Priority.........................................................................................10-10
10-7 DMA Source Pointer (High-Order Bits).....................................................................10-11
10-8 DMA Source Pointer (Low-Order Bits).....................................................................10-12
10-9 DMA Destination Pointer (High-Order Bits)..............................................................10-13
10-10 DMA Destination Pointer (Low-Order Bits)...............................................................10-14
10-11 DMA Control Register...............................................................................................10-15
10-12 Transfer Count Register...........................................................................................10-19
11-1 80C187-Supported Data Types..................................................................................11-8
11-2 80C186 Modular Core Family/80C187 System Configuration....................................11-9
11-3 80C187 Configuration with a Partially Buffered Bus.................................................11-12
11-4 80C187 Exception Trapping via Processor Interrupt Pin..........................................11-14
12-1 Entering/Leaving ONCE Mode...................................................................................12-2
A-1 Formal Definition of ENTER........................................................................................A-3
A-2 Variable Access in Nested Procedures.......................................................................A-4
A-3 Stack Frame for Main at Level 1..................................................................................A-4
A-4 Stack Frame for Procedure A at Level 2 .....................................................................A-5
A-5 Stack Frame for Procedure B at Level 3 Called from A...............................................A-6
A-6 Stack Frame for Procedure C at Level 3 Called from B ..............................................A-7
B-1 Input Synchronization Circuit.......................................................................................B-1

xv
CONTENTS
TABLES
Table Page
1-1 Comparison of 80C186 Modular Core Family Products...............................................1-2
1-2 Related Documents and Software................................................................................1-3
2-1 Implicit Use of General Registers.................................................................................2-5
2-2 Logical Address Sources............................................................................................2-13
2-3 Data Transfer Instructions..........................................................................................2-18
2-4 Arithmetic Instructions................................................................................................2-20
2-5 Arithmetic Interpretation of 8-Bit Numbers.................................................................2-21
2-6 Bit Manipulation Instructions ......................................................................................2-21
2-7 String Instructions.......................................................................................................2-22
2-8 String Instruction Register and Flag Use....................................................................2-23
2-9 Program Transfer Instructions....................................................................................2-25
2-10 Interpretation of Conditional Transfers.......................................................................2-26
2-11 Processor Control Instructions ...................................................................................2-27
2-12 Supported Data Types ...............................................................................................2-37
3-1 Bus Cycle Types ........................................................................................................3-12
3-2 Read Bus Cycle Types...............................................................................................3-20
3-3 Read Cycle Critical Timing Parameters......................................................................3-20
3-4 Write Bus Cycle Types...............................................................................................3-23
3-5 Write Cycle Critical Timing Parameters......................................................................3-25
3-6 HALT Bus Cycle Pin States........................................................................................3-29
3-7 Queue Status Signal Decoding..................................................................................3-40
3-8 Signal Condition Entering HOLD................................................................................3-42
4-1 Peripheral Control Block...............................................................................................4-3
5-1 Suggested Values for Inductor L1 in Third Overtone Oscillator Circuit........................5-4
5-2 Summary of Power Management Modes...................................................................5-23
6-1 Chip-Select Unit Registers...........................................................................................6-6
6-2 UCS Block Size and Starting Address........................................................................6-12
6-3 LCS Active Range......................................................................................................6-13
6-4 MCS Active Range.....................................................................................................6-13
6-5 MCS Block Size and Start Address Restrictions........................................................6-14
6-6 PCS Active Range......................................................................................................6-15
7-1 Identification of Refresh Bus Cycles.............................................................................7-5
8-1 Default Interrupt Priorities.............................................................................................8-3
8-2 Fixed Interrupt Types ...................................................................................................8-9
8-3 Interrupt Control Unit Registers in Master Mode........................................................8-11
8-4 Interrupt Control Unit Register Comparison...............................................................8-26
8-5 Slave Mode Fixed Interrupt Type Bits ........................................................................8-26
9-1 Timer 0 and 1 Clock Sources.....................................................................................9-12
9-2 Timer Retriggering......................................................................................................9-13
11-1 80C187 Data Transfer Instructions.............................................................................11-3
11-2 80C187 Arithmetic Instructions...................................................................................11-4
11-3 80C187 Comparison Instructions...............................................................................11-5
11-4 80C187 Transcendental Instructions..........................................................................11-5
11-5 80C187 Constant Instructions....................................................................................11-6

CONTENTS
xvi
TABLES
Table Page
11-6 80C187 Processor Control Instructions......................................................................11-6
11-7 80C187 I/O Port Assignments..................................................................................11-10
C-1 Instruction Format Variables........................................................................................C-1
C-2 Instruction Operands...................................................................................................C-2
C-3 Flag Bit Functions........................................................................................................C-3
C-4 Instruction Set .............................................................................................................C-4
D-1 Operand Variables ......................................................................................................D-1
D-2 Instruction Set Summary.............................................................................................D-2
D-3 Machine Instruction Decoding Guide...........................................................................D-9
D-4 Mnemonic Encoding Matrix.......................................................................................D-20
D-5 Abbreviations for Mnemonic Encoding Matrix...........................................................D-22

xvii
CONTENTS
EXAMPLES
Example Page
5-1 Initializing the Power Management Unit for Idle or Powerdown Mode.......................5-16
5-2 Initializing the Power Management Unit for Power-Save Mode.................................5-22
6-1 Initializing the Chip-Select Unit...................................................................................6-20
7-1 Initializing the Refresh Control Unit............................................................................7-11
8-1 Initializing the Interrupt Control Unit for Master Mode................................................8-31
9-1 Configuring a Real-Time Clock...................................................................................9-18
9-2 Configuring a Square-Wave Generator......................................................................9-21
9-3 Configuring a Digital One-Shot...................................................................................9-22
10-1 Initializing the DMA Unit...........................................................................................10-23
10-2 Timed DMA Transfers..............................................................................................10-26
11-1 Initialization Sequence for 80C187 Math Coprocessor ............................................11-15
11-2 Floating Point Math Routine Using FSINCOS..........................................................11-16

1
Introduction