Intel F-Tile SDI II Intel Agilex User manual

F-Tile SDI II Intel® Agilex™ FPGA IP
Design Example User Guide
Updated for Intel® Quartus® Prime Design Suite: 21.4
IP Version: 19.2.0
Online Version
Send Feedback
ID: 710496
Version: 2022.01.28

Contents
1. F-Tile SDI II Intel® Agilex™ FPGA IP Design Example Quick Start Guide......................... 3
1.1. Directory Structure................................................................................................ 3
1.2. Generating the Design............................................................................................6
1.3. Simulating the Design............................................................................................ 7
1.4. Compiling and Testing the Design in Hardware...........................................................9
1.5. Design Example Parameters.................................................................................. 11
2. Design Example Detailed Description............................................................................13
2.1. Features............................................................................................................. 13
2.2. Hardware and Software Requirements.................................................................... 14
2.3. Functional Description.......................................................................................... 15
2.3.1. Design Components................................................................................. 19
2.3.2. Clocking Scheme..................................................................................... 22
2.4. Simulation.......................................................................................................... 27
2.4.1. Testbench Components............................................................................. 27
2.4.2. Test Description....................................................................................... 28
2.4.3. Hardware Testing..................................................................................... 29
2.4.4. Signal.................................................................................................... 30
3. Document Revision History for the F-Tile SDI II Intel Agilex Design Example User
Guide....................................................................................................................... 39
Contents
F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide Send Feedback
2

1. F-Tile SDI II Intel® Agilex™ FPGA IP Design Example
Quick Start Guide
The SDI II Intel® FPGA IP design examples for Intel Agilex™ F-tile devices feature a
simulating testbench and a hardware design that supports compilation and hardware
testing.
When you generate a design example, the parameter editor automatically creates the
files necessary to simulate, compile, and test the design in hardware.
Note: The support for 21.4 Intel Agilex SDI II Design Example hardware is preliminary and
only supports static rate.
Figure 1. Development Stages
Design
Example
Generation
Compilation
(Simulator)
Compilation
(Quartus Prime)
Functional
Simulation
Hardware
Testing
1.1. Directory Structure
The directories contain the generated files for the design examples.
710496 | 2022.01.28
Send Feedback
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel
Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the
application or use of any information, product, or service described herein except as expressly agreed to in
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered

Figure 2. Directory Structure for the Design Examples
<Design Example>
qdb
quartus
sdi_ii_agi_demo.qpf
sdi_ii_agi_demo.qsf
sdi_ii_agi_demo.sv
sdi_ii_agi_demo.sdc
edge_detector.sv
clock_heartbeat.v
sgpio_slave.v
vid_pattgen (for serial loopback design)
rx (for simplex mode design)
tx (for simplex mode design)
du (for duplex mode design)
loopback (for parallel loopback design)
phy_adapter
alt_reset_delay.v
device_init.sv
<xcvr_ref_sysclk ip generated folder>
xcvr_ref_sysclk.ip
rtl
tpg.ctrl.tcl
generation.log
hwtest
(for serial loopback design)
simulation
mentor
synopsys
testbench
xcelium
<reset_release ip generated folder>
reset_release.ip
jtag.sdc
sim_setup_gen.sh
Table 1. Other Generated Files in RTL Folder
Folders Files
vid_pattgen /sdi_ii_colorbar_gen.v
/sdi_ii_ed_vid_pattgen.v
/sdi_ii_makeframe.v
/sdi_ii_patho_gen.v
/pattgen_ctrl.qsys
<qsys generated folder>
loopback /loopback_top.v
/fifo/sdi_ii_ed_loopback.sdc
/fifo/sdi_ii_ed_loopback.v
du /du_<vid_std>_top.v
sdi_<vid_std>_du_sys.qsys (optional)
<qsys generated folder>
rx /rx_<vid_std>_top.v
/sdi_<vid_std>_rx_sys.qsys
continued...
1. F-Tile SDI II Intel® Agilex™ FPGA IP Design Example Quick Start Guide
710496 | 2022.01.28
F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide Send Feedback
4

Folders Files
<qsys generated folder>
tx /tx_<vid_std>_top.sv
/sdi_<vid_std>_tx_sys.qsys
<qsys generated folder>
phy_adapter /sdi_ftile_phy_adapter.sv
/sdi_ftile_phy_adapter.sdc
/rxdata_dcfifo.ip
/rxdata_mwfifo.ip (optional)
[Only in 12-SDI single rate mode Design Example]
txdata_fifo.ip
<ip generated folder>
Table 2. Other Generated Files in Simulation Folder
Folders Files
mentor /mentor.do
synopsys /vcs/filelist.f
/vcs/vcs_sim.sh
/vcsmx/vcsmx_sim.sh
testbench tb_top.sv
rx_checker/sdi_ii_tb_rx_checker.v
rx_checker/tb_data_compare.v
rx_checker/tb_dual_link_sync.v
rx_checker/tb_fifo_line_test.v
rx_checker/tb_frame_locked_test.sv
rx_checker/tb_ln_check.v
rx_checker/tb_rxsample_test.v
rx_checker/tb_trs_locked_test.sv
rx_checker/tb_txpll_test.sv
rx_checker/tb_vpid_check.v
tb_control/sdi_ii_tb_control.v
tb_control/tb_clk_rst.v
tb_control/tb_data_delay.v
tb_control/tb_serial_delay.sv
tb_control/tb_tasks.v
tb_checker/sdi_ii_tb_tx_checker.v
continued...
1. F-Tile SDI II Intel® Agilex™ FPGA IP Design Example Quick Start Guide
710496 | 2022.01.28
Send Feedback F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide
5

Folders Files
tb_checker/tb_serial_check_counter.v
tb_checker/tb_serial_descrambler.v
tb_checker/tb_tx_clkout_check.v
vid_pattgen/sdi_ii_colorbar_gen.v (for parallel loopback design)
vid_pattgen/sdi_ii_ed_vid_pattgen.v (for parallel loopback design)
vid_pattgen/sdi_ii_makeframe.v (for parallel loopback design)
vid_pattgen/sdi_ii_patho_gen.v (for parallel loopback design)
xcelium /xcelium_sim.sh
1.2. Generating the Design
Configure the SDI II Intel FPGA IP parameter editor in the Intel Quartus® Prime
software to generate the design examples.
Figure 3. Generating the Design Flow
Start Parameter
Editor
Specify IP Variation
and Select Device
Select
Design Parameters
Specify
Example Design
Initiate
Design Generation
1. Create an empty project targeting Intel Agilex device family and select the desired
device.
2. In the IP Catalog, locate and double-click SDI II Intel FPGA IP. The IP
Parameter Editor window appears.
3. Specify a top-level name for your custom IP variation. The parameter editor saves
the IP variation settings in a file named <your_ip>.ip or <your_ip>.qsys.
4. On the Design Example tab, select the desired parameter for the design
example. Select Simulation to generate the testbench, and select Synthesis to
generate the hardware design example.
5. For Target Development Kit, select the relevant FPGA development kit. You may
change the target device using the Change Target Device parameter if your
board revision does not match the grade of the default targeted device.
6. Click Generate Example Design button to initiate the design generation.
1. F-Tile SDI II Intel® Agilex™ FPGA IP Design Example Quick Start Guide
710496 | 2022.01.28
F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide Send Feedback
6

Figure 4. Design Example Tab in SDI II IP Parameter Editor
1.3. Simulating the Design
Figure 5. Simulating the Design flow
Run
Support Logic Generation
in Quartus
Run
Generate Simulator Setup
Script for IP
in Quartus
Go to
simulation/<Simulator>
Directory
Run
<Simulation Script>
To run example design simulation, follow these steps:
1. Generate the necessary simulation setup files.
a. Using GUI method:
i. Open the Intel Quartus Prime Project in Intel Quartus Prime directory.
ii. Run Support-Logic Generation to generate the transceiver RTL files.
Figure 6. Support-Logic Generation in Compilation Dashboard
1. F-Tile SDI II Intel® Agilex™ FPGA IP Design Example Quick Start Guide
710496 | 2022.01.28
Send Feedback F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide
7

iii. To generate the simulation setup files, click Tools ➤ Generate Simulator
Setup Script for IP....
iv. Set the output directory to .../simulation.
Figure 7. Generating Simulation Setup File Using GUI
b. Using command-line:
i. Open a command-line terminal.
ii. Make sure your environment variable points to the bin/bin64 in your
Intel Quartus Prime installation directory
iii. Change the current directory to the generated simulation folder in your
terminal.
iv. Run this command source sim_setup_gen.sh.
2. Go to simulation folder.
3. Go to the desired simulator folder and run the simulation script:
a. ModelSim* SE or Questa* FE: Bring up the simulator GUI, change directory
to mentor folder and type do mentor.do
b. VCS*: Go to synopsys/vcs folder and type source vcs_sim.sh.
c. VCS MX: Go to synopsys/vcsmx folder and type source vcsmx_sim.sh
d. Xcelium* (supported verilog only): Go to xcelium folder and type source
xcelium_sim.sh(1)
4. A successful simulation ends with the following message:
(1) Xcelium is not supporting VHDL format.
1. F-Tile SDI II Intel® Agilex™ FPGA IP Design Example Quick Start Guide
710496 | 2022.01.28
F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide Send Feedback
8

1.4. Compiling and Testing the Design in Hardware
Figure 8. Compiling and Testing the Design Flow
Compile Design
in Quartus Prime
Software
Set Up Hardware Test Design
in Hardware
Program Device
To compile and run a demonstration test on the hardware design example, follow
these steps:
1. Open the Intel Quartus Prime project (sdi_ii_agi_demo.qpf) located in
Quartus directory.
2. To perform Intel Quartus Prime compilation, click Processing ➤ Start
Compilation.
3. Connects the Nextera SDI daughter card to FMC port A on the development kit.
4. For parallel loopback design, connects the BNC RX connector (J1/12G In) to an
external video source and connects the TX connector (J2/12G Out) to a video
analyzer. For serial loopback design, connects the BNC TX connector (J2/12G
Out) to RX connector (J1/12G In) or a video analyzer.
5. Ensure all the switches on the development kit are in their default position per
Agilex I-series SoC Development Kit User Guide.
6. After the compilation completes, open Programmer and program the
generated .sof file to the development kit.
7. For serial loopback design, you need to open System Console to control the
internal video pattern generator.
a. Go to Tools ➤ System Debugging Tools and click System Console.
b. After the initialization, type source ../hwtest/tpg_ctrl.tcl to open the
pattern generator control UI.
c. Select your desired video format through the UI.
Note: To allow segmented frame video format (1080sF30, 1080sF25) and
interlaced video format (1080i60, 1080i50) to be correctly differentiated in
external analyzer, you must insert Payload ID in the serial loopback design
1. F-Tile SDI II Intel® Agilex™ FPGA IP Design Example Quick Start Guide
710496 | 2022.01.28
Send Feedback F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide
9

Figure 9. Selecting Video Format Through System Console
8. The analyzer should be able to display the video generated from the source. Refer
to jumper settings in the Jumper Settings and Descriptions Table to change the
jumper (J8) position before switching between fractional frame rate and integer
frame rate video format. You must press the push button (PB0) to trigger a device
(LMK03328) power cycling through the PDN pin every time you change the jumper
(J8) position.
Figure 10. Jumper Settings on Nextera 12G-SDI FMC Daughtercard
1. F-Tile SDI II Intel® Agilex™ FPGA IP Design Example Quick Start Guide
710496 | 2022.01.28
F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide Send Feedback
10

Table 3. Jumper Settings and Descriptions
Jumper Block Description Setting
J7 Programming Header -
J8
To switch the generated clock
frequency to TX channel:
• Pin 1-2 = 297 Mhz
• Pin 2-3 = 297/1.001 Mhz
1-2: 297 Mhz
2-3: 297/1.001 Mhz
J9
To select SDI or IP mode:
• Pin 1-2 = SDI mode
• Pin 2-3 = IP mode
1-2
Related Information
Agilex I-series SoC Development Kit User Guide
1.5. Design Example Parameters
Table 4. Parameters available in Design Example tab
Parameter Value Description
Select Design • Parallel loopback with
external VCXO
• Serial loopback
Select available design example to be generated.
•Parallel loopback with external VCXO: Parallel
loopback design with an external VCXO to synchronize
the clock between RX and TX.
•Serial loopback: An internal video pattern generator
generates along with TX and transmits to RX. This
design allows simple demonstration when you do not
have a video source available.
Simulation On / Off Turns on this option to generate necessary files for
simulation testbench.
Synthesis On Turns on this option to generate necessary files forIntel
Quartus Prime compilation and hardware demo.
This option is greyed out and set to always Enabled. This is
because synthesis files are still required to run Support-
Logic Generation stage in Intel Quartus Prime to generate
the transceiver tile’s files which are essential to run
simulation as well.
Generate File Format • Verilog
• VHDL
Select the HDL format for generated design example fileset.
Note that the HDL format only affects the generated top
level IP files. All the other files, for example testbenches
and top level files for hardware demo are in Verilog.
Select Daughter card • Nextera VIDIO 12G-SDI
FMC card
Select the daughter card for the targeted design example.
This option is greyed out as only Nextera VIDIO 12G-SDI
FMC card is supported in this design example.
Select Board • No Development Kit
• Agilex I-Series SOC
Development Kit
• Custom Development Kit
Select the board for the targeted design example.
continued...
1. F-Tile SDI II Intel® Agilex™ FPGA IP Design Example Quick Start Guide
710496 | 2022.01.28
Send Feedback F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide
11

Parameter Value Description
• No Development Kit: This option excludes hardware
aspects for the design example. All the pin assignments
are set to virtual pins.
• Agilex I-Series SOC Development Kit: This option
automatically selects the project’s target device to
match the device on this development kit. You may
change the target device with the “Change Target
Device” parameter below if your board revision has a
different grade of the default targeted device. All the
pins assignment has been set accordingly to the
development kit.
• Custom Development Kit: This option allows the design
example to be tested on a third-party development kit
with Intel FPGA device. You may need to set the pin
assignment on your own.
Change Target Device On / Off Turn on this option and select the preferred device variant
for the development kit.
Related Information
Nextera Vidio
For more information about Nextera VIDIO 12G-SDI FMC card.
1. F-Tile SDI II Intel® Agilex™ FPGA IP Design Example Quick Start Guide
710496 | 2022.01.28
F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide Send Feedback
12

2. Design Example Detailed Description
The SDI II Intel FPGA IP core includes the following design examples for Intel Agilex
F-tile devices.
• Parallel loopback with external VCXO
• Serial loopback
Note: Only Single-Rate design examples are available in the Intel Quartus Prime 21.4
software. Multi-rate design will be available in a future Intel Quartus Prime release.(2)
2.1. Features
1. LED status for early debugging stage with RX or TX only options.
2. To use RX or TX only components, remove the irrelevant blocks from the simplex
version serial loopback design as described in the following table.
Table 5. Features
User Require Preserve Remove
RX only • RX top
• Reference and System PLL Clocks
IP
• DR IP & DR arbiter (if present)
• Device Init
TX Top
TX only • TX top
• Reference and System PLL Clocks
IP
• DR IP & DR arbiter (if present)
• Device Init
RX Top
(2) Statements in this document that refer to future plans or expectations are forward-looking
statements. These statements are based on current expectations and involve many risks and
uncertainties that could cause actual results to differ materially from those expressed or
implied in such statements.
710496 | 2022.01.28
Send Feedback
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel
Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the
application or use of any information, product, or service described herein except as expressly agreed to in
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered

Figure 11. Components required for TX or RX only design on Intel Agilex Device
Parallel Data
Serial Data Avalon-MM
Control/Status
RX Only Components
TX Only Components
Top
TX Top RX Top
SDI TX Sys
Pattern Gen
Control PIO
JTAG to Avalon
Master Bridge
Pattern Ctrl
SDI RX Sys
Reference
and System
PLL Clocks IP
Video Pattern
Generator
SDI F-tile
PHY Adapter
F-tile PMA/
FEC Direct
PHY IP (TX)
F-tile PMA/
FEC Direct
PHY IP (RX)
SDI II
(TX)
SDI II
(RX)
SDI F-tile
PHY Adapter
Device_init
Common components for TX/RX only design
Note: Refer to Clocking Scheme on page 22 for the Reference and System PLL Clocks IP
connections.
2.2. Hardware and Software Requirements
Intel uses the following hardware and software to test the design example:
Hardware
• Agilex I-Series SOC Development Kit
• SDI Signal Generator
• SDI Signal Analyzer
• BNC to BNC cables
• VIDIOTM FMC Development Module VIDIO-12G-A (Nextera 12G SDI FMC daughter
card)
2. Design Example Detailed Description
710496 | 2022.01.28
F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide Send Feedback
14

Software
• Intel Quartus Prime software version 21.4 Patch 0.01
• Either one of the following simulators for functional simulation:
— ModelSim - Intel FPGA Edition
— Questa-Intel FPGA Edition
— VCS/VCS MX
— Xcelium (Verilog only)
Related Information
Why does the SDI II Intel® Agilex™ F-Tile FPGA IP design example fail to compile at
the Support-Logic Generation stage?
2.3. Functional Description
The SDI II Intel FPGA IP core design example supports the following simplex and
duplex transceiver mode:.
• Parallel loopback with simplex mode
• Parallel loopback with duplex mode
• Serial loopback with simplex mode
• Serial loopback with duplex mode
2. Design Example Detailed Description
710496 | 2022.01.28
Send Feedback F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide
15

Figure 12. Parallel Loopback with Simplex Mode
Parallel Data
Serial Data
Control/Status
Top
RX Top
SDI RX Sys Loopback Top
Loopback
FIFO
TX Top
SDI TX Sys
SDI F-tile
PHY Adapter
Reference
and System
PLL Clocks IP
SDI F-tile PHY
Adapter
F-tile PMA/
FEC Direct
PHY IP (RX)
F-tile PMA/
FEC Direct
PHY IP (TX)
Device_init
SDI II
(RX)
SDI II
(TX)
Note: Refer to Clocking Scheme on page 22 for the Reference and System PLL Clocks IP
connections.
2. Design Example Detailed Description
710496 | 2022.01.28
F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide Send Feedback
16

Figure 13. Parallel Loopback with Duplex Mode
Parallel Data
Serial Data
Control/Status
Top
Du Top
SDI RX Sys
Loopback Top
Loopback
FIFO
Reference
and System
PLL Clocks IP
SDI F-tile
PHY Adapter Device_init
F-tile PMA/
FEC Direct
PHY IP (RX)
F-tile PMA/
FEC Direct
PHY IP (TX)
SDI II
(Duplex)
Note: Refer to Clocking Scheme on page 22 for the Reference and System PLL Clocks IP
connections.
2. Design Example Detailed Description
710496 | 2022.01.28
Send Feedback F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide
17

Figure 14. Serial Loopback with Simplex Mode
Parallel Data
Serial Data Avalon-MM
Control/Status
Top
TX Top RX Top
SDI TX Sys
Pattern Gen
Control PIO
JTAG to Avalon
Master Bridge
Pattern Ctrl
SDI RX Sys
Reference
and System
PLL Clocks IP
Video Pattern
Generator
SDI F-tile
PHY Adapter
F-tile PMA/
FEC Direct
PHY IP (TX)
F-tile PMA/
FEC Direct
PHY IP (RX)
SDI II
(TX)
SDI II
(RX)
SDI F-tile
PHY Adapter
Device_init
Note: Refer to Clocking Scheme on page 22 for the Reference and System PLL Clocks IP
connections.
2. Design Example Detailed Description
710496 | 2022.01.28
F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide Send Feedback
18

Figure 15. Serial Loopback with Duplex Mode
Parallel Data
Serial Data Avalon-MM
Control/Status
Top
Du Top
SDI Du Sys
Pattgen Ctrl
Pattern Gen
Control PIO
Video Pattern
Generator
JTAG to Avalon
Master Bridge
Reference
and System
PLL Clocks IP
SDI F-tile
PHY Adapter
Device_init
F-tile PMA/
FEC Direct
PHY IP (RX)
F-tile PMA/
FEC Direct
PHY IP (TX)
SDI II
(Duplex)
Note: Refer to Clocking Scheme on page 22 for the Reference and System PLL Clocks IP
connections.
2.3.1. Design Components
The SDI II Intel FPGA IP core design examples require the following components.
2. Design Example Detailed Description
710496 | 2022.01.28
Send Feedback F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide
19

Table 6. Device Under Test (DUT) Components
Component Description
SDI II • TX
— The IP core receives the video data from top level and encodes the
necessary information, for example line number, CRC or payload ID into
the data streams.
• RX
— The IP core receives the parallel data from Transceiver Native PHY and
performs necessary decoding, such as descrambling, realigning the data
and extracting the necessary information.
— The output data from these blocks connects to the SDI F-tile PHY adapter
module before passing it to Direct PHY IP.
F-tile PMA/FEC Direct PHY • TX
— Hard transceiver block which receives the parallel data from SDI core and
serialize the data before transmitting it.
• RX
— Hard transceiver block to receive the serial data from an external video
source.The PHY runs in System PLL clocking mode and system clock
output always runs at a higher clock frequency than the native PMA
recovered clock.
SDI mode Minimum System PLL output
frequency
HD-SDI single rate 150 MHz
3G-SDI single rate 300 MHz
12G-SDI single rate 600 MHz
PHY adapter Adapter block which includes DCFIFO for converting the bit width of parallel data
between transceiver and SDI core, as well as to transfer the data between these
two clock domains.
Table 7. Loopback Top Components
Component Description
Loopback FIFO This module contains DCFIFO for video data transferring between receiver clock
domain and transmitter clock domain.
Table 8. Video Pattern Generator Components
Component Description
Video Pattern Generator Basic video pattern generator which can support SD-SDI up to 12G-SDI video
formats with 4:2:2 YCbCr. You can select static video with colorbar pattern or
pathological pattern from this pattern generator.
Pattern Gen Control PIO Provides a memory-mapped interface for controlling the video pattern generator.
JTAG to Avalon Master Bridge Provides System Console host access to the Parallel I/O (PIO) IP in the design
via the JTAG interface.
Table 9. Common Blocks at Top Level
Common Block Description
Reference and System PLL Clocks This IP connects the System PLL output clock as well as the TX PLL and RX CDR
reference clock to the F-tile PMA/FEC Direct PHY IP.
System PLL clock output is always set to run at a higher clock frequency than the
native PMA recovered clock.
continued...
2. Design Example Detailed Description
710496 | 2022.01.28
F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide Send Feedback
20