Intel NetStructure ZT 5515 Owner's manual

Intel®NetStructureTM ZT 5515
Compute Processor Board
Technical Product Specification
June 2004
Order Number: 273813-005
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2Intel®NetStructureTM ZT 5515 Compute Processor BoardTechnical Product Specification
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Intel®NetStructureTM ZT 5515 Compute Processor Board Technical Product Specification 3
Contents
Contents
1 Document Organization................................................................................................................9
2 Introduction..................................................................................................................................11
2.1 Product Definition ...............................................................................................................11
2.2 Features..............................................................................................................................13
2.3 Functional Blocks................................................................................................................14
2.3.1 CompactPCI*/PSB Architecture.............................................................................14
2.3.2 Processor...............................................................................................................15
2.3.3 Chipset...................................................................................................................15
2.3.4 PCI-to-PCI Bridge (Not supported)........................................................................16
2.3.5 Memory and I/O Addressing..................................................................................16
2.3.6 Power Ramp Circuitry............................................................................................16
2.3.7 Rear-Panel I/O.......................................................................................................17
2.3.8 PCI Video...............................................................................................................17
2.3.9 PCI Mezzanine Card (PMC) Interface ...................................................................17
2.3.10 Dual Ethernet Interfaces........................................................................................18
2.3.11 IDE Hard Drive.......................................................................................................18
2.3.12 Serial I/O................................................................................................................18
2.3.13 Interrupts................................................................................................................18
2.3.14 Counter/Timers......................................................................................................19
2.3.15 DMA.......................................................................................................................19
2.3.16 Real-Time Clock ....................................................................................................19
2.3.17 Reset .....................................................................................................................20
2.3.18 Two-Stage Watchdog Timer..................................................................................20
2.3.19 Universal Serial Bus (USB)....................................................................................20
2.3.20 Baseboard Management Controller.......................................................................20
2.3.21 IDE Controller ........................................................................................................20
2.3.22 Floppy Disk Controller ...........................................................................................21
2.3.23 Keyboard and Mouse Controller............................................................................21
2.3.24 LED Indicators .......................................................................................................21
2.4 Software..............................................................................................................................22
3 Getting Started.............................................................................................................................23
3.1 Unpacking...........................................................................................................................23
3.2 System Requirements ........................................................................................................23
3.2.1 BIOS Version.........................................................................................................23
3.2.2 Connectivity ...........................................................................................................24
3.2.3 Electrical and Environmental .................................................................................24
3.3 Memory Configuration ........................................................................................................25
3.4 I/O Configuration.................................................................................................................27
3.5 Connectors .........................................................................................................................27
3.6 Switch Options....................................................................................................................28
3.7 BIOS Configuration Overview.............................................................................................28
3.8 Operating System Installation.............................................................................................30
4 Configuration...............................................................................................................................31
4.1 Switch Options and Locations ............................................................................................31
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4Intel®NetStructureTM ZT 5515 Compute Processor BoardTechnical Product Specification
Contents
4.2 Switch Descriptions ............................................................................................................32
4.2.1 SW1 (Reset)..........................................................................................................32
4.2.2 SW2-1 (Flash Write-Protect)..................................................................................33
4.2.3 SW2-2 (IPMI Flash Write Protect) .........................................................................33
4.2.4 SW2-3 (Real-Time Clock Reset) ...........................................................................33
4.2.5 SW2-4 (CMOS Clear)............................................................................................33
4.2.6 SW3-1 (BIOS Recovery Module/Flash Select)......................................................34
4.2.7 SW3-2 (Bypass BMC to power up)........................................................................34
4.2.8 SW3-3 (Ethernet SMBUS isolation).......................................................................34
4.2.9 SW3-4 (VGA Routing Control)...............................................................................34
4.2.10 SW4-1, SW4-2 (Software Configuration)...............................................................35
4.2.11 SW4-3 (Console Redirection)................................................................................35
4.2.12 SW4-4 (BMC Dual Domain Mode).........................................................................35
4.2.13 SW5 (Ejector Switch).............................................................................................35
4.3 Jumper Descriptions...........................................................................................................36
4.3.1 J29 (BIOS Configuration Mode).............................................................................36
5 Reset.............................................................................................................................................37
5.1 Reset Types and Sources..................................................................................................37
5.1.1 Hard Reset Sources ..............................................................................................37
5.1.2 Soft Reset Sources................................................................................................37
5.1.3 Backend Power Down Sources.............................................................................38
5.1.4 NMI Sources..........................................................................................................38
6 System Monitoring and Control.................................................................................................39
6.1 Monitoring and Control Functions.......................................................................................39
6.1.1 Field Replaceable Unit (FRU) Information.............................................................40
6.1.2 System Event Log Information...............................................................................40
6.2 SMBus Address Map..........................................................................................................40
7 IDE Controller ..............................................................................................................................41
7.1 Features of the IDE Controller............................................................................................41
7.2 Disk Drive Support..............................................................................................................41
7.2.1 Primary IDE Channel.............................................................................................41
7.2.2 Secondary IDE Channel........................................................................................41
7.3 IDE I/O Mapping.................................................................................................................42
7.4 IDE CompactFlash Carrier..................................................................................................42
7.5 IDE Device Drivers .............................................................................................................42
8 Watchdog Timer..........................................................................................................................43
8.1 Watchdog Timer Overview .................................................................................................43
8.1.1 Power Up Initialization...........................................................................................44
8.1.2 Timeout Values......................................................................................................44
8.2 Using the Watchdog in an Application................................................................................44
8.2.1 Watchdog Reset....................................................................................................44
8.2.1.1 Enabling the Watchdog Reset ...............................................................44
8.2.1.2 Setting the Terminal Count....................................................................45
8.2.1.3 Strobing the Watchdog ..........................................................................45
8.2.2 Watchdog NMI.......................................................................................................46
8.2.2.1 Chaining the ISRs..................................................................................46
8.2.2.2 Enabling the Watchdog NMI..................................................................47
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Intel®NetStructureTM ZT 5515 Compute Processor Board Technical Product Specification 5
Contents
8.2.2.3 NMI Handler...........................................................................................48
9 System BIOS................................................................................................................................49
9.1 On-board Flash Memory.....................................................................................................49
9.1.1 Flash Utility Program .............................................................................................49
9.2 BIOS Configuration Overview.............................................................................................50
9.3 System Information Structure.............................................................................................50
9.3.1 Implementation ......................................................................................................50
9.3.2 Detailed Structure Element Descriptions...............................................................52
9.3.3 How to Find the System Information Structure......................................................55
9.4 OSFlash..............................................................................................................................56
9.4.1 Implementation ......................................................................................................56
9.5 Plug and Play (PnP) ...........................................................................................................56
9.5.1 Resource Allocation...............................................................................................56
9.5.2 PnP ISA Auto-configuration...................................................................................57
9.5.3 PCI Auto-configuration...........................................................................................58
9.5.4 Legacy ISA Configuration......................................................................................58
9.5.5 Automatic Detection of Video Adapters.................................................................58
9.6 BIOS Recovery...................................................................................................................58
9.7 Console Redirection ...........................................................................................................59
9.8 System Management BIOS (SMBIOS)...............................................................................59
9.8.1 EN 50081-1 Emissions ..........................................................................................91
9.8.2 EN 55024 Immunity ...............................................................................................92
9.8.3 FCC (USA).............................................................................................................92
Figures
1 ZT 5515 Faceplate......................................................................................................................12
2 Functional Block Diagram...........................................................................................................14
3 Memory Address Map Example..................................................................................................26
4 I/O Address Map.........................................................................................................................26
5 Setup Screen..............................................................................................................................29
6 Default Switch Configuration ......................................................................................................32
7 Watchdog Timer Architecture.....................................................................................................43
8 PCB Dimensions.........................................................................................................................64
9 Connector Locations...................................................................................................................65
10 Backplane Connectors - Pin Locations.......................................................................................66
Tables
1 Fault Current Limits ....................................................................................................................16
2 Electrical and Environmental......................................................................................................24
3 Switch Cross-Reference Table...................................................................................................31
4 SW2-1 Status..............................................................................................................................33
5 SW2-2 Status..............................................................................................................................33
6 SW2-3 Status..............................................................................................................................33
7 SW2-4 Status..............................................................................................................................33
8 SW3-1 Status..............................................................................................................................34
9 SW3-2 Status..............................................................................................................................34
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6Intel®NetStructureTM ZT 5515 Compute Processor BoardTechnical Product Specification
Contents
10 SW3-3 Status .............................................................................................................................34
11 SW3-4 Status .............................................................................................................................34
12 SW4-3 Status .............................................................................................................................35
13 SW4-4 Status .............................................................................................................................35
14 SW5 Status.................................................................................................................................36
15 J-29 Status .................................................................................................................................36
16 SMBus Device Details................................................................................................................40
17 Detailed Structure Element Descriptions....................................................................................52
18 Absolute Maximum Ratings........................................................................................................61
19 DC Operating Characteristics.....................................................................................................62
20 Battery Backup Characteristics ..................................................................................................62
21 Board Dimensions and Weight...................................................................................................63
22 Connector Assignments .............................................................................................................64
23 J1 CompactPCI Bus Connector Pinout ......................................................................................67
24 J2 CompactPCI Bus Connector Pinout ......................................................................................68
25 J3 Connector Pinout...................................................................................................................69
26 J5 Rear Panel I/O Connector Pinout..........................................................................................70
27 JA1 Ethernet A Connector Pinout...............................................................................................71
28 J25 VGA Connector Pinout ........................................................................................................72
29 J20 Universal Serial Bus 0 Connector Pinout.............................................................................72
30 J30 COM1 Serial Port Pinout .....................................................................................................72
31 J11 PCI Mezzanine Connector Pinout........................................................................................73
32 J12 PCI Mezzanine Connector Pinout........................................................................................74
33 J14 PCI Mezzanine Connector Pinout........................................................................................75
34 J8 IDE Connector Pinout............................................................................................................76
35 Thermal Requirements...............................................................................................................77
36 System Register Definitions .......................................................................................................79
37 Flash Control (78h).....................................................................................................................80
38 Watchdog (79h)..........................................................................................................................81
39 PAL Revision ID (7Bh)................................................................................................................82
40 Port 80 BIOS POST Codes (80h)...............................................................................................82
41 Switch Monitors (E3h) ................................................................................................................83
42 Geographic Addressing (E4h) ....................................................................................................84
43 SM Bus Enable (E6h).................................................................................................................84
Revision History
Date Revision Description
June 2004 005 Removed 2 Gbyte memory support due to lack of manufacturers of single-stick 2-Gbyte SDRAM (DDR
unregistered, unbuffered, ECC/non-ECC).
June 2003 004 Updated warranty and customer support information.
November 2002 003 Changed MTBF
November 2002 002 Changed default switch configuration to show SW 4 Open by
default.
November 2002 001 Initial release of this document
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Intel®NetStructureTM ZT 5515 Compute Processor Board Technical Product Specification 7
Document Organization
Document Organization 1
This document describes the operation and use of the Intel®NetStructure™ ZT 5515 Compute
Processor Board with a Mobile Intel®Pentium® 4 Processor - M. This board is a single board
computer designed to work as a modular component in a CompactPCI* system. The Mobile Intel®
Pentium®4 Processor-M is utilized in a micro FCPGA package along with dual Gigabit Ethernet
controllers and the latest in memory and I/O technology to provide an inexpensive, yet fast and
reliable PICMG 2.16 board.
The following topics are covered in this document.
Chapter 2, “Introduction” introduces the key features of the ZT 5515. This chapter includes a
product definition, a list of product features, and a functional block diagram with a brief
description of each block. This chapter can be used to compare the features of the ZT 5515 against
the needs of a specific application.
Chapter 3, “Getting Started” provides unpacking instructions and initial setup information for the
ZT 5515. This chapter summarizes configuration information and should be read before using the
board.
Chapter 4, “Configuration” describes the switches and cuttable traces on the ZT 5515. This chapter
details factory default settings and provides information about tailoring the board to the needs of
specific applications.
Chapter 5, “Reset”discusses the reset types and reset sources available on the ZT 5515.
Chapter 6, “System Monitoring and Control” lists various system monitoring and control features
available on the ZT 5515.
Chapter 7, “IDE Controller” provides an introduction to the ZT 5515's IDE Controller. This
chapter covers drive configuration, IDE I/O mapping, device drivers, and the ZT 5515's support for
internal and external disk drives.
Chapter 8, “Watchdog Timer” explains the operation of the ZT 5515's watchdog timer. Sample
code is provided to illustrate how the watchdog's functions are used in an application.
Chapter 9, “System BIOS” discusses recovery from and correction of a corrupted BIOS.
Appendix A, “Specifications” contains the electrical, environmental, and mechanicalspecifications
for the ZT 5515. This chapter also provides a connector location illustration and connector pinout
tables.
Appendix B, “Thermal Considerations” describes the thermal requirements for reliable operation
of the ZT 5515.
Appendix C, “System Registers” provides a detailed description of the system registers available
for monitoring and controlling various board operations.
Appendix D, “Datasheet Reference” provides links to web sites with information about many of
the devices and technologies used in the ZT 5515.
Appendix E, “Warranty Information” provides warranty information.
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8Intel®NetStructureTM ZT 5515 Compute Processor BoardTechnical Product Specification
Document Organization
Appendix F, “Customer Support” provides technical and sales assistance information.
Appendix G, “Agency Approvals” presents UL, CE, and FCC agency approval and certification
information for the ZT 5515.
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Intel®NetStructureTM ZT 5515 Compute Processor Board Technical Product Specification 9
Introduction
Introduction 2
This chapter provides an introduction to the Intel®NetStructure™ ZT 5515 Compute Processor
Board including a product definition, a list of product features, and a functional block diagram with
descriptions of each block.
Figure 1, “ZT 5515 Faceplate” on page 10 identifies the connectors, indicators, and switches
available on the ZT 5515's faceplate. Optional rear-panel transition boards are available to extend
various faceplate features to a system's rear-panel. For more information about compatible rear-
panel transition boards, see the Intel®NetStructure™ZT 4807 Packet Switched Rear-Panel
Transition Board Hardware Manual available from the Intel website at http://www.intel.com/
network/csp/products/cpci_index.htm.
2.1 Product Definition
The ZT 5515 Compute Processor Board is a single board computer designed to work as a modular
component in a CompactPCI* system. It utilizes the Mobile Intel®Pentium®4 Processor -M in a
micro FCPGA package along with dual Gigabit Ethernet controllers and the latest in memory and
I/O technology to provide an inexpensive, fast and reliable PICMG* 2.16 board. The ZT 5515 is
CompactPCI Packet Switching Backplane (CompactPCI/PSB) compatible and draws its power
from the J1 and J2 connectors, but it does not contain a CompactPCI* bus. The ZT 5515 does
include a dual Intelligent Platform Management Bus (IPMB) for system management along with
IPMI v1.5 compatible firmware.
The ZT 5515 occupies a single 6U high Eurocard slot. The board can be used in either a system
master slot or in a peripheral slot. In either case the ZT 5515 will not run or interact with other
devices on the CompactPCI bus, instead this board relies on its fast Ethernet controllers for inter-
board communications.
Though the ZT 5515 is highly integrated, its capabilities can be extended with optional boards
available from Intel. Expansion boards are available to add CompactFlash* (Intel® NetStructure™
ZT 96080) in place of the hard drive and rear transition boards (Intel® NetStructure™ZT 4807) are
available to extend I/O access to the rear of a system. For more information about options and
accessories, including the ZT 96080 CompactFlash Carrier, see the Intel®NetStructure™building
blocks page at:
http://developer.intel.com/design/network/products/cbp/linecard.htm
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10 Intel®NetStructureTM ZT 5515 Compute Processor BoardTechnical Product Specification
Introduction
Figure 1. ZT 5515 Faceplate
Ejector Handle
Ejector Handle
PMC
Video
Ethernet
USB
CPU Reset Switch
COM RS-232
Serial Port
IDE Activity LED
Reset LED
Status LED Hotswap LED
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