Intel SL3QA - Pentium III 550 MHz Processor User manual

Intel®Pentium®III Processor
Specification Update
August 2008
Revision 060
Document Number: 244453-060

2Specification Update
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
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AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS
INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR
INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use
in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
The Intel® Pentium® III processor may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Pentium, Intel Xeon, Celeron, MMX and the Intel logo are trademarks or registered trademarks of Intel Corporation or its
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*Other names and brands may be claimed as the property of others.
Copyright © 1999-2008, Intel Corporation.

Specification Update 3
Contents
Preface............................................................................................................................. 8
Summary Tables of Changes.............................................................................................. 10
Identification Information .................................................................................................. 20
Errata ............................................................................................................................ 39
Specification Changes....................................................................................................... 88
Specification Clarifications ................................................................................................. 89
Documentation Changes ................................................................................................... 93

4Specification Update
Revision History
Revision Description Date
-001 This is the first Specification Update for Pentium® III processors. March 1999
-002 Added Erratum E42. Deleted Erratum E16 and renumbered existing
items. Corrected Errata table “Plans” column for E39. Updated the
Pentium III Processor Identification Information table.
April 1999
-003 Updated the Pentium III Processor Identification Information table.
Updated the Errata table by marking Errata E34, E35, and E40 as
Fixed.
May 1999
-004 Updated the Pentium III Processor Identification and Package
Information table. Added Erratum 43. Added Documentation Change
E1. Added Specification Clarifications E1 and E2. Added Specification
Change E3.
June 1999
-005 Added footnote 4 to the Pentium III Processor Identification and
Package Information table. Added Erratum E44. Added stepping Kc0 in
Summary Table of Changes. Added Mixed Steppings in DP Systems
section. Updated Documentation Changes, Specification Clarifications,
and Specification Changes introduction paragraphs.
July 1999
-006 Added Errata E45 and E46. Added Documentation Change E2.
Updated Identification Information table. Updated and corrected
Pentium III Processor Identification and Package Information table.
Updated Codes Used in Summary Table. Updated column heading in
Errata, Documentation Changes, Specification Clarifications and
Specification Changes tables.
August 1999
-007 Revised Errata E45. Updated DP Platform Population Matrix for the
Pentium III Processor with 100 MHz System Bus. Updated datasheet
references to include the latest supported frequency.
September 1999
-008 Added Errata E47. Updated the Pentium III Processor Identification and
Package Information table. Added the DP Platform Population Matrix
for the Pentium III Processor with 133 MHz System Bus table. Added
Brand ID column to Identification Information. Updated datasheet
references to include the latest supported frequency.
October 1999
-009 Added Errata E48 and E49. Added Documentation Change E3. Added
new stepping column in the Summary of Changes tables. Updated the
Pentium® III Processor Identification Information tables. Updated
Mixed Steppings in DP System section. Updated the Pentium® III
Process Identification Information table. Updated references.
November 1999
-010 Updated document references in Preface to include new Pentium III
processor datasheets. Updated errata E10, E11, E19, and E32 in the
Summary of Errata table. Added Errata E50-E58. Added
Documentation Change E4. Added Specification Clarification E3.
Added Specification Changes E4 and E5.
December 1999

Specification Update 5
Revision Description Date
-011 Corrected an error in the Summary of Errata table. Erratum E56 was
incorrectly shown as applying to the Ca2 stepping. Erratum E56 does
NOT apply to the Ca2 stepping.
December 1999
-012 Updated Preface to include new Pentium III processor datasheets.
Added 800-MHz Pentium III processor information to the DP Platform
Population Matrix tables and the Pentium® III Processor Identification
and Packaging Information table. Added note 10 to the Pentium® III
Processor Identification and Packaging Information table and updated
Notes column and other table data. Updated erratum E51. Added
Errata E59-E62. Added Documentation Change E5. Added
Specification Change E6.
January 2000
-013 Updated Errata E49 and E61. Added Documentation Change E6.
Updated the Pentium® III Processor Identification Information.
Updated S-Spec SL365. Updated Summary of Changes product letter
codes.
February 2000
-014 Updated Preface to include new Pentium III processor datasheet.
Updated Pentium® III Processor Identification and Package
Information table. Updated Summary of Errata, Summary of
Documentation Changes, Summary of Specification Clarifications
Summary of Specification Changes tables with Cb0 stepping. Updated
Erratum E48.
March 2000
-015 Special Launch Edition: Updated the new Cb0 stepping information.
Updated the document references in the Preface. Updated DP
population table.
March 2000
-016 Updated Processor Identification Information table. Updated DP
Population Tables. Added Errata E63 & E64.
April 2000
-017 Updated Pentium III Processor Identification and Package Information
table. Updated Errata E64. Added Errata E65 & E66.
May 2000
-018 Updated Processor Identification, Summary of Errata, and Summary of
Specification Changes tables. Updated Dual Processor Tables. Added
new Specification Change E7.
June 2000
-019 Added new errata E67 & E68. Updated Processor Identification Table.
Edited erratum E36. Updated Processor Identification, Summary of
Errata, Summary of Documentation Changes, Summary of
Specification Clarifications, Summary of Specification Changes tables
with cC0 Stepping.
July 2000
-020 Added new Erratum E69. Updated Dual Processor Matrix. Updated Dual
Processor Matrix. Updated Processor Identification Table with new C0
step CPUs.
August 2000
-021 Added New Errata E70 & E71. Added Re-Writes for Errata E28, E48, &
E62. Added New Documentation Changes E7 & E8. Updated Dual
Processor Matrix, removed TBDs. Updated Processor Identification
Table.
September 2000
-022 Updated Pentium®III Processor Identification Information table.
Updated Dual Processor Matrix. Added New Errata E72 and E73. Added
New Documentation Changes E9 and E10.
October 2000
-023 Updated Processor Identification Table. Added New Erratum E73. November 2000

6Specification Update
Revision Description Date
-024 Updated Specification Update product key to include the Intel®
Pentium® 4 processor, Revised Erratum E2. Added new
Documentation Changes E11 – E16.
December 2000
-025 Revised Erratum E2. Added new Documentation Changes E17 and E18.
Updated Processor Identification Table.
January 2001
-026 Added new Documentation Change E19. Revised Documentation
Change E17.
February 2001
-027 Added new Errata E74 and E75. March 2001
-028 Added erratum E76 March 2001
-029 Revised Erratum E76 to Fixed. Updated processor identification table.
Updated the tables in the Mixed Steppings in DP Systems section.
May 2001
-030 Updated note 18 in the Pentium® III Processor Identification and
Package Information table. Updated Specification Update product key
to include the Intel® Xeon™ processor
June 2001
-031 Special Launch Edition: Added package marking information under
General Section. Added new S spec info into processor table. Updated
Dual Processor tables. Updated Summary of Errata, Summary of
Documentation, Summary of Specification Clarifications, and Summary
of Changes tables. Added Errata E77 & E78.
June 2001
-032 Added new S spec info into processor table. Revised package marking
information under General Section. Updated Dual Processor tables.
Deleted duplicate information in the processor ID table.
July 2001
-033 Added new errata E79 and E80. Updated DP Matrix Tables August 2001
-034 Changed word “motherboard” to “baseboard” in erratum E78 October 2001
-035 Updated DP population matrix for new tA1 parts. Added Doc Changes
E20, E21, E22, E23, and E24.
November 2001
-036 Special launch edition. Added part with S-Spec SL5VX at 1.33GHz to
the Pentium® III Processor Identification and Package Information list.
November 2001
-037 Added: Doc changes E25, E26, E27, E28, E29, Spec Clarification E4, E5
and Spec Change E8. Added part with S-Spec SL657 to the Processor
ID Information Table
February 2002
-038 Modified Erratum E80 and added Erratum E81. Added Doc Change E1. March 2002
-039 Out of Cycle Special Launch Edition. Added Server LV part with S-Spec
Number SL66D at 800 MHz to the Pentium® III Processor Identification
and Package Information list.
March 2002
-040 Added Doc Change E1. April 2002
-041 Modified Errata E59. Added Doc Changes E1, E2, and E3. May 2002
-042 Added Erratum E82. Added Doc Changes E1 and E2. Added parts with
S-Spec numbers SL6C2, SL6C3, SL6C4 and SL6BZ with Core Stepping
tB1 to the Processor ID Information Table.
June 2002
-043 Added Document Changes E3-E12. Added parts with S-Spec numbers
SL6BW, SL6BX, SL6BY and SL6HC with Core Stepping tB1 to the
Processor ID Information Table. Changed status of erratum E78 to
NOFIX.
July 2002

Specification Update 7
Revision Description Date
-044 Added new Doc Changes E3-E24. Removed parts with S-Spec numbers
SL6C2, SL6C3, SL6C4 and SL6BZ with Core Stepping tB1 from the
Processor ID Information Table.
September 2002
-045 Added Doc Changes E25 to E32. Updated Summary of Changes. October 2002
-046 Updated DP FC-PGA2 Matrix table. Added one S-spec number. December 2002
-047 Added Erratum E83. March 2003
-048 Updated Summary of Errata table E78 and Added one S Spec number. May 2003
-049 Added Errata E84 and E85. November 2003
-050 Updated E85 and added E86 to E89 October 2004
-051 Added Errata E90, E91, E92 November 2004
-052 Added Errata E93, E94 February 2005
-053 Updated Errata E80 March 2005
-054 Added Specification Clarification April 2005
-055 Added Errata E95, E96, E97, E98, E99, E100, E101, E102, E103, E104,
E105, E106, E107. Updated Summary Table of Changes. Updated the
name of the Sofftware Developer Manuals.
December 2005
-056 Added Erratum E108 January 2007
-057 Updated Summary Table of Changes. May 2007
-058 Added Erratum E109. Updated Summary Table of Changes. August 2007
-059 Updated Summary Table of Changes. April 2008
-060 Updated Summary Table of Changes. August 2008
§

Preface
8Specification Update
Preface
This document is an update to the specifications contained in the documents listed in
the following Affected Documents/Related Documents table. It is a compilation of
device and document errata and specification clarifications and changes, and is
intended for hardware system manufacturers and for software developers of
applications, operating system, and tools.
Information types defined in the Nomenclature section of this document are
consolidated into this update document and are no longer published in other
documents. This document may also contain information that has not been previously
published.
Affected Documents
Document Title Document
Number/Location
Pentium®III Processor for the SC242 at 450 MHz to 1.13 GHz datasheet
Pentium® III Processor for the PGA370 Socket up to 1.13 GHz
datasheet
244452
245264
Related Documents
Document Title Document
Number/Location
Intel Architecture Software Developer’s Manual, Volumes 1, 2a, 2b, 3a
and 3b
253665, 253666,
253667, 253668,
253669
Nomenclature
Errata are design defects or errors. Errata may cause the Pentium III behavior to
deviate from published specifications. Hardware and software designed to be used
with any given stepping must assume that all errata documented for that stepping
are present on all devices.
Specification Changes are modifications to the current published specifications.
These changes will be incorporated in the next release of the specifications.
Specification Clarifications describe a specification in greater detail or further
highlight a specification’s impact to a complex design situation. These clarifications
will be incorporated in the next release of the specifications.

Preface
Specification Update 9
Documentation Changes include typos, errors, or omissions from the current
published specifications. These changes will be incorporated in the next release of the
specifications.
Note: Errata remain in the specification update throughout the product’s lifecycle, or until a
particular stepping is no longer commercially available. Under these circumstances,
errata removed from the specification update are archived and available upon
request. Specification changes, specification clarifications and documentation
changes are removed from the specification update when the appropriate changes
are made to the appropriate product specification or user documentation
(datasheets, manuals, etc.).
§

Summary Tables of Changes
10 Specification Update
Summary Tables of Changes
The following table indicates the Specification Changes, Errata, Specification
Clarifications or Documentation Changes, which apply to the listed MCH steppings.
Intel intends to fix some of the errata in a future stepping of the component, and to
account for the other outstanding issues through documentation or Specification
Changes as noted. This table uses the following notations:
Codes Used in Summary Table
Stepping
X: Erratum, Specification Change or Clarification that applies
to this stepping.
(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification
change does not apply to listed stepping.
Status
Doc: Document change or update that will be implemented.
PlanFix: This erratum may be fixed in a future stepping of the
product.
Fixed: This erratum has been previously fixed.
NoFix: There are no plans to fix this erratum.
Row
Shaded: This item is either new or modified from the previous
version of the document.
Each Specification Update item is prefixed with a capital letter to distinguish the
product. The key below details the letters that are used in Intel’s microprocessor
Specification Updates:
A = Dual-Core Intel® Xeon® processor 7000 sequence
C = Intel® Celeron® processor

Summary Tables of Changes
Specification Update 11
D = Dual-Core Intel® Xeon® processor 2.80 GHz
E = Intel® Pentium® III processor
F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D
processor
I = Dual-Core Intel® Xeon® processor 5000 series
J = 64-bit Intel® Xeon® processor MP with 1MB L2 cache
K = Mobile Intel® Pentium® III processor
L = Intel® Celeron® D processor
M = Mobile Intel® Celeron® processor
N = Intel® Pentium® 4 processor
O = Intel® Xeon® processor MP
P = Intel ® Xeon® processor
Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading technology
on 90-nm process technology
R = Intel® Pentium® 4 processor on 90 nm process
S = 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2
cache versions)
T = Mobile Intel® Pentium® 4 processor-M
U = 64-bit Intel® Xeon® processor MP with up to 8MB L3 cache
V = Mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA
package
W= Intel® Celeron® M processor
X = Intel® Pentium® M processor on 90nm process with 2-MB L2 cache and
Intel® processor A100 and A110 with 512-KB L2 cache
Y = Intel® Pentium® M processor
Z = Mobile Intel® Pentium® 4 processor with 533 MHz system bus
AA = Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor
Extreme Edition 955, 965
AB = Intel® Pentium® 4 processor 6x1 sequence
AC = Intel(R) Celeron(R) processor in 478 pin package
AD = Intel(R) Celeron(R) D processor on 65nm process
AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65nm
process
AF = Dual-Core Intel® Xeon® processor LV
AG = Dual-Core Intel® Xeon® processor 5100 series
AH = Intel® Core™2 Duo/Solo processor for Intel® Centrino® Duo processor
technology

Summary Tables of Changes
12 Specification Update
AI = Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop
processor E6000 and E4000 sequence
AJ = Quad-Core Intel® Xeon® processor 5300 series
AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel®
Core™2 Quad processor Q6000 sequence
AL = Dual-Core Intel® Xeon® processor 7100 series
AM = Intel® Celeron® processor 400 sequence
AN = Intel® Pentium® dual-core processor
AO = Quad-Core Intel® Xeon® processor 3200 series
AP = Dual-Core Intel® Xeon® processor 3000 series
AQ = Intel® Pentium® dual-core desktop processor E2000 sequence
AR = Intel® Celeron® processor 500 series
AS = Intel® Xeon® processor 7200, 7300 series
AT = Intel® Celeron® processor 200 series
AU = Intel® Celeron® Dual Core processor T1400
AV = Intel® Core™2 Extreme processor QX9650 and Intel® Core™2 Quad
processor Q9000 series
AW = Intel® Core™ 2 Duo processor E8000 series
AX = Quad-Core Intel® Xeon® processor 5400 series
AY= Dual-Core Intel® Xeon® processor 5200 series
AZ = Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45-
nm Process
AAA = Quad-Core Intel® Xeon® processor 3300 series
AAB = Dual-Core Intel® Xeon® E3110 Processor
AAC = Intel® Celeron® dual-core processor E1000 series
AAD = Intel® Core™2 Extreme Processor QX9775Δ
AAE = Intel® Atom™ processor Z5xx series
AAF = Intel® Atom™ processor 200 series
AAG = Intel® Atom™ processor N series
The Specification Updates for the Pentium processor, Pentium®Pro processor, and
other Intel products do not use this convention.
NO. kB 0 kC 0 cA 2 cB 0 cC 0 cD 0 tA 1 tB 1 Plans ERRATA
E1 X X X X X X X X NoFix
FP data operand pointer may be incorrectly
calculated after FP access which wraps
64-Kbyte boundary in 16-bit code

Summary Tables of Changes
Specification Update 13
NO. kB 0 kC 0 cA 2 cB 0 cC 0 cD 0 tA 1 tB 1 Plans ERRATA
E2 X X X X X X X X NoFix
Differences exist in debug exception
reporting
E3 X X X X X X X X NoFix
FLUSH# servicing delayed while waiting for
STARTUP_IPI in 2-way MP systems
E4 X X X X X X X X NoFix
Code fetch matching disabled debug register
may cause debug exception
E5 X X X X X X X X NoFix
Double ECC error on read may result in
BINIT#
E6 X X X X X X X X NoFix
FP inexact-result exception flag may not be
set
E7 X X X X X X X X NoFix BTM for SMI will contain incorrect FROM EIP
E8 X X X X X X X X NoFix
I/O restart in SMM may fail after
simultaneous MCE
E9 X X X X X X X X NoFix
Branch traps do not function if BTMs are also
enabled
E10 X X Fixed
Checker BIST failure in FRC mode not
signaled
E11 X X Fixed
BINIT# assertion causes FRCERR assertion in
FRC mode
E12 X X X X X X X X NoFix
Machine check exception handler may not
always execute successfully
E13 X X X X X X X X NoFix
MCE due to L2 parity error gives L1
MCACOD.LL
E14 X X X X X X X X NoFix LBER may be corrupted after some events
E15 X X X X X X X X NoFix
BTMs may be corrupted during simultaneous
L1 cache line replacement
E16 X X X X X X X X NoFix
EFLAGS discrepancy on a page fault after a
multiprocessor TLB shootdown
E17 X X X X X X X X NoFix
Near CALL to ESP creates unexpected EIP
address
E18 X X X X X X X X NoFix
Memory type undefined for nonmemory
operations
E19 X X Fixed
Infinite snoop stall during L2 initialization of
MP systems
E20 X X X X X X X X NoFix
FP data operand pointer may not be zero
after power on or Reset
E21 X X X X X X X X NoFix
MOVD following zeroing instruction can cause
incorrect result
E22 X X X X X X X X NoFix
Premature execution of a load operation
prior to exception handler invocation
E23 X X X X X X X X NoFix
Read portion of RMW instruction may
execute twice

Summary Tables of Changes
14 Specification Update
NO. kB 0 kC 0 cA 2 cB 0 cC 0 cD 0 tA 1 tB 1 Plans ERRATA
E24 X X X X X X X X NoFix
MC2_STATUS MSR has model-specific error
code and machine check architecture error
code reversed
E25 X X X X X X X X NoFix
Mixed cacheability of lock variables is
problematic in MP systems
E26 X X X X X X X X NoFix
MOV with debug register causes debug
exception
E27 X X X X X X X X NoFix
Upper four PAT entries not usable with Mode
B or Mode C paging
E28 X X X X X X X X NoFix
Data breakpoint exception in a displacement
relative near call may corrupt EIP
E29 X X X X X X X X NoFix
RDMSR and WRMSR to invalid MSR may not
cause GP fault
E30 X X X X X X X X NoFix
SYSENTER/SYSEXIT instructions can
implicitly load null segment selector to SS
and CS registers
E31 X X X X X X X X NoFix
PRELOAD followed by EXTEST does not load
boundary scan data
E32 X X Fixed
Far jump to new TSS with D-bit cleared may
cause system hang
E33 X X X X X X X X NoFix
INT 1 instruction handler execution could
generate a debug exception
E34 X Fixed
COMISS/UCOMISS may not update EFLAGS
under certain conditions
E35 X Fixed Transmission error on cache read
E36 X X X X X X X X NoFix
Potential loss of data coherency during MP
data ownership transfer
E37 X X X X X X X X NoFix
Misaligned Locked access to APIC space
results in hang
E38 X X Fixed
Floating-point exception signal may be
deferred
E39 X X X X X X X X NoFix
Memory ordering based synchronization may
cause a livelock condition in mp systems
E40 X Fixed
System bus address parity generator may
report false AERR#
E41 X X X X X X X X NoFix System bus ECC not functional with 2:1 ratio
E42 X X X X X X X X NoFix
Processor may assert DRDY# on a write with
no data
E43 X X X X X X X X NoFix
GP# fault on WRMSR to
ROB_CR_BKUPTMPDR6
E44 X X X X Fixed
Machine check exception may occur due to
improper line eviction in the IFU

Summary Tables of Changes
Specification Update 15
NO. kB 0 kC 0 cA 2 cB 0 cC 0 cD 0 tA 1 tB 1 Plans ERRATA
E45 X X X Fixed
Performance counters include Streaming
SIMD Extensions L1 prefetch
E46 X X X X X Fixed Snoop request may cause DBSY# hang
E47 X X X X X X X X NoFix
Lower bits of SMRAM SMBASE register
cannot be written with an ITP
E48 X X X Fixed
Task Switch May Cause Wrong PTE and PDE
Access Bit to be Set
E49 X X X X X X X X NoFix
Unsynchronized Cross-Modifying code
operations can cause unexpected instruction
execution results
E50 X Fixed
Processor will erroneously report a BIST
failure
E51 X Fixed Noise sensitivity issue on processor SMI# pin
E52 X Fixed
Limitation on cache line ECC detection and
correction
E53 X Fixed
L2_LD and L2_M_LINES_OUTM performance-
monitoring counters do not work
E54 X Fixed IFU/DCU deadlock may cause system hang
E55 X Fixed
L2_DBUS_BUSY performance monitoring
counter will not count writes
E56 X X Fixed
Incorrect sign may occur on X87 result due
to indefinite QNaN result from streaming
SIMD extensions multiply
E57 X X X X Fixed
Deadlock may occur due to illegal-
instruction/page-miss combination
E58 X X X X Fixed
MASKMOVQ instruction interaction with
string operation may cause deadlock
E59 X X X X X X X X NoFix
MOVD, CVTSI2SS, or PINSRW Following
Zeroing Instruction Can Cause Incorrect
Result
E60 X X X X X X X X NoFix
FLUSH# assertion following STPCLK# may
prevent CPU clocks from stopping
E61 X Fixed
Intermittent failure to assert ADS# during
processor power-on
E62 X X X X X X Fixed
Floating-point exception condition may be
deferred
E63 X Fixed
THERMTRIP# may not be asserted as
specified
E64 X X Fixed
Cache line reads may result in eviction of
invalid data.
E65 X X X X X X X X NoFix
Snoop probe during FLUSH# could cause L2
to be left in shared state

Summary Tables of Changes
16 Specification Update
NO. kB 0 kC 0 cA 2 cB 0 cC 0 cD 0 tA 1 tB 1 Plans ERRATA
E66 X X X X Fixed Livelock may occur due to IFU line eviction
E67 X X X X Fixed
Selector for the LTR/LLDT register may get
corrupted
E68 X X X X X X X X NoFix INIT does not clear global entries in the TLB
E69 X X X X X X X X NoFix VM bit will be cleared on a double fault
handler
E70 X X X X X X X X NoFix Memory aliasing with inconsistent A and D
bits may cause processor deadlock
E71 X X X X X X X X NoFix
Use of memory aliasing with inconsistent
memory type may cause system hang
E72 X X X X X X X X NoFix
Processor may report invalid TSS fault
instead of Double fault during mode C
paging
E73 X X X X X X X X NoFix
Machine check exception may occur when
interleaving code between different memory
types
E74 X X X X X X X X NoFix
Wrong ESP register values during a fault in
VM86 mode
E75 X X X X X X X X NoFix
APIC ICR write may cause interrupt not to be
sent when ICR delivery bit pending
E76 X Fixed
High temperature and low supply voltage
operation may result in incorrect processor
operation
E77 X X X X X X X X PlanFix
During Boundary Scan, BCLK not Sampled
High When SLP# is Asserted Low
E78 X X X X X X X NoFix Incorrect assertion of THERMTRIP# Signal
E79 X NoFix
Processor might not exit Sleep State
properly upon de-assertion of CPUSLP#
signal
E80 X X X X X X X1Fixed
The Instruction Fetch Unit (IFU) may fetch
instructions based upon stale CR3 data after
a write to CR3 register
E81 X X X X X X X X NoFix
Under Some Complex Conditions, the
Instructions in the Shadow of a JMP FAR may
be Unintentionally Executed and Retired
E82 X X X X X X X X NoFix
Processor Does not Flag #GP on Non-zero
Write to Certain MSRs
E83 X X X X X X X X NoFix IFU/BSU Deadlock May Cause System Hang
E84
X X X X X X X X NoFix REP MOVS Operation in Fast string Mode
Continues in that Mode When Crossing into a
Page with a Different Memory Type

Summary Tables of Changes
Specification Update 17
NO. kB 0 kC 0 cA 2 cB 0 cC 0 cD 0 tA 1 tB 1 Plans ERRATA
E85
X X X X X X X X NoFix The FXSAVE, STOS, MOVS Instructions May
Cause a Store Ordering Violation When Data
Crosses a Page with a UC Memory Type
E86 X X X X X X X X NoFix
POPF and POPFD Instructions that Set the
Trap Flag Bit May Cause Unpredictable
Processor Behavior
E87 X X X X X X X X NoFix
Code Segment Limit Violation May Occur on
4 Gbyte Limit Check
E88 X X X X X X X X NoFix
FST Instruction with Numeric and Null
Segment Exceptions May Cause General
Protection Faults to be Missed and FP Linear
Address (FLA) Mismatch
E89 X X X X X X X X NoFix
Code Segment is Wrong on SMM Handler
when SMBASE is not Aligned
E90 X X X X X X X X NoFix
Page with PAT (Page Attribute Table) Set to
USWC (Uncacheable Speculative Write
Combine) While Associated MTRR (Memory
Type Range Register) is UC (Uncacheable)
May Consolidate to UC
E91 X X X X X X X X NoFix
Under Certain Conditions LTR (Load Task
Register) Instruction May Result in System
Hang
E92 X X X X X X X X NoFix
Loading from Memory Type USWC
(Uncacheable Speculative Write Combine)
May Get Its Data Internally Forwarded From
a Previous Pending Store
E93 X X X X X X X X NoFix
FXSAVE after FNINIT Without an Intervening
FP (Floating Point) Instruction May Save
Uninitialized Values for FDP (x87 FPU
Instruction Operand (Data) Pointer Offset)
and FDS (x87 FPU Instruction Operand
(Data) Pointer Selector)
E94 X X X X X X X X NoFix
FSTP (Floating Point Store) Instruction Under
Certain Conditions May Result In Erroneously
Setting a Valid Bit on an FP (Floating Point)
Stack Register
E95 X X X X X X X X NoFix
Invalid Entries in Page-Directory-Pointer-
Table-Register (PDPTR) May Cause General
Protection (#GP) Exception if the Reserved
Bits are Set to One
E96 X X X X X X X X NoFix
Writing the Local Vector Table (LVT)
when an Interrupt is Pending May Cause an
Unexpected Interrupt
E97 X X X X X X X X NoFix
The Processor May Report a #TS Instead of
a #GP Fault
E98 X X X X X X X X NoFix
A Write to an APIC Register Sometimes May
Appear to Have Not Occurred

Summary Tables of Changes
18 Specification Update
NO. kB 0 kC 0 cA 2 cB 0 cC 0 cD 0 tA 1 tB 1 Plans ERRATA
E99 X X X X X X X X NoFix
Using 2M/4M Pages When A20M# Is
Asserted May Result in Incorrect Address
Translations
E100 X X X X X X X X NoFix
Values for LBR/BTS/BTM will be Incorrect
after an Exit from SMM
E101 X X X X X X X X NoFix INIT Does Not Clear Global Entries in the TLB
E102 X X X X X X X X NoFix
REP MOVS/STOS Executing with Fast Strings
Enabled and Crossing Page Boundaries with
Inconsistent Memory Types may use an
Incorrect Data Size or Lead to Memory-
Ordering Violations
E103 X X X X X X X X NoFix
The BS Flag in DR6 May be Set for Non-
Single-Step #DB Exception
E104 X X X X X X X X NoFix
Fault on ENTER Instruction May Result in
Unexpected Values on Stack Frame
E105 X X X X X X X X NoFix
Unaligned Accesses to Paging Structures May
Cause the Processor to Hang
E106 X X X X X X X X NoFix
INVLPG Operation for Large (2M/4M) Pages
May be Incomplete under Certain Conditions
E107 X X X X X X X X NoFix
Page Access Bit May be Set Prior to
Signaling a Code Segment Limit Fault
E108 X X X X X X X X NoFix
EFLAGS, CR0, CR4 and the EXF4 Signal May
be Incorrect after Shutdown
E109 X X X X X X X X NoFix
Performance Monitoring Event
FP_MMX_TRANS_TO_MMX May Not Count
Some Transitions
* Fix will be only on Pentium® III processors with CPUID=068xh and not
CPUID=067xh
Notes:
1- For these steppings, this erratum may be worked around in BIOS.
Number SPECIFICATION CHANGES
There are no Specification Changes in this revision of the Specification Update.
Number SPECIFICATION CLARIFICATIONS
E1 Specification clarification with respect to time stamp counter.

Summary Tables of Changes
Specification Update 19
Number DOCUMENTATION CHANGES
There are no Documentation Chnages in this revision of the Specification Update
§

Identification Information
20 Specification Update
Identification Information
Component Identification via Programming Interface
The Pentium®III processor can be identified by the following values:
Family1Model2 Brand ID3
0110 0111 00h = Not Supported
0110 1000 02h = "Intel®Pentium®III
Processor"
NOTES:
1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of
the EAX register after the CPUID instruction is executed with a 1 in the EAX register,
and the generation field of the Device ID register accessible through Boundary Scan.
2. The Model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the
EAX register after the CPUID instruction is executed with a 1 in the EAX register, and
the model field of the Device ID register accessible through Boundary Scan.
3. The Brand ID corresponds to bits [7:0] of the EBX register after the CPUID instruction is
executed with a 1 in the EAX register.
The Pentium III processor’s second level (L2) cache size can be determined by the
following register contents:
512-Kbyte Unified L2 Cache143h
256-Kbyte 8 way set associative
32byte line size, L2 Cache182h
512-Kbyte 8 way set associative
32byte line size, L2 Cache183h
NOTES:
1. For the Pentium III processor, the unified L2 cache size corresponds to a token in the
EDX register after the CPUID instruction is executed with a 2 in the EAX register. Other
Intel microprocessor models or families may move this information to other bit positions
or otherwise reformat the result returned by this instruction; generic code should parse
the resulting token stream according to the definition of the CPUID instruction.