Intel E5420 - CPU XEON QUAD CORE 2.50GHZ FSB1333MHZ 12M LGA771 HALOGEN FREE... User manual

Document Number: 318585-019
Intel® Xeon® Processor 5400 Series
Specification Update
December 2010

2Intel® Xeon® Processor 5400 Series
SpecificationUpdate
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different processor families. See http://www.intel.com/products/processor_number for details.
The Intel® Xeon® Processor 5400 Series may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
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Copyright © 2007-2010, Intel Corporation. All Rights Reserved.

3Intel® Xeon® Processor 5400 Series
SpecificationUpdate
Content
Revision History...............................................................................................................5
Preface..............................................................................................................................6
Summary Tables of Changes..........................................................................................8
Identification Information..............................................................................................15
Errata...............................................................................................................................18
Specification Changes...................................................................................................41
Specification Clarifications...........................................................................................42
Documentation Changes...............................................................................................43
§

Intel® Xeon® Processor 5400 Series 4
Specification Update

5Intel® Xeon® Processor 5400 Series
SpecificationUpdate
Revision History
Revision Description Date
-001 Initial Release - HTN_Public November 2007
-002 Added Errata AX43 through AX50
Updated Erratum AX26 December 2007
-003 Updated Erratum AX18
Added Erratum AX51 January 2008
-004 Added Erratum AX52 January 2008
-005 Added Erratum AX53 and AX54 February 2008
-006 Updated Table 1 to support L5408 March 2008
-007 Added L5410 and L5420 to Table 1
Added Specification Clairification on TLB April 2008
-008 Added Erratum AX55-AX57 May 2008
-009 Added Erratum AX58 June 2008
-010
Added Erratum AX59-AX64
Updated Table 1 for E-step Processor samples
Updated C & E step microcode
Updated notes in Table 1. Added Tcontrol Enabling Range and
removed actual Tcontrol values
July 2008
-011 Added Erratum AX65 and AX66 August 2008
-012 Added Erratum AX67-AX70
Added Production E-step S-spec numbers to Table 1 October 2008
-013 Added Erratum AX71
Added Production E-step S-spec numbers to Table 1 November 2008
-014 Updated Erratum AX68
Added Erratum AX72 December 2008
-015 Updated Erratum AX1 February 2009
-016 No changes....released to keep in sync with other related
documents. May 2009
-017 Added Erratum AX73 June 2009
-018 No changes....released to keep in sync with other related
documents. December 2010
-019 Added Erratum AX74-AX76 December 2010

Intel® Xeon® Processor 5400 Series 6
Specification Update
Preface
This document is an update to the specifications contained in the Affected Documents
table below. This document is a compilation of device and documentation errata,
specification clarifications and changes. It is intended for hardware system
manufacturers and software developers of applications, operating systems, or tools.
Information types defined in Nomenclature are consolidated into the specification
update and are no longer published in other documents.
This document may also contain information that was not previously published.
Affected Documents
Related Documents
Document Title Document Number/
Location
Intel® Xeon® Processor 5400 Series Datasheet 318589
Document Title Document Number/
Location
AP-485, Intel® Processor Identification and the CPUID Instruction http://www.intel.com/
design/processor/
applnots/241618.htm
Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1: Basic Architecture
Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A: Instruction Set Reference Manual A-M
Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2B: Instruction Set Reference Manual N-Z
Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3A: System Programming Guide
Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3B: System Programming Guide
Intel® 64 and IA-32 Intel Architecture Optimization Reference
Manual
http://www.intel.com/
products/processor/
manuals/index.htm
Intel® 64 and IA-32 Architectures Software Developer’s Manual
Documentation Changes http://www.intel.com/
design/processor/
specupdt/252046.htm

7Intel® Xeon® Processor 5400 Series
SpecificationUpdate
Nomenclature
Errata are design defects or errors. These may cause the Intel® Xeon® Processor
5400 Series behavior to deviate from published specifications. Hardware and software
designed to be used with any given stepping must assume that all errata documented
for that stepping are present on all devices.
S-Spec Number is a five-digit code used to identify products. Products are
differentiated by their unique characteristics,e.g., core speed, L2 cache size, package
type, etc. as described in the processor identification information table. Read all notes
associated with each S-Spec number.
Specification Changes are modifications to the current published specifications.
These changes will be incorporated in any new release of the specification.
Specification Clarifications describe a specification in greater detail or further
highlight a specification’s impact to a complex design situation. These clarifications will
be incorporated in any new release of the specification.
Documentation Changes include typos, errors, or omissions from the current
published specifications. These will be incorporated in any new release of the
specification.
Note: Errata remain in the specification update throughout the product’s lifecycle, or until a
particular stepping is no longer commercially available. Under these circumstances,
errata removed from the specification update are archived and available upon request.
Specification changes, specification clarifications and documentation changes are
removed from the specification update when the appropriate changes are made to the
appropriate product specification or user documentation (datasheets, manuals, and so
forth).

Intel® Xeon® Processor 5400 Series 8
Specification Update
Summary Tables of Changes
The following tables indicate the errata, specification changes, specification
clarifications, or documentation changes which apply to the Intel® Xeon® Processor
5400 Series product. Intel may fix some of the errata in a future stepping of the
component, and account for the other outstanding issues through documentation or
specification changes as noted. These tables uses the following notations:
Codes Used in Summary Tables
Stepping
X: Errata exists in the stepping indicated. Specification Change or
Clarification that applies to this stepping.
(No mark)
or (Blank box): This erratum is fixed in listed stepping or specification change
does not apply to listed stepping.
Page
(Page): Page location of item in this document.
Status
Doc: Document change or update will be implemented.
Plan Fix: This erratum may be fixed in a future stepping of the product.
Fixed: This erratum has been previously fixed.
No Fix: There are no plans to fix this erratum.
Row
Change bar to left of table row indicates this erratum is either new or modified from the
previous version of the document.
Each Specification Update item is prefixed with a capital letter to distinguish the
product. The key below details the letters that are used in Intel’s microprocessor
Specification Updates:
A = Intel® Xeon® processor 7000 sequence
C = Intel® Celeron® processor
D = Intel® Xeon® processor 2.80 GHz
E = Intel® Pentium® III processor
F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor
I = Intel® Xeon® processor 5000 series
J = 64-bit Intel® Xeon® processor MP with 1MB L2 cache
K = Mobile Intel® Pentium® III processor

9Intel® Xeon® Processor 5400 Series
SpecificationUpdate
L = Intel® Celeron® D processor
M = Mobile Intel® Celeron® processor
N = Intel® Pentium® 4 processor
O = Intel® Xeon® processor MP
P = Intel ® Xeon® processor
Q = Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading Technology
(Intel® HT Technology) on 90-nm process technology
R = Intel® Pentium® 4 processor on 90 nm process
S = 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache
versions)
T = Mobile Intel® Pentium® 4 processor-M
U = 64-bit Intel® Xeon® processor MP with up to 8 MB L3 cache
V = Mobile Intel® Celeron® processor on.13 micron process in Micro-FCPGA package
W= Intel® Celeron® M processor
X = Intel® Pentium® M processor on 90 nm process with 2-MB L2 cache and Intel®
processor A100 and A110 with 512-KB L2 cache
Y = Intel® Pentium® M processor
Z = Mobile Intel® Pentium® 4 processor with 533 MHz system bus
AA = Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor Extreme
Edition 955, 965
AB = Intel® Pentium® 4 processor 6x1 sequence
AC = Intel® Celeron® processor in 478 pin package
AD = Intel® Celeron® D processor on 65nm_process
AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65 nm process
AF = Intel® Xeon® processor LV
AG = Intel® Xeon® processor 5100 series
AH = Intel® Core™2 Duo/Solo Processor for Intel® Centrino® Duo Processor Technology
AI = Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor
E6000 and E4000 sequence
AJ = Intel® Xeon® processor 5300 series
AK = Intel® Core™2 Extreme processor QX6000 sequence and Intel® Core™2 processor
Q6000 sequence
AL = Intel® Xeon® processor 7100 series
AM = Intel® Celeron® processor 400 sequence
AN = Intel® Pentium® processor
AO = Intel® Xeon® processor 3200 series
AP = Intel® Xeon® processor 3000 series
AQ = Intel® Pentium® desktop processor E2000 sequence
AR = Intel® Celeron processor 500 series
AS = Intel® Xeon® processor 7200, 7300 series

Intel® Xeon® Processor 5400 Series 10
Specification Update
AT = Intel® Celeron® processor 200 series
AV = Intel® Core™2 Extreme Processor QX9650 Sequence and Intel® Core™2 Processor
Q9000 Sequence processor
AW = Intel® Core™ 2 Duo processor E8000 series
AX = Intel® Xeon® Processor 5400 Series
AY = Intel® Xeon® Processor 5200 Series
AZ= Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45-nm
Process
AAA= Intel® Xeon® processor 3300 series
AAB= Intel® Xeon® E3110 Processor
AAC= Intel® Celeron® processor E1000 series
AAD= Intel® Core™ 2 extreme Processor OX9775
AAE= Intel® Atom™ Processor Z5xx series
AAF= Intel® Atom™ Processor 200 series
AAG= Intel® Atom™ Processor N series
AAH= Intel® Atom™ Processor 300 series
AAI= Intel® Xeon® Processor 7400 Series

11 Intel® Xeon® Processor 5400 Series
SpecificationUpdate
Errata Intel®Xeon®Processor 5400 Series (Sheet 1 of 3)
Number Stepping Stepping Status (Hardware
Fix?) ERRATA
C-0 E-0
AX1 XXNoFixEFLAGS Discrepancy on Page Faults After a Translation Change
AX2 XXNoFix
INVLPG Operation for Large (2M/4M) Pages May be Incomplete under Certain
Conditions
AX3 XXNoFix
Store to WT Memory Data May be Seen in Wrong Order by Two Subsequent
Loads
AX4 XXNoFixNon-Temporal Data Store May be Observed in Wrong Program Order
AX5 XXNoFixPage Access Bit May be Set Prior to Signaling a Code Segment Limit Fault
AX6 XXNoFix
Updating Code Page Directory Attributes without TLB Invalidation May Result
in Improper Handling of Code #PF
AX7 XXNoFixStorage of PEBS Record Delayed Following Execution of MOV SS or STI
AX8 XXNoFix
Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count
Some Transitions
AX9 XXNoFix
A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent
Triggering of the Monitoring Hardware
AX10 XXNoFixPerformance Monitoring Event MISALIGN_MEM_REF May Over Count
AX11 XXNoFixThe Processor May Report a #TS Instead of a #GP Fault
AX12 XXNoFixCode Segment Limit Violation May Occur on 4 Gigabyte Limit Check
AX13 XXNoFixA Write to an APIC Register Sometimes May Appear to Have Not Occurred
AX14 XXNoFixLast Branch Records (LBR) Updates May be Incorrect after a Task Switch
AX15 XXNoFix
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page
Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or
Lead to Memory-Ordering Violations.
AX16 XXNoFix
Upper 32 bits of 'From' Address Reported through BTMs or BTSs May be
Incorrect
AX17 XXNoFix
Address Reported by Machine-Check Architecture (MCA) on Single-bit L2
ECC Errors May be Incorrect
AX18 XXNoFix
Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher
Priority Interrupts/Exceptions and May Push the Wrong Address Onto the
Stack
AX19 XXNoFixStore Ordering May be Incorrect between WC and WP Memory Type
AX20 XXNoFixEFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after Shutdown
AX21 XXNoFix
Premature Execution of a Load Operation Prior to Exception Handler
Invocation
AX22 XXNoFix
Performance Monitoring Events for Retired Instructions (C0H) May Not Be
Accurate
AX23 XXNoFix
Returning to Real Mode from SMM with EFLAGS.VM Set May Result in
Unpredictable System Behavior
AX24 XXNoFix
CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal to 248
May Terminate Early
AX25 XXNoFix
Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause
an Unexpected Interrupt

Intel® Xeon® Processor 5400 Series 12
Specification Update
AX26 XXNoFix
Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced Before
Higher Priority Interrupts
AX27 XXNoFix
VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last
Exception Record (LER) MSR
AX28 XXNoFixINIT Does Not Clear Global Entries in the TLB
AX29 XXNoFixSplit Locked Stores May not Trigger the Monitoring Hardware
AX30 XXNoFix
Programming the Digital Thermal Sensor (DTS) Threshold May Cause
Unexpected Thermal Interrupts
AX31 XXNoFix
Writing Shared Unaligned Data that Crosses a Cache Line without Proper
Semaphores or Barriers May Expose a Memory Ordering Issue
AX32 XXNoFix
General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit
Violation above 4-G Limit
AX33 XXNoFixAn Asynchronous MCE During a Far Transfer May Corrupt ESP
AX34 X X Plan Fix CPUID Reports Architectural Performance Monitoring Version 2 is Supported,
When Only Version 1 Capabilities are Available
AX35 XXNoFixB0-B3 Bits in DR6 May Not be Properly Cleared After Code Breakpoint
AX36 XXNoFix
An xTPR Update Transaction Cycle, if Enabled, May be Issued to the FSB after
the Processor has Issued a Stop-Grant Special Cycle
AX37 XFixed
Performance Monitoring Event IA32_FIXED_CTR2 May Not Function Properly
when Max Ratio is a Non-Integer Core-to-Bus Ratio
AX38 XXNoFixInstruction Fetch May Cause a Livelock During Snoops of the L1 Data Cache
AX39 XXNoFix
Use of Memory Aliasing with Inconsistent Memory Type may Cause a System
Hang or a Machine Check Exception
AX40 XXNoFix
A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to Memory-
Ordering Violations
AX41 XFixed
VM Exit with Exit Reason "TPR Below Threshold" Can Cause the Blocking by
MOV/POP SS and Blocking by STI Bits to be Cleared in the Guest
Interruptability-State Field
AX42 XXNoFix
Using Memory Type Aliasing with Cacheable and WC Memory Types May
Lead to Memory Ordering Violations
AX43 XXNoFix
VM Exit Caused by a SIPI Results in Zero Being Saved to the Guest RIP Field
in the VMCS
AX44 XFixedNMIs May Not Be Blocked by a VM-Entry Failure
AX45 XFixed
Partial Streaming Load Instruction Sequence May Cause the Processor to
Hang
AX46 XXNotFixed
Self/Cross Modifying Code May Not be Detected or May Cause a Machine
Check Exception
AX47 XFixed
Data TLB Eviction Condition in the Middle of a Cacheline Split Load Operation
May Cause the Processor to Hang
AX48 XFixed
Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits
without TLB Shootdown May Cause Unexpected Processor Behavior
AX49 XXFixed
RSM Instruction Execution under Certain Conditions May Cause Processor
Hang or Unexpected Instruction Execution Results
AX50 XXNoFixBenign Exception after a Double Fault May Not Cause a Triple Fault Shutdown
Errata Intel®Xeon®Processor 5400 Series (Sheet 2 of 3)
Number Stepping Stepping Status (Hardware
Fix?) ERRATA
C-0 E-0

13 Intel® Xeon® Processor 5400 Series
SpecificationUpdate
AX51 XXNoFixLER MSRs May be Incorrectly Updated
AX52 XXNoFix
Short Nested Loops That Span Multiple 16-Byte Boundaries May Cause a
Machine Check Exception or a System Hang
AX53 XXNoFix
IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check Error
Reporting Enable Correctly
AX54 XXNoFix
An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV
SS/POP SS Instruction if it is Followed by an Instruction That Signals a
Floating Point Exception
AX55 XXNoFix
A VM Exit Due to a Fault While Delivering a Software Interrupt May Save
Incorrect Data into the VMCS
AX56 XXNoFix
A VM Exit Occurring in IA-32e Mode May Not Produce a VMX Abort When
Expected
AX57 XXNoFix
IRET under Certain Conditions May Cause an Unexpected Alignment Check
Exception
AX58 XXNoFix
VM Entry May Fail When Attempting to Set
IA32_DEBUGCTL.FREEZE_WHILE_SMM_EN
AX59 XNoFixVM Entry May Use Wrong Address to Access Virtual-APIC Page
AX60 XNoFixINIT Incorrectly Resets IA32_LSTAR MSR
AX61 XNoFixCPUID Instruction May Return Incorrect Brand String
AX62 XXNoFix
Global Instruction TLB Entries May Not be Invalidated on a VM Exit or VM
Entry
AX63 XNoFixXRSTOR Instruction May Cause Extra Memory Reads
AX64 XNoFix
Enabling PECI via the PECI_CTL MSR Does Not Enable PECI and May
Corrupt the CPUID Feature Flags
AX65 XXNoFix
Corruption of CS Segment Register During RSM While Transitioning From
Real Mode to Protected Mode
AX66 XXNoFix
LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt
Occurs in 64-bit Mode
AX67 XNoFixThe XRSTOR Instruction May Fail to Cause a General-Protection Exception
AX68 XNoFix
The XSAVE Instruction May Erroneously Modify Reserved Bits in the
XSTATE_BV Field
AX69 XNoFixStore Ordering Violation When Using XSAVE
AX70 XXNoFixMemory Ordering Violation With Stores/Loads Crossing a Cacheline Boundary
AX71 XXNoFixB0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set
AX72 X X Plan Fix Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected
Instruction Execution Results
AX73 XXNoFix
A Page Fault May Not be Generated When the PS bit is set to “1” in a PML4E
or PDPTE
AX74 XXNoFixNot-Present Page Faults May Set the RSVD Flag in the Error Code
AX75 XXNoFixVM Exits Due to “NMI-Window Exiting” May Be Delayed by One Instruction
AX76 XXNoFixA 64-bit Register IP-relative Instruction May Return Unexpected Results
Errata Intel®Xeon®Processor 5400 Series (Sheet 3 of 3)
Number Stepping Stepping Status (Hardware
Fix?) ERRATA
C-0 E-0

Intel® Xeon® Processor 5400 Series 14
Specification Update
Specification Changes
Number SPECIFICATION CHANGES
None for this revision of this specification update.
Specification Clarifications
Number SPECIFICATION CLARIFICATIONS
AX1 Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation
Documentation Changes
Number DOCUMENTATION CHANGES
None for this revision of this specification update.

15 Intel® Xeon® Processor 5400 Series
SpecificationUpdate
Identification Information
Component Identification via Programming Interface
The Intel® Xeon® Processor 5400 Series stepping can be identified by the following
register contents:
When EAX is initialized to a value of 1, the CPUID instruction returns the Extended
Family, Extended Model, Type, Family, Model and Stepping value in the EAX register.
Note that the EDX processor signature value after reset is equivalent to the processor
signature output value in the EAX register.
Notes:
1. The Extended Family, bits [27:20] are used in conjunction with the Family Code, specified in bits [11:8],
to indicate whether the processor belongs to the Intel386, Intel486, Pentium, Pentium Pro, Pentium 4,
or Intel® Core™ processor family.
2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are
used to identify the model of the processor within the processor’s family.
3. The Processor Type, specified in bits [13:12] indicates whether the processor is an original OEM
processor, an OverDrive processor, or a dual processor (capable of being used in a dual processor
system).
4. The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX
register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of
the Device ID register accessible through Boundary Scan.
5. The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX
register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the
Device ID register accessible through Boundary Scan.
6. The Stepping ID in bits [3:0] indicates the revision number of that model. See Table 2 for the processor
stepping ID number in the CPUID information.
Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX
registers after the CPUID instruction is executed with a 2 in the EAX register.
Reserved Extended
Family1Extended
Model2Reserved Processor
Type3Family
Code4Model Number5Stepping ID6
31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0
0000000b 0001b 00b 0110b 0111b XXXXb

Intel® Xeon® Processor 5400 Series 16
Specification Update
Component Marking Information
Intel® Xeon® Processor 5400 Series stepping can be identified by the following
component markings:
Figure 1. Processor Top-side Markings (Example)
Table 1. Intel® Xeon® Processor 5400 Series Identification Information
(Sheet 1 of 2)
S-Spec Processor Number Core Stepping CPUID1Core
Freq
(GHz)
Data
Bus
Freq
(MHz)
L2
Cache
Size
(MB)
Thermal
Design
Power
(TDP)
Notes
SLANZ X5482 C-0 10676h 3.20 1600 12 (2x6MB) 150
SLANP X5460 C-0 10676h 3.16 1333 12 (2x6MB) 120
SLASA X5472 C-0 10676h 3 1600 12 (2x6MB) 120
SLASB X5450 C-0 10676h 3 1333 12 (2x6MB) 120
SLANR E5472 C-0 10676h 3 1600 12 (2x6MB) 80
SLANQ E5450 C-0 10676h 3 1333 12 (2x6MB) 80
SLANS E5440 C-0 10676h 2.83 1333 12 (2x6MB) 80
SLANT E5462 C-0 10676h 2.80 1600 12 (2x6MB) 80
SLANU E5430 C-0 10676h 2.66 1333 12 (2x6MB) 80
SLANV E5420 C-0 10676h 2.50 1333 12 (2x6MB) 80
SLANW E5410 C-0 10676h 2.33 1333 12 (2x6MB) 80
SLAP2 E5405 C-0 10676h 2 1333 12 (2x6MB) 80
SLAP5 L5408 C-0 10676h 2.13 1066 12 (2x6MB) 50
SLAP4 L5410 C-0 10676h 2.33 1333 12 (2x6MB) 50
SLARP L5420 C-0 10676h 2.50 1333 12 (2x6MB) 50
SLBBD X5492 E-0 1067Ah 3.40 1600 12 (2x6MB) 150
SLBBG X5482 E-0 1067Ah 3.20 1600 12 (2x6MB) 120
SLBBF X5470 E-0 1067Ah 3.33 1333 12 (2x6MB) 120
SLBBB X5472 E-0 1067Ah 3 1600 12 (2x6MB) 120
SLBBA X5460 E-0 1067Ah 3.16 1333 12 (2x6MB) 120
ATPO
S/N
ATPO
S/N
GROUP1LINE1
GROUP1LINE2
GROUP1LINE3
GROUP1LINE4
GROUP1LINE5
LOT NO
S/N
Legend:
GROUP1LINE1
GROUP1LINE2
GROUP1LINE3
GROUP1LINE4
GROUP1LINE5
Mark Text (Production Mark):
2.66GHz/12M/1333
Intel ® Xeon®
SXXX XXXXX
i (M) © ’07 x54XX
(FPO)

17 Intel® Xeon® Processor 5400 Series
SpecificationUpdate
Notes:
1. Processors in the QDF/S-Spec column that begin with a Q are for qualification only. PPS Samples.
2. E5405 does not support Intel SpeedStep® Technology. All others listed do support this technology.
SLBBE X5450 E-0 1067Ah 3 1333 12 (2x6MB) 120
SLBBH E5472 E-0 1067Ah 3 1600 12 (2x6MB) 80
SLBBM E5450 E-0 1067Ah 3 1333 12 (2x6MB) 80
SLBBN E5462 E-0 1067Ah 2.80 1600 12 (2x6MB) 80
SLBBJ E5440 E-0 1067Ah 2.83 1333 12 (2x6MB) 80
SLBBK E5430 E-0 1067Ah 2.66 1333 12 (2x6MB) 80
SLBBC E5410 E-0 1067Ah 2.33 1333 12 (2x6MB) 80
SLBBP E5405 E-0 1067Ah 2 1333 12 (2x6MB) 80
SLBBL E5420 E-0 1067Ah 2.50 1333 12 (2x6MB) 80
SLBBQ L5430 E-0 1067Ah 2.66 1333 12 (2x6MB) 50
SLBBR L5420 E-0 1067Ah 2.50 1333 12 (2x6MB) 50
SLBBS L5410 E-0 1067Ah 2.33 1333 12 (2x6MB) 50
SLBBT L5408 E-0 1067Ah 2.13 1066 12 (2x6MB) 40
Table 1. Intel® Xeon® Processor 5400 Series Identification Information
(Sheet 2 of 2)
S-Spec Processor Number Core Stepping CPUID1Core
Freq
(GHz)
Data
Bus
Freq
(MHz)
L2
Cache
Size
(MB)
Thermal
Design
Power
(TDP)
Notes

Intel® Xeon® Processor 5400 Series 18
Specification Update
Errata
AX1. EFLAGS Discrepancy on Page Fault After Translation Change
Problem: This erratum is regarding the case where paging structures are modified to change a
linear address from writable to non-writable without software performing an
appropriate TLB invalidation. When a subsequent access to that address by a specific
instruction (ADD, AND, BTC, BTR, BTS, CMPXCHG, DEC, INC, NEG, NOT, OR, ROL/ROR,
SAL/SAR/SHL/SHR, SHLD, SHRD, SUB, XOR, and XADD) causes a page fault, the value
saved for EFLAGS may incorrectly contain the arithmetic flag values that the EFLAGS
register would have held had the instruction completed without fault. This can occur
even if the fault causes a VM exit or if its delivery causes a nested fault.
Implication: None identified. Although the EFLAGS value saved may contain incorrect arithmetic flag
values, Intel has not identified software that is affected by this erratum. This erratum
will have no further effects once the original instruction is restarted because the
instruction will produce the same results as if it had initially completed without a page
fault.
Workaround: If the page fault handler inspects the arithmetic portion of the saved EFLAGS value,
then system software should perform a synchronized paging structure modification and
TLB invalidation.
Status: For the steppings affected, see the Summary Tables of Changes.
AX2. INVLPG Operation for Large (2M/4M) Pages May be Incomplete under
Certain Conditions
Problem: The INVLPG instruction may not completely invalidate Translation Look-aside Buffer
(TLB) entries for large pages (2M/4M) when both of the following conditions exist:
"Address range of the page being invalidated spans several Memory Type Range
Registers (MTRRs) with different memory types specified "INVLPG operation is
preceded by a Page Assist Event (Page Fault (#PF) or an access that results in either A
or D bits being set in a Page Table Entry (PTE)).
Implication: Stale translations may remain valid in TLB after a PTE update resulting in unpredictable
system behavior. Intel has not observed this erratum with any commercially available
software.
Workaround: Software should ensure that the memory type specified in the MTRRs is the same for
the entire address range of the large page.
Status: For the steppings affected, see the Summary Tables of Changes.
AX3. Store to WT Memory Data May be Seen in Wrong Order by Two
Subsequent Loads
Problem: When data of Store to WT memory is used by two subsequent loads of one thread and
another thread performs cacheable write to the same address the first load may get the
data from external memory or L2 written by another core, while the second load will
get the data straight from the WT Store.
Implication: Software that uses WB to WT memory aliasing may violate proper store ordering.
Workaround: Do not use WB to WT aliasing.
Status: For the steppings affected, see the Summary Tables of Changes.

19 Intel® Xeon® Processor 5400 Series
SpecificationUpdate
AX4. Non-Temporal Data Store May be Observed in Wrong Program Order
Problem: When non-temporal data is accessed by multiple read operations in one thread while
another thread performs a cacheable write operation to the same address, the data
stored may be observed in wrong program order (i.e. later load operations may read
older data).
Implication: Software that uses non-temporal data without proper serialization before accessing the
non-temporal data may observe data in wrong program order.
Workaround: Software that conforms to the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A, section "Buffering of Write Combining Memory Locations" will
operate correctly.
Status: For the steppings affected, see the Summary Tables of Changes.
AX5. Page Access Bit May be Set Prior to Signaling a Code Segment Limit
Fault
Problem: If code segment limit is set close to the end of a code page, then due to this erratum
the memory page Access bit (A bit) may be set for the subsequent page prior to
general protection fault on code segment limit.
Implication: When this erratum occurs, a non-accessed page which is present in memory and
follows a page that contains the code segment limit may be tagged as accessed.
Workaround: Erratum can be avoided by placing a guard page (non-present or non-executable page)
as the last page of the segment or after the page that includes the code segment limit.
Status: For the steppings affected, see the Summary Tables of Changes.
AX6. Updating Code Page Directory Attributes without TLB Invalidation May
Result in Improper Handling of Code #PF
Problem: Code #PF (Page Fault exception) is normally handled in lower priority order relative to
both code #DB (Debug Exception) and code Segment Limit Violation #GP (General
Protection Fault). Due to this erratum, code #PF may be handled incorrectly, if all of the
following conditions are met:
1. A PDE (Page Directory Entry) is modified without invalidating the corresponding
TLB (Translation Look-aside Buffer) entry
2. Code execution transitions to a different code page such that both
• The target linear address corresponds to the modified PDE
• The PTE (Page Table Entry) for the target linear address has an A
(Accessed) bit that is clear
3. One of the following simultaneous exception conditions is present following the
code transition
• Code #DB and code #PF
• Code Segment Limit Violation #GP and code #PF
Implication: Software may observe either incorrect processing of code #PF before code Segment
Limit Violation #GP or processing of code #PF in lieu of code #DB.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AX7. Storage of PEBS Record Delayed Following Execution of MOV SS or STI
Problem: When a performance monitoring counter is configured for PEBS (Precise Event Based
Sampling), overflow of the counter results in storage of a PEBS record in the PEBS

Intel® Xeon® Processor 5400 Series 20
Specification Update
buffer. The information in the PEBS record represents the state of the next instruction
to be executed following the counter overflow. Due to this erratum, if the counter
overflow occurs after execution of either MOV SS or STI, storage of the PEBS record is
delayed by one instruction.
Implication: When this erratum occurs, software may observe storage of the PEBS record being
delayed by one instruction following execution of MOV SS or STI. The state information
in the PEBS record will also reflect the one instruction delay.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AX8. Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
Problem: Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask 01H) counts
transitions from x87 Floating Point (FP) to MMX™ instructions. Due to this erratum, if
only a small number of MMX instructions (including EMMS) are executed immediately
after the last FP instruction, a FP to MMX transition may not be counted.
Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be
lower than expected. The degree of undercounting is dependent on the occurrences of
the erratum condition while the counter is active. Intel has not observed this erratum
with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AX9. A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent
Triggering of the Monitoring Hardware
Problem: The MONITOR instruction is used to arm the address monitoring hardware for the
subsequent MWAIT instruction. The hardware is triggered on subsequent memory store
operations to the monitored address range. Due to this erratum, REP STOS/MOVS fast
string operations to the monitored address range may prevent the actual triggering
store to be propagated to the monitoring hardware.
Implication: A logical processor executing an MWAIT instruction may not immediately continue
program execution if a REP STOS/MOVS targets the monitored address range.
Workaround: Software can avoid this erratum by not using REP STOS/MOVS store operations within
the monitored address range.
Status: For the steppings affected, see the Summary Tables of Changes.
AX10. Performance Monitoring Event MISALIGN_MEM_REF May Over Count
Problem: Performance monitoring event MISALIGN_MEM_REF (05H) is used to count the number
of memory accesses that cross an 8-byte boundary and are blocked until retirement.
Due to this erratum, the performance monitoring event MISALIGN_MEM_REF also
counts other memory accesses.
Implication: The performance monitoring event MISALIGN_MEM_REF may over count. The extent of
the over counting depends on the number of memory accesses retiring while the
counter is active.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.