Lattice Semiconductor LatticeECP3 Versa User manual

July 2013
Revision: EB62_01.6

LatticeECP3 Versa Evaluation Board

User’s Guide

2
LatticeECP3 Versa Evaluation Board
User’s Guide
Introduction
The LatticeECP3™ Versa Evaluation Board allows designers to investigate and experiment with the features of the
LatticeECP3 Field-Programmable Gate Array. The features of the LatticeECP3 Versa Evaluation Board can assist
engineers with rapid prototyping and testing of their specific designs. The LatticeECP3 Versa Evaluation Board is
part of the LatticeECP3 Versa Development Kit. The guide is intended to be referenced in conjunction with demo
user’s guides to demonstrate the LatticeECP3 FPGA.
Figure 1. LatticeECP3 Versa Evaluation Board, Top Side
User
Switches
Status LEDs
USB
Programming
J3 – JTAG
Interface J13 – JTAG
Interface
On-Board
Clock
Management
Expansion Connectors
DDR3
Memory
SERDES Test
SMA Connectors
LED
Display
GSRn &
PROGRAMn
Push-buttons
10/100/1000
RJ-45
Connections
PCI Express x1
SPI Flash
Configuration
Memory
12V DC
Power Input
Features
• Half-length PCI Express form-factor
– Allows demonstration of PCI Express x1 interconnection
• Electrical testing of one full-duplex SERDES channel via SMA connections
• USB-B connection for UART and device programming
• Two RJ45 interfaces to 10/100/1000 Ethernet to GMII
• On-board Boot Flash
– 64M Serial SPI Flash
• DDR3-1333 memory components (64Mb/x16)
• Expansion mezzanine interconnection for prototyping
• 14-segment alpha-numeric display
• Switches, LEDs and displays for demo purposes
• ispVM™ programming support
• On-board reference clock sources

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LatticeECP3 Versa Evaluation Board
User’s Guide
The contents of this user’s guide include top-level functional descriptions of the various portions of the evaluation
board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics.
Caution: The LatticeECP3 Versa Evaluation Board contains ESD-sensitive components. ESD safe practices should
be followed while handling and using the evaluation board.
LatticeECP3 Device
This board features a LatticeECP3 FPGA with a 1.2V core supply. It can accommodate all pin-compatible
LatticeECP3 devices in the 484-ball fpBGA (1mm pitch) package. A complete description of this device can be
found in the LatticeECP3 Family Data Sheet.
Note: The connections referenced in this document refer to the LFE3-35EA-8FN484C device.
Applying Power to the Board
The LatticeECP3 Versa Evaluation Board is ready to power on. The board can be supplied with power from a PCI
Express host system or standalone with an external wall power module.
The 12V DC input power source is fused with a surface mounted fuse, as noted in Ta ble 1.
Table 1. Board Power Supply Fuses – (See Appendix B, Figure 12)
Fuse Designator Description
F1 12V Input Supply Fuse
The board may be plugged into a host PC. Only plug the board into a PCI Express slot when the system is powered
off. Once inserted, the PC can be safely powered on.
Using the evaluation board outside of a PC chassis supply requires the factory-supplied wall supply module. Use of
other supplies is not suggested. GME Technology’s GFP181DA-1215B-1 (or equivalent) is provided with the
LatticeECP3 Versa Development Kit.
Figure 2. Power Distribution Scheme – (See Appendix B, Figure 12)
SW
3_3V, +3.3V, 1.35 A, Power Status LED D9
12_0V
(5A fused)
Power Status LED D13
EN
SW
SW 1_5V, +1.5V, 1.1 A, Power Status LED D11
EN
VCC_CORE, +1.2V, 1.35 A, Power Status LED D10
SW
LDO SERDES 1_2V, +1.2V, 1A, Power Status LED D12
EN
2_5V, +2.5V, 1.1 A, Power Status LED D31
Programming/FPGA Configuration
The LatticeECP3 Versa Evaluation Board has a built-in download controller for programming the LatticeECP3
FPGA. The built-in module consists of a USB Type-B connector and a USB UART device. To use the built-in down-
load cable, simply connect a standard USB cable (a USB-B to USB-A cable is included with the LatticeECP3 Versa
Development Kit) from J2 to your PC (with ispVM System software installed). The USB hub on the PC will detect
the addition of the USB function, making the built-in cable available for use with the ispVM System software. The
USB cable is connected in parallel to J3.

4
LatticeECP3 Versa Evaluation Board
User’s Guide
Alternate ispVM Download Interface
J3 is a 1x10 100mil header that is provided for use with an external Lattice download cable (available separately).
A USB download cable can be attached to the board using J3 to interface with the FPGA (U1).
Note: Resistors R38, R33, R32 and R36 need to be removed.
A separate header is provided to interface to a download cable for the ispClock™5406A clock device (U13). U13 is
not interfaced to the built-in download interface. U13 is factory-programmed for use with the reference designs and
should only be altered for customized designs.
A 10-pin JTAG connector is used in conjunction with the ispVM USB download cable to program and control the
device. A separate 10-pin header (J14) is provided for programming U13.
Table 2. ispVM JTAG Connector Pinout (J3 and J14) – (See Appendix B, Figure 5)
Pin Function Color
1PWR Red
2TDO Brown
3TDI Orange
4N/C —
5N/C —
6TMS Purple
7 GND Black
8TCK White
9N/C —
10 N/C —
ispVM Requirements
Note: An ispDOWNLOAD™ cable is included with Lattice Diamond®design software. This cable is not needed for
the typical use of this board since it includes the built-in download module and only requires the USB cable
included with the board. Standalone ispVM download cables may be purchased separately from Lattice.
After initial board setup, use the following procedure to program the board. Instructions assume that ispVM soft-
ware has been installed on a local PC.
Requirements:
• PC with ispVM System 18.0 (or later) programming software, installed with appropriate drivers (USB driver for
USB cable, Windows 7/XP/2000/NT parallel port driver for ispDOWNLOAD cable).
Note: An option to install these drivers is included as part of the ispVM System setup.
• ispDOWNLOAD cable (pDS4102-DL2A, HW7265-DL3A, HW-USB-1A, etc.). Required only for alternative FPGA
programming and ispClock5406A reprogramming.

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LatticeECP3 Versa Evaluation Board
User’s Guide
Board Programming
Configuration Status Indicators
(see Appendix B, Figure 13)
Figure 3. LatticeECP3 Status LEDs and Push-button Controls
The LEDs indicate the configuration status of the LatticeECP3 FPGA.
•D17 (red) illuminated indicates that programming was aborted or reinitialized, driving the INITN output low.
•D20 (green) illuminated indicates the successful completion of configuration by releasing the open collector
DONE output pin.
•D19 (red) illuminated indicates that PROGRAMN is low.
•D18 (red) illuminated indicates that GSRN is low.
PROGRAMN and GSRN
These push-button switches assert/de-assert the logic levels on PROGRAMN (SW2) and GSRN (SW1). Depress-
ing the button drives a logic level “0” to the device.
Programming Serial SPI Flash Memory
A serial SPI (16-pin TSSOP, 64M) Flash memory device (U8) is on-board for non-volatile configuration memory
storage. A STMicro M25P64VMF16 device is populated on-board.
The Serial SPI Flash memory device can be configured easily via its JTAG port. This mode enables the FPGA to
be programmed at power-up or assertion of PROGRAMN with a bitstream stored in the memory device.
1. Connect the LatticeECP3 Versa Evaluation Board.
2. In the dialog box, select SPI Flash Programming Mode in the Device Access Option pull-down menu.

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LatticeECP3 Versa Evaluation Board
User’s Guide
Figure 4. Device Information Dialog Screen
3. The SPI Serial Flash Device dialog box will open. In this box, select SPI Flash Erase, Program, Verify in the
Operation pull-down menu.
4. Select SPI Serial Flash in the Device Family pull-down menu, STMicro under the Vendor pull-down menu,
SPI-M2564 under the Device pull-down menu, and 16-lead SOIC under the Package submenu.
Figure 5. Select Device Dialog Box

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LatticeECP3 Versa Evaluation Board
User’s Guide
Figure 6. Sample SPI Serial Flash Device Dialog Box
5. Click OK in the SPI Serial Flash Device dialog box. Then click OK in the Select Device dialog box. You will
return to the main configuration screen
6. From the main programming window, select Go from the top toolbar. This will begin the SPI Serial Flash pro-
gramming.
On-Board Clock Capabilities
(See Appendix B, Figure 19)
The LatticeECP3 Versa Evaluation Board allows for several clock source options. Some of these options are con-
trolled via the ispClock5406A programmable clock manager device. The ispClock5406A enables the reference
clock from the PCI Express interface to provide a reference clock to the SERDES. This is true only when the board
is in a PCI Express host socket. When the board is not in a PCI Express host socket, the clock will be supplied by a
156.25 MHz clock on-board oscillator. Both clock inputs can be fanned out to the dedicated SERDES reference
inputs, FPGA inputs, and to the expansion connectors. The factory default programming only connects the
SERDES reference clock inputs. Factory-defined demonstration designs will control and manage the clock.
Figure 7. Clock Controller Scheme
Clock Select
FPGA
Clock
PCLKT0
F11
PCLKC0
F12
SERDES
Reference
Clock
Factory Default
Clock Programming
SERDES Reference
Clock Only
Expansion Interface
Clock
REFCLKP
V12
REFCLKN
V11
PCI Express
156.25 MHz
On-board
Oscillator

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LatticeECP3 Versa Evaluation Board
User’s Guide
General Purpose Clock Source
An on-board 100MHz LVDS oscillator is provided for general purpose use. This clock source is connected to differ-
ential inputs L5 and K6 and must be used as LVDS inputs to the FPGA. This pin pair also provides optimal interface
to the FPGA PLL for customized use.
The PCI Express add-in card specification requires add-in boards to include capabilities to tell the host of its pres-
ence. The LatticeECP3 Versa Evaluation Board allows this optional connection via a board jumper. The factory
default will have two jumpers installed as shown below for the PRSNT connection to the PCI Express host.
Figure 8. PCI Express PRSNT Control Connection
J4
1 2
3 4
5 6
PCI Express PRSNT
Jumper Selector
SERDES
The LatticeECP3 quad-based SERDES FPGA is utilized on the board for several purposes. The PCSA quad is pro-
visioned to provide a single, full-duplex PCI Express channel. The high-speed signals are connected to the PCI
Express edge connection.
Table 3. PCI Express Channel Interconnections
PETp0 HDINP0 Y15
PETn0 HDINN0 Y14
PERp0 HDOUTP0 AB15
PERn0 HDOUTN0 AB14
Table 4. SMA Test Interconnections
J5 HDINP3 Y8
J6 HDINN0 Y9
J7 HDOUTP3 AB8
J8 HDOUTN3 AB9
FPGA Test Pins
(see Appendix B, Figure 18)
General Purpose DIP Switches
General purpose FPGA pins are available for user applications. FPGA pins are connected to switch SW3, a SPST
slide-actuated DIP switch. The switches are connected to logic level 0 when moved to the ON position. Switch posi-
tion 1 is indicated with a dot. These inputs are within a bank connected to 1.5V. The user must program these
inputs to be the LVCMOS15 type in the design.

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LatticeECP3 Versa Evaluation Board
User’s Guide
Figure 9. LatticeECP3 Versa Evaluation Board LEDs and Switches
The designated pins are connected according to Table 5.
Table 5. FPGA Ball to DIP Switch Position
FPGA Ball
Number
SW3 DIP Switch
Position
J7 1
J6 2
H2 3
H3 4
J3 5
K3 6
J2 7
J1 8
General Purpose LEDs
(See Appendix B, Figure 18)
The LEDs provided on the LatticeECP3 Versa Evaluation Board are connected to general purpose FPGA I/Os.
These LEDs provide status for user designs and must be included in the design. The LEDs illuminate when the
FPGA output is driven LOW. Tabl e 6 shows the LED and associated FPGA pins. These pins are within an I/O bank
connected to 3.3V and the user should program these to be LVCMOS33 type outputs in the design.
Table 6. LED Definitions
LED
Number
FPGA Ball
Number
PCB
Designator LED Color
LED0 U19 D21 Green
LED1 U18 D22 Green
LED2 AA21 D24 Ye l l o w
LED3 Y20 D25 Ye l l o w
LED4 W19 D26 Red
LED5 V19 D27 Red
LED6 AA20 D29 Blue
LED7 AB20 D28 Blue

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LatticeECP3 Versa Evaluation Board
User’s Guide
Alpha-numeric LED Display
(see Appendix A, Figure 18)
A 14-segment alpha-numeric display is provided on the board (D23). These LED segments are connected to gen-
eral-purpose FPGA I/Os. The LEDs must be included in the FPGA design. The LEDs illuminate when the FPGA
output is driven LOW. Ta bl e 7 shows the LED and associated FPGA pins. These pins are within an I/O bank con-
nected to 3.3V and the user should program these to be LVCMOS33 outputs in the design.
Figure 10. 14-Segment Display
Table 7. Alpha-numeric LED Definitions
Display
fpBGA Ball
Number Display
fpBGA Ball
Number
AV6 JAB3
BU7 KAB4
CY6 LW4
DAa6 MY5
EU8 NAA4
FT8 PAA5
GR9 DP W5
HT9
DDR3 Memory Device
(see Appendix B, Figure 17)
• The LatticeECP3 Versa Evaluation Board is equipped with a SDRAM memory device (1.5V, 64Mb/x16, 96-ball
FBGA, 667 MHz, DDR3-1333) such as the Micron MT41J64M16JT-15E:G device.
• The DDR3 memory includes a 16-bit wide memory controller interface.
• The board includes termination of data, address and command signals. It includes all power and external compo-
nents needed to demonstrate the memory controller of the LatticeECP3 device.
• A 100 MHz on-board clock oscillator is available to provide a DDR3 reference clock.

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LatticeECP3 Versa Evaluation Board
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Table 8. DDR3 Memory Controller Interconnections
NETNAME
484 fpBGA
Ball Number NETNAME
484 fpBGA
Ball Number
DQ0 E5 A0 C8
DQ1 E4 A1 C7
DQ2 D2 A2 B7
DQ3 D1 A3 D8
DQ4 C2 A4 F9
DQ5 B2 A5 E9
DQ6 G5 A6 A3
DQ7 G4 A7 D7
DQ8 G2 A8 A7
DQ9 F1 A9 B8
DQ10 H4 A10 C9
DQ11 E2 A11 C10
DQ12 J4 K_0 K4
DQ13 B1 K_0# K5
DQ14 C1 CAS# A4
DQ15 G3 BA0 B4
DQS0 F5 BA1 E6
DQS0# F4 BA2 D5
DQS1 H5 ODT E7
DQS1# H6 CS0# C6
CEO G8 WE# D6
RAS# A6 VREF E1
CLKP L5 DM0 E3
CLKN K6 DM1 F3
Ethernet Interfaces
(see Appendix B, Figure 18)
Two Marvell 88E1119R Gigabit Ethernet transceiver devices (U17) are included on the board. This physical layer
device supports 1000BASE-T, 100BASE-TX, and 10BASE-T applications via a standard media interface to a dual
RJ45 connection. The RJ45 connection includes network magnetics providing the proper signal conditioning, elec-
tro-magnetic interference suppression and signal isolation. This connector includes two LEDs and the board
includes four status LEDs from the Marvell device. The LEDs are register-programmed and detailed descriptions
are available in the Marvell device data sheet.
Table 9. PHY Status Indicators
LED Status Description
RJ45 (Yellow) LED RX
RJ45 (Yellow) LED TX
Each Marvell 88E1119R device communicates via a GMII interface to the LatticeECP3 device.

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LatticeECP3 Versa Evaluation Board
User’s Guide
Table 10. FPGA GPIO to GMII Interfaces
Signal PHY#1 PHY#2
RSTN L3 R21
MDIO L2 U16
MDC: V4 Y18
RXC L4 N19
RX_ER M4 V20
RX_DV M1 U15
RX_D0 M5 AB17
RX-D1 N1 AA17
RX_D2 N6 R19
RX_D3 P6 V21
RX_D4 T2 T17
RX_D5 R2 R18
RX_D6 P5 W21
RX_D7 P3 Y21
TXC C12 M21
TX_EN V3 V22
TX_D0 V1 W22
TX_D1 U1 R16
TX_D2 R3 P17
TX_D3 P1 Y22
TX_D4 N5 T21
TX_D5 N3 U22
TX_D6 N4 P20
TX_D7 N2 U20
GTXCLK M2 M19
CRS P4 P19
COL R1 N18
COMA R41T151
125CLK T3 R17
1. Each PHY device includes a header dedicated to the COMA connection to the device.
The header is populated with a jumper that disables and places the PHY in a low power
configuration. Headers J10 and J12 are used for this purpose. It is assigned to PHYs U9
and U10, respectively.

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LatticeECP3 Versa Evaluation Board
User’s Guide
Table 11. Expansion Connections
x3 Expansion Connector x4 Expansion Connector
Pin Signal 484-Ball fpBGA Pin Signal 484-Ball fpBGA
1 GND GND 1 HPE-RST# J20
2NC NC 2GND GND
32.5V 2.5V 3IO0 B11
4IO29 D17 4IO1 B12
5IO30 J22 5IO2 A12
6IO31 K22 6IO3 A13
7IO32 L18 7IO4 E12
8IO33 L19 8IO5 E13
9IO34 L22 9IO6 C13
10 IO35 M22 10 IO7 C14
11 IO36 K18 11 IO8 D13
12 IO37 K17 12 IO9 D14
13 IO38 H22 13 IO10 A14
14 IO39 H21 14 IO11 B14
15 IO40 G22 15 IO12 F13
16 IO41 G21 16 IO13 F14
17 IO42 J18 17 IO14 A15
18 IO43 J17 18 IO15 B15
19 IO44 F22 19 GND GND
20 IO45 E22 20 3.3V 3.3V
21 5VIN 5VIN 21 IO16 C15
22 GND GND 22 GND GND
23 2.5V 2.5V 23 IO17 D15
24 GND GND 24 GND GND
25 3.3V 3.3V 25 IO18 G15
26 GND GND 26 GND GND
27 3.3V 3.3V 27 IO19 G14
28 GND GND 28 IO20 A16
29 OSC U13 PIN27 29 IO21 B16
30 GND GND 30 GND GND
31 CLKIN E15 31 IO22 F15
32 GND GND 32 IO23 F16
33 CLKOUT D12 33 IO24 A17
34 GND GND 34 GND GND
35 3.3V 3.3V 35 IO25 B18
36 GND GND 36 IO26 A18
37 3.3V 3.3V 37 IO27 A19
38 GND GND 38 CARDSEL# J19
39 3.3V 3.3V 39 IO28 D16
40 GND GND 40 GND GND

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LatticeECP3 Versa Evaluation Board
User’s Guide
References
• DS1021, LatticeECP3 Family Data Sheet
• HB1009, LatticeECP3 Family Handbook
•QS013,LatticeECP3 Versa Evaluation Board Quick Start Guide
• UG46, PCI Express Demos for the LatticeECP3 Versa Evaluation Board
• UG45, DDR3 Demo for the LatticeECP3 Versa Evaluation Board
• UG44, SERDES Eye/Backplane Demo for the LatticeECP3 Versa Evaluation Board
Ordering Information
Description Ordering Part Number
China RoHS Environment-Friendly
Use Period (EFUP)
LatticeECP3 Versa Evaluation Board LFE3-35EA-VERSA-EVN

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LatticeECP3 Versa Evaluation Board
User’s Guide
Technical Support Assistance
e-mail: [e-mail]
Internet: www.latticesemi.com
Revision History
Date Version Change Summary
April 2011 01.0 Initial release.
August 2011 01.1 Updated LatticeECP3 Versa Evaluation Board, Top Side diagram.
Corrected ispVM System software version number in the ispVM
Requirements text section.
Corrected ispVM JTAG Connector Pinout table caption information.
November 2011 01.2 Corrected error in the column headings of the Expansion Connections
table.
February 2012 01.3 Updated document with new corporate logo.
February 2012 01.4 Expansion Connections table – Updated information for pins 31 and 33.
August 2012 01.5 Added alternate Abracon part numbers for Discera oscillators in Bill of
Materials.
July 2013 01.6 Added note in the Alternate ispVM Download Interface section.
Updated Technical Support Assistance information.
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.

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LatticeECP3 Versa Evaluation Board
User’s Guide
Appendix A. Schematics
Figure 11. Cover Page
5
5
4
4
3 3
2 2
1
1
D D CC B B A A
Power Device Power Pins
3.3V Programming SPI
PCSA
Bank
8
ECP3
Bank 0
Bank 3
FPGA
Bank 6 Bank 7
Bank 1
Bank 2
SERDES
Designator U1 is the FPGA DUT.
PCIe X1 CH#0
CLK5406
REFERENCE
CLOCKS
PCIe RefClk 156.25M OSC
Expansion Port- 3.3V
1.5V 16-Bit DDR3
PCSA RefClk General Clk 3.3V GMII PHY#1
3.3V GMII PHY#2
Expansion
Port-3.3V
SMA Test CH#3
Expansion Clk
PLL
100.00M DIFF OSC
LED SEGMENT ARRAY
USER DIP SWITCH
USER LEDS
Revision History: February 9, 2011 Rev A Final Design JPS February 24, 2011 Rev B JPS
Title Size Project Rev Date: Sheet of
1605 Valley Center Parkway Bethlehem, PA 18017
ECP3 VERSA Eval Board
B
Cover Page
B
111Monday, March 14, 2011
Title Size Project Rev Date: Sheet of
1605 Valley Center Parkway Bethlehem, PA 18017
ECP3 VERSA Eval Board
B
Cover Page
B
111Monday, March 14, 2011
Title Size Project Rev Date: Sheet of
1605 Valley Center Parkway Bethlehem, PA 18017
ECP3 VERSA Eval Board
B
Cover Page
B
111Monday, March 14, 2011

17
LatticeECP3 Versa Evaluation Board
User’s Guide
Figure 12. Power
5 5
4
4
3
3
2
2
1
1
D D C C B B A A
10V
Core Power
2.3v minimum input voltage
+1.2 v 500 mA
+1.2 v 500 mA
0.46 v drop at 500 mA max
+1.5v
1.1 A
POWER INPUT
+11v to +16v
1.2v/ms
1.2v/ms
1.2v/ms
Voltage Regulators
+3.3 v 1.35 A
SW
3_3V, +3.3 V, 1.35 A
Power Supply Block Diagram
12_0V
EN
+1.2 v 1.35 A
Vout = 0.8*(R15/R21+1) = 1.21 v
SW
(5A fused)
SW 1_5V, +1.5 V, 1.1 A
EN
VCC_CORE, +1.2 V, 1.35 A
SW
Vout = 0.8*(R8/R13+1) = 3.28 v Vout = 0.8*(R16/R17+1) = 1.51 v
LDO SERDES 1_2V, +1.2 V, 1A
EN
SERDES Power
DDR3 1.5V Power
3.3V
1.2v/ms +2.5v 1.1 A
Vout = 0.8*(R7/R9+1) = 2.52 v
2.5V
2_5V, +2.5V, 1.1 A
1.2V VCC_CORE 1.5V 3.3V
1.2V Analog
12VIN GOOD
6.3V 0805
DNI
DNI
10V
2.5V
VCCPLL
PCSA_VCCIB PCSA_VCCOB
VCCA
12_0V
12_0VIN 12_0V
12_0V
VOUT2
2_5V
2_5V
3_3V 3_3V
3_3V2_5V
VCC_CORE
3_3V 3_3V
1_5V
VOUT1
VCCA
3_3V
3_3V
VCC_CORE
3_3V12_0V
VCC_CORE
12_0V
1_5V
12_0V
VCCA
12_0V
12_0VIN
2_5V
Title Size Project Rev Date: Sheet of
1605 Valley Center Parkway Bethlehem, PA 18017
ECP3- VERSA Eval Board
B
Power
C
211Wednesday, February 09, 2011
Title Size Project Rev Date: Sheet of
1605 Valley Center Parkway Bethlehem, PA 18017
ECP3- VERSA Eval Board
B
Power
C
211Wednesday, February 09, 2011
Title Size Project Rev Date: Sheet of
1605 Valley Center Parkway Bethlehem, PA 18017
ECP3- VERSA Eval Board
B
Power
C
211Wednesday, February 09, 2011
R19
30_1K-0402SMT
R7 21_5K-0402SMT 1%
C6
100NF-0402SMT
R22
1_8K-1206SMT
C20
10NF-0402SMT
C5
10NF-0402SMT
C41
22uF,6.3V-0805SMT
RLP-133
3_3UF-10V-0805SMT C12
R28
10K-0603SMT
C14
1UF-16V-0805SMT
R20
20K-0402SMT
R3 OPEN-0603SMT
D2
1N4448W
21
C16 10NF-0402SMT
C24
1UF-16V-0805SMT
R17 16_9K-0402SMT 1%
C8
100NF-0402SMT
R18
63_4K-0402SMT
1%

G
D10
LED_GREEN_0603
U4 LT3508EUF
FB2 18
VC2 19
PG2 20
RT/SYNC
22
SHDN 21
FB1
1
TRACK/SS1
2
BOOST1
7
SW1
8
VIN1 9
VC1
24
VIN2 10
PG1
23
SW2 11
BOOST2 12
TRACK/SS2 17
GND5
25
GND6
13
GND7
14
GND4
6GND3
5GND2
4GND1
3
GND8
15
GND9
16
C31
1NF-0402SMT
C21
10NF-0402SMT
TP4
C2
10NF-0402SMT
L1
4.7uH-SPD62R-472M
+
C13
22UF-16V-TANTBSMT
10uF,25V-1206SMT
C30
C33
10NF-0402SMT
U2
LT3029EDE
BYP1
1
VIN1_13 13
BYP2 8
ADJ2 9
GND
5
ADJ1
16
EN
15
VOUT1
4
EN2 10
VOUT2 7
VIN2 12
VOUT1_3
3VOUT2_6 6
VIN1 14
VIN2_11 11
NC
2
GND_PAD
17
R12
51K-0402SMT
U3 LT3508EUF
FB2 18
VC2 19
PG2 20
RT/SYNC
22
SHDN 21
FB1
1
TRACK/SS1
2
BOOST1
7
SW1
8
VIN1 9
VC1
24
VIN2 10
PG1
23
SW2 11
BOOST2 12
TRACK/SS2 17
GND5
25
GND6
13
GND7
14
GND4
6GND3
5GND2
4GND1
3
GND8
15
GND9
16
R23 1_8K-1206SMT
D5
1N4448W
21
3_3UF-10V-0805SMT
C10
C28
100NF-0402SMT
C58 22uF,6.3V-0805SMT RLP-133
C9
100NF-0402SMT
R2 0R-0603SMT
C60
10pF-0402SMT
R15 5_11K-0402SMT 1%
C19
1UF-16V-0805SMT
C45
330pF-0402SMT
C42 22uF,6.3V-0805SMT RLP-133
R13 11_5K-0402SMT 1%
F1
F1251CT-ND
5A Fast-Blo SMT Socketed Fuse
R29
10K-0603SMT
+
C25
22UF-16V-TANTBSMT
C1
10NF-0402SMT
C51
10uF,25V-1206SMT
RLP-134
R179 220R-0603SMT
C54
22uF,6.3V-0805SMT
RLP-133
C32
1NF-0402SMT
R1
0R-0603SMT
C62
330pF-0402SMT
D3
DFLS220L
12
+
C18
22UF-16V-TANTBSMT
D1
1N4448W
21
G
D9
LED_GREEN_0603
R26 220R-0603SMT
C29
10NF-0402SMT
J1
PJ-032A Male Power Jack 2.1mm
1
3
2
TP2
G
D31
LED_GREEN_0603
C3
10NF-0402SMT
L4
4.7uH-SPD62R-472M
R25
1_8K-1206SMT
C64
22uF,6.3V-0805SMT
RLP-133
R27
10K-0603SMT
G
D12 LED_GREEN_0603
C38 220NF-0402SMT 16V
FB1
BLM41PG600SN1
C47
10pF-0402SMT
C35
1UF-16V-0805SMT
C4
10NF-0402SMT
R8
35_7K-0402SMT
1%
C55
22uF,6.3V-0805SMT
RLP-133
C53 220NF-0402SMT 16V
D8
DFLS220L
12
R14 51K-0402SMT
G
D13
LED_GREEN_0603
R24
1_8K-1206SMT
C40
22uF,6.3V-0805SMT
RLP-133
R11
34K-0402SMT
1%

C61
10pF-0402SMT
LFE3-35E-FN484CES
U1A
Data Sheet Version = 1.0
GND
R13 GND
L11 GND
M10 GND
E8 GND
U17 GND
U14 GND
N13 GND
AB16 GND
N21 GND
G11 GND
K10 GND
C19 GND
T13 GND K11 GND P18 GND
AA11 GND
V7 GND
M3 GND
L10 GND
V9 GND
H15 GND
F6 GND
L13 GND
F17 GND
T11 GND
R8 GND
B17 GND
A1 GND
R15 GND
AA14 GND
V8 GND
P16 GND
U6 GND N8 GND
U21 GND
J21 GND
K15 GND
L20 GND
H13 GND
L16 GND
A22 GND
J5 GND
V16 GND
W7 GND
AA8 GND
B13 GND
B5 GND
AB7 GND
L7 GND
H10 GND
M11 GND
W20 GND
M7 GND
V15 GND
AA9 GND
T12 GND
P2 GND
E21 GND
C11 GND
AA12 GND
Y16 GND
V14 GND
AA16 GND
H18 GND
M12 GND
R5 GND
W16 GND
AB22 GND
H8 GND
N10 GND
E14 GND
U10 GND
F2 GND
Y7 GND K2 GND
R10 GND
K12 GND
AA18 GND
L12 GND
U9 GND
T10 GND
AA13 GND
AB1 GND
M13 GND
D3 GND
AA15 GND AA10 GND
U13 GND
AA7 GND
N12 GND
Y4 GND
M16 GND
K8 GND
V2 GND
G12 GND
B9 GND
K13 GND
N11
RESERVE-AB2 AB2 RESERVE-AA3 AA3
VCC J11 VCC J9 VCC P11 VCC P12
VCC J14
VCC J13
VCC M14 VCC M9
VCC P9 VCC L9 VCC P14
VCC P10 VCC J12
VCC J10 VCC L14
VCC P13
VCCA V13 VCCA U12
VCCA U11 VCCA V10
VCCAUX M8 VCCAUX R11 VCCAUX H11 VCCAUX M15
VCCAUX R12
VCCAUX H12 VCCAUX L8 VCCAUX L15
VCCPLL_L K9 VCCPLL_L N9
VCCPLL_R K14
VCCPLL_R N14
XRES N15
FB4
BLM41PG600SN1
C43 1000pF-0402SMT
C245
100pF-0402SMT
R16
15K-0402SMT
1%
C22
100NF-0402SMT
D4
DFLS220L
12
C57 1000pF-0402SMT
R6 51K-0402SMT
Q2
2N2222/SOT23
3
1
2
L3
4.7uH-SPD62R-472M
D14 SCHOTTKY/VISHAY-V12P10
+
C36
22UF-16V-TANTBSMT
C52
220NF-0402SMT
16V
C11
100NF-0402SMT
TP3
R10
51K-0402SMT
L2
4.7uH-SPD62R-472M
C27
1UF-16V-0805SMT
D6
1N4448W
21
C49
22uF,6.3V-0805SMT
RLP-133
Q3
2N2222/SOT23
3
1
2
C59
330pF-0402SMT
C34
100NF-0402SMT
R5 10K-0402SMT
C56 1000pF-0402SMT
R9
10K-0402SMT
1%
C23
100NF-0402SMT
C39 220NF-0402SMT 16V
C48
330pF-0402SMT
TP1
C50 22uF,6.3V-0805SMT RLP-133
Q1
2N2222/SOT23
3
1
2
C7
100NF-0402SMT
D7
DFLS220L
12
R21 10K-0402SMT 1%
R4 OPEN-0603SMT
C46
10pF-0402SMT
+
C26
22UF-16V-TANTBSMT
C44 1000pF-0402SMT
C37
10uF,25V-1206SMT
RLP-134
C246
100pF-0402SMT
10uF,25V-1206SMT C17
G
D11 LED_GREEN_0603
C15
10NF-0402SMT
FB2
BLM41PG600SN1
C63
22uF,6.3V-0805SMT
RLP-133
FB3
BLM41PG600SN1

18
LatticeECP3 Versa Evaluation Board
User’s Guide
Figure 13. Programming
5 5
4
4
3
3
2
2
1
1
D D C C B B A A
FPGA GSRN PROGRAMN
DONE indicator will light when
configuration is successfully completed INITN indicator will light if an error occurs during configuration programming
CONFIG Status LEDs
PROGRAMN & GSRN Pushbuttons
SPI FLASH
DONE
INITN
GSRN PROGRAMN
USB Download
Local JTAG
header (ispVM)
TMS TCK DONE INITn +3.3V TDI GND TDO PROGRAMn
12 MHz
PROGRAMN
GSRN
INITN
DONE
NW
FLASH_DIS
FPGA_SISPI
GSRN
PROGRAMN
FPGA_CSSPI0N_DI
SPI0_Q
FPGA_MCLK
USB_N_i
USB1_CS
USB_N
USB_P_i
FPGA_WRITEN
USB1_D
FPGA_CSN
USB_P
FPGA_CS1N
DONE
FPGA_CCLK
INITN
PROGRAMN
FPGA_TDO
FPGA_TDI
FPGA_TMS
FPGA_TCK
FPGA_CCLK
FPGA_MCLK PROGRAMN
SPIFASTN
FPGA_WRITEN INITN SPIFASTN
FPGA_CSSPI0N_DI FPGA_CSN FPGA_CS1N
DONE
FPGA_SISPI SPI0_Q GSRN RXD_UART TXD_UART
TXD_UART
RXD_UART
USB1_CS USB1_SK USB1_Q
JTAG_ACT
JTAG_ACT
UART_ACT
UART_ACT
3_3V
3_3V
3_3V 3_3V 3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
FTVCC1_8V
FTVCC1_8V 3_3V
3_3V
3_3V
3_3V
3_3V
3_3V 3_3V
156MHz_EN [9]
SCL [9]
SDA [9]
PCIE_PERSTN [4]
CLK_RESETn [9]
Title Size Project Rev Date: Sheet of
1605 Valley Center Parkway Bethlehem, PA 18017
ECP3 VERSA Eval Board
B
Programming
C
311Friday, March 18, 2011
Title Size Project Rev Date: Sheet of
1605 Valley Center Parkway Bethlehem, PA 18017
ECP3 VERSA Eval Board
B
Programming
C
311Friday, March 18, 2011
Title Size Project Rev Date: Sheet of
1605 Valley Center Parkway Bethlehem, PA 18017
ECP3 VERSA Eval Board
B
Programming
C
311Friday, March 18, 2011
R56 680R-0603SMT
C66 100NF-0402SMT
R44
12K-0603SMT
R36 0R-0603SMT
C83
10NF-0402SMT
R37
10K-0603SMT
R31
220R-0603SMT
C72 100NF-0402SMT
LFE3-35E-FN484CES
U1I
TCK
G7
TDI
G6
TDO
C3
TMS
C4
VCCJ
H7
C79
12PF-0603SMT
DI
R48 2_2K-0603SMT
DI
FB5 MPZ1608Y600B DI
12
R54 10K-0402SMT
C67
100NF-0402SMT
VCC
GND
TDO TDI
ispEN_N
NC
TMS
TCK
DONE
INITN
J3 HEADER 10
1
2 3 4 5 6
7
8
9
10
C82
100NF-0402SMT
R46 4_7K-0603SMT
R69 10K-0402SMT
R66
10K-0402SMT
R38 0R-0603SMT
U7
MAX6817
IN1
1
GND
2
IN2
3
OUT2 4
VCC 5
OUT1 6
+
C65 4_7UF-10V-SMT
C70
100NF-0402SMT
R58
4_7K-0603SMT
G
D15
LED_GREEN_0603
R60
680R-0603SMT
Y1
ATS120SM-1 HC-49/US-SM
DI
12
R39 27R-0603SMT
R63
10K-0402SMT
R53
4_7K-0402SMT
R45
4_7K-0603SMT
+
C74 3_3UF-10V-SMT
L5
1UH-1206SMT
G
D16
LED_GREEN_0603
R67
10K-0402SMT
R64
10K-0402SMT
R52
0R-0402SMT
C77
100NF-0402SMT
FTDI High-Speed USB FT2232H
FT2232HL U5
VREGIN
50
VREGOUT
49
DM
7
DP
8
REF
6
RESET#
14
EECS
63
EECLK
62
EEDATA
61
OSCI
2
OSCO
3
TEST
13
ADBUS0 16 ADBUS1 17 ADBUS2 18 ADBUS3 19
VPHY 4
VPLL 9
VCORE 12
VCORE 37
VCORE 64
VCCIO 20
VCCIO 31
VCCIO 42
VCCIO 56
AGND
10
GND
1
GND
5
GND
11
GND
15
GND
25
GND
35
GND
47
GND
51
PWREN# 60
SUSPEND# 36
ADBUS4 21
ADBUS5 22 ADBUS6 23 ADBUS7 24
ACBUS0 26
ACBUS1 27 ACBUS2 28
ACBUS3 29
ACBUS4 30 ACBUS5 32
ACBUS6 33 ACBUS7 34 BDBUS0 38 BDBUS1 39 BDBUS2 40
BDBUS3 41 BDBUS4 43
BDBUS5 44
BDBUS6 45
BDBUS7 46
BCBUS0 48
BCBUS1 52
BCBUS2 53
BCBUS3 54 BCBUS4 55 BCBUS5 57 BCBUS6 58 BCBUS7 59
TP5
R61
220R-0603SMT
C69
100NF-0402SMT
R62 OPEN-0402SMT
R34
4_7K-0402SMT
C76
33pF-0402SMT-DNI
R65
10K-0603SMT
C75
33pF-0402SMT-DNI
SW2
C85
10NF-0402SMT
R33 0R-0603SMT
SW1
93LC56-SO8 U6
CS 1
CLK 2
DI 3
DO 4
VSS
5ORG 6NU 7VCC 8
R47 4_7K-0603SMT
R42
10K-0402SMT
R51
4_7K-0402SMT
R40
4_7K-0402SMT
R71 10K-0402SMT
R30
220R-0603SMT
G
D20
LED_GREEN_0603
C68
100NF-0402SMT
U8
M25P64-FLASH
S#
7
Q
8
DU1
3
DU2
4
VCC
2HOLD#
1
DU4
6DU3 5
W# 9
VSS 10
DU5 11 DU6 12 DU7 13
DU8 14
D15
CK 16
+
C71 4_7UF-10V-SMT
J2
USB_MINI_AB
11 22
33 44 55
7
788
99 6
6
R50 1M-0603SMT DI
LFE3-35E-FN484CES
U1H
CCLK F20
CFG0 E20 CFG1 E19 CFG2 B21
DONE F21
INITN D20
PR11A/W RITEN J16
PR11B/D0/SPIFAST N H17
PR12A/D1 C22 PR12B/D2 D22
PR14A/D3/SI G17
PR14B/D4/SO G18
PR15A/D5 G19
PR15B/D6/SPID1 G20 PR17A/D7/SPID0 H19
PR17B/BUSY/SISPI H20
PR6A C21
PR6B/DI/CSSPI0N/CSSPIN D21
PR8A/CS1N/HOLDN/CONT2N F19
PR8B/CSN/SN/CONT1N F18
PR9A/DOUT /CSON/CSSPI1N A21
PR9B/MCLK B22
PROGRAMN C20
PT68A C18 PT68B B19 PT70A E18 PT70B E17 PT71A A20
PT71B B20 PT73A D18
PT73B D19
VCCIO8 H16 VCCIO8 G16
R70
10K-0402SMT
R59
FB6 MPZ1608Y600B DI
12
Y
D18
LED_RED_0603
R49 1K-0603SMT
C81
100NF-0402SMT
R55
680R-0603SMT
R
D17
LED_RED_0603
R41
10K-0402SMT
R68 10K-0402SMT
R57 C73 100NF-0402SMT
R43
10K-0402SMT
Y
D19 LED_RED_0603
Q4
2N2222/SOT23
3
1
2
R32 0R-0603SMT
R35 27R-0603SMT
C80 12PF-0603SMT
18pF = 12pF + Ground Plane ( 6pF )
DI
C84
100NF-0603SMT
C78
100NF-0603SMT

19
LatticeECP3 Versa Evaluation Board
User’s Guide
Figure 14. SERDES
5
5
4
4
3 3
2 2
1
1
D D CC B B A A
X1 PCIe Board Fingers
All Nets to SMAs are 100-ohm differential pairs. The P and N traces shall be <20mil matched in length
All Nets are 85-ohm differential pairs. The P and N traces shall be <20mil matched in length
B side = Primary Component Side(TOP) A side = Secondary Component Side(BOTTOM)
x1_PERp0
x1_PERn0
PRSNT3#
PCIE_3V3
PRSNT1#
x1_PERp0
x1_PERn0
x1_PETp0
x1_PETn0
PCIE_3V3
PCSA_HDOUTP0
PCSA_HDOUTN0
PCSA_HDINN3PCSA_HDINP3
PCSA_HDOUTP3 PCSA_HDOUTN3
PCIE_CLKP
PCIE_CLKN
PRSNT1#
PRSNT3#
PCSA_HDOUTN3 PCSA_HDOUTP3 PCSA_HDOUTN0
PCSA_HDOUTP0
PCSA_HDINN3 PCSA_HDINP3
x1_PETp0
x1_PETn0
PCSA_REFCLKP
PCSA_REFCLKN
12_0VIN
PCSA_VCCOB
3_3V
PCSA_VCCIB
PCSA_VCCOB PCSA_VCCIB
PCIE_CLKP[9]
PCIE_CLKN[9]
PCSA_REFCLKP [9]
PCSA_REFCLKN [9]
PCIE_PERSTN[3]
PRSNT [9]
Title Size Project Rev Date: Sheet of
1605 Valley Center Parkway Bethlehem, PA 18017
ECP3 VERSA Eval Board
B
SERDES
B
411Wednesday, February 09, 2011
Title Size Project Rev Date: Sheet of
1605 Valley Center Parkway Bethlehem, PA 18017
ECP3 VERSA Eval Board
B
SERDES
B
411Wednesday, February 09, 2011
Title Size Project Rev Date: Sheet of
1605 Valley Center Parkway Bethlehem, PA 18017
ECP3 VERSA Eval Board
B
SERDES
B
411Wednesday, February 09, 2011
J5 SMA
12
3
4
5
C90
1NF-0402SMT
R178 OPEN-0603SMT
J6 SMA
12
3
4
5
C88
100NF-0402SMT
J4
HEADER 3X2
2 4 6
1 3 5
C89
10NF-0402SMT
J7 SMA
12
3 4
5
C87100NFX5R-0402SMT
C86100NFX5R-0402SMT
J8 SMA
12
3 4
5
CN1
PCI Express x1 Edge Finger Conn.
PRSNT1#
A1
+12V
A2
+12V
A3
GND
A4
JTAG2
A5
JTAG3
A6
JTAG4
A7
JTAG5
A8
+3.3V
A9
+3.3V
A10
PERST#
A11
GND
A12
REFCLK+
A13
REFCLK-
A14
GND
A15
PERp0
A16
PERn0
A17
GND
A18
+12V B1 +12V B2
RSVD_B3 B3
GND B4
SMCLK B5
SMDAT B6
GND B7
+3.3V B8
JTAG1 B9
3.3Vaux B10
WAKE# B11
RSVD_B12 B12
GND B13
PETp0 B14
PETn0 B15
GND B16
PRSNT3# B17
GND B18
TP6 Testpoint
1
C91
100NF-0402SMT
C93
1NF-0402SMT
LFE3-35E-FN484CES
U1J
PCSA_HDINN0 Y14
PCSA_HDINN1 Y13
PCSA_HDINN2 Y10 PCSA_HDINN3 Y9
PCSA_HDINP0 Y15 PCSA_HDINP1 Y12 PCSA_HDINP2 Y11
PCSA_HDINP3 Y8
PCSA_HDOUTN0 AB14
PCSA_HDOUTN1 AB13
PCSA_HDOUTN2 AB10 PCSA_HDOUTN3 AB9
PCSA_HDOUTP0 AB15
PCSA_HDOUTP1 AB12
PCSA_HDOUTP2 AB11
PCSA_HDOUTP3 AB8
PCSA_REFCLKN V11
PCSA_REFCLKP V12
PCSA_VCCIB0 W15 PCSA_VCCIB1 W12 PCSA_VCCIB2 W11
PCSA_VCCIB3 W8
PCSA_VCCOB0 W14
PCSA_VCCOB1 W13
PCSA_VCCOB2 W10 PCSA_VCCOB3 W9
R72
4_7K-0603SMT
C92
10NF-0402SMT

20
LatticeECP3 Versa Evaluation Board
User’s Guide
Figure 15. 10/100/1000-T PHY #1/RJ45
5 5
4
4
3
3
2
2
1
1
D D C C B B A A
TX and RX traces are all matched length < 2"
MH1 and MH2 are 0.100" diameter plated
through holes
Ethernet RJ45 Connector
Place caps close to RJ45 jack
Place termination resistors RX_D0-7, RX_ER, RX_DV, RX_CLK, TX_CLK, CRS, COL, RSTN as close to the G-PHY as possible using 50 ohm impedence traces.
Place termination
resistors TX_D0-7, TX_ER, TX_EN, GTX_CLK as close to FPGA as possible using 50 ohm impedence traces.
GPHY 1.8V Power
PHY1_VDDOR
PHY1_VDDO
ETH1_MD1_N ETH1_MD2_P ETH1_MD1_P
ETH1_MD3_N
ETH1_MD3_P
PHY1_LED0
ETH1_MD2_N ETH1_MD0_P
ETH1_MD0_N
PHY1_LED1
ETH1_MD0_N
ETH1_MD0_P
ETH1_MD1_P
ETH1_MD1_N
ETH1_MD2_P
ETH1_MD2_N
ETH1_MD3_P
ETH1_MD3_N
PHY1_TXD0
PHY1_TXD2
PHY1_TXD1
PHY1_TX_EN
PHY1_TXD3 PHY1_TXD4 PHY1_TXD5 PHY1_TXD6 PHY1_TXD7
PHY1_RXD0
PHY1_RXD1
PHY1_RXD3
PHY1_RXD4
PHY1_RXD5
PHY1_RXD6
PHY1_RXD7
PHY1_RXD2
PHY1_MDC PHY1_MDIO PHY1_VDDOPHY1_GTXCLK
PHY1_TXC
PHY1_CRS PHY1_COL
PHY1_RXC
PHY1_RX_DV
PHY1_RX_ER
PHY1_LED0 PHY1_LED1 PHY1_LED2 PHY1_COMAn
PHY1_VDDOR
PHY1_VDDOR
PHY1_DVDD PHY1_VDDO PHY1_DVDD
PHY1_DVDD PHY1_DVDD
PHY1_AVDDC
PHY1_AVDD
PHY1_AVDD
PHY1_AVDDR
PHY1_AVDDX
PHY1_AVDDX
PHY1_AVDDC
PHY1_RSTN
PHY1_LED2
PHY1_VDDO
PHY1_XTAL_OUTPHY1_XTAL_IN
PHY1_XTAL_IN PHY1_XTAL_OUT
PHY1_DVDD
PHY1_VDDO
1_RXC
1_RX_DV
1_RX_ER
1_RXD4
1_RXD1
1_RXD0
1_RXD6
1_RXD5
1_RXD7
1_RXD3
1_RXD2
1_TXC
1_COL 1_CRS
PHY1_COMAn
PHY1_CLK125
1_RSTN
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6
SEG7
SEG8
SEG9
SEG10 SEG11 SEG12 SEG13 SEG14
PHY1_AVDD
PHY1_AVDD
PHY1_VCC_CT
PHY1_AVDDRPHY1_AVDDR
1_125MHz PHY1_CLK125 1_COL 1_CRS 1_GTXCLK PHY1_GTXCLK PHY1_MDC PHY1_MDIO 1_RSTN
1_RXC
1_RX_DV
1_RX_ER
1_RXD0 1_RXD1 1_RXD2
1_RXD3
1_RXD4 1_RXD5 1_RXD6 1_RXD7
PHY1_TX_EN1_TX_EN
PHY1_TXD01_TXD0 PHY1_TXD1
1_TXD1
PHY1_TXD2
1_TXD2
PHY1_TXD3
1_TXD3
PHY1_TXD41_TXD4 PHY1_TXD51_TXD5 PHY1_TXD61_TXD6 PHY1_TXD7
1_TXD7 PHY1_COMAn
PHY1_AVDDC
3_3V
PHY1_VCC_CT
3_3V
3_3V
3_3V
SEG[0:14] [8]
1_TXC
[10]
Title Size Project Rev Date: Sheet of
1605 Valley Center Parkway Bethlehem, PA 18017
ECP3-VERSA Eval Board
B
10/100/1000-T PHY#1/RJ45
C
511Thursday, February 24, 2011
Title Size Project Rev Date: Sheet of
1605 Valley Center Parkway Bethlehem, PA 18017
ECP3-VERSA Eval Board
B
10/100/1000-T PHY#1/RJ45
C
511Thursday, February 24, 2011
Title Size Project Rev Date: Sheet of
1605 Valley Center Parkway Bethlehem, PA 18017
ECP3-VERSA Eval Board
B
10/100/1000-T PHY#1/RJ45
C
511Thursday, February 24, 2011
0
R90
0
R97
C114
10uF/6V3/X7R-0805SMT
C128
100NF-0603SMT
C122
100NF-0603SMT
LFE3-35E-FN484CES
U1F
PB10A V6 PB10B U7 PB11A Y6 PB11B AA6 PB13A U8 PB13B T8 PB16A R9 PB16B T9
PB2A AB3 PB2B AB4 PB4A W4 PB4B Y5 PB5A AA4
PB5B AA5 PB7A W5
PB7B W6
PB8A AB5 PB8B AB6
PL36A/LDQ41 L3 PL36B/LDQ41 L2
PL38A/PCLKT6_0/LDQ41 L4
PL38B/PCLKC6_0/LDQ41 M4
PL39A/LDQ41 M2 PL39B/LDQ41 M1
PL41A/LDQS41_P M5
PL41B/LDQS41_N N6
PL42A/LDQ41 N2
PL42B/LDQ41 N1
PL44A/VREF1_6/LDQ41 N4 PL44B/VREF2_6/LDQ41 P4
PL45A/LDQ50 N3 PL45B/LDQ50 P3 PL47A/LDQ50 N5 PL47B/LDQ50 P6 PL48A/LDQ50 P1 PL48B/LDQ50 R1
PL50A/LDQS50_P P5
PL50B/LDQS50_N R6
PL51A/LDQ50 R3 PL51B/LDQ50 R2 PL53A/LDQ50 U1 PL53B/LDQ50 U2
PL53E_A/LLM1_GPLLT_FB_A T2
PL53E_B/LLM1_GPLLT_FB_B T1
PL53E_C/LLM1_GPLLT_IN_A T3
PL53E_D/LLM1_GPLLT_IN_B U3
PL56B/LDQ59 P7
PL57A/LDQ59 V1 PL57B/LDQ59 W1
PL59A/LDQS59_P R7
PL59B/LDQS59_N T7
PL60A/LDQ59 V3
PL60B/LDQ59 W3
PL62A/LDQ59 R4 PL62B/LDQ59 T5 PL63A/LDQ68 W2 PL63B/LDQ68 Y1 PL65A/LDQ68 T4
PL65B/LDQ68 U4
PL66A/LDQ68 AA1 PL66B/LDQ68 Y2
PL68A/LDQS68_P T6
PL68B/LDQS68_N U5
PL69A/LDQ68 Y3 PL69B/LDQ68 AA2
PL71A/LDQ68 V4
PL71B/LDQ68 V5
VCCIO6 P8 VCCIO6 N7
VTT6 M6
C100 10NF-0402SMT
0
R94
C110
100NF-0603SMT
R106
4_75K-0603SMT
C115
100NF-0603SMT
0
R85
0
R77
C95
100NF-0603SMT
FB12
Z-600 ohm / 74279265
12
0
R80
C104
100NF-0603SMT
C131
100NF-0603SMT
0
R96
0
R84
C116
10uF/6V3/X7R-0805SMT
0
R89
C96
10NF-0402SMT
12
C94
10uF/6V3/X7R-0805SMT
C103
10uF/6V3/X7R-0805SMT
C99 10NF-0402SMT
R104
C118
100NF-0603SMT
C242
100NF-0402SMT
FB9
Z-600 ohm / 74279265
1 2
C107
100NF-0603SMT
C106
10uF/6V3/X7R-0805SMT
C98 10NF-0402SMT
12
0
R88
R105 4_99K-0402SMT
RLP-100
C126 100NF-0603SMT
TP7
0
R76
C105
100NF-0603SMT
0
R75
TP8
C124
100NF-0603SMT
C97 10NF-0402SMT
12
C102
100NF-0603SMT
0
R79
FB7
Z-600 ohm / 74279265
1 2
R100
4_7K-0402SMT
Q5
BCP69-16
1
32
4
C130
100NF-0603SMT
0
R82
C111 27pF-0603SMT
C125
10uF/6V3/X7R-0805SMT
C108
10NF-0402SMT
FB10
Z-600 ohm / 74279265
1 2
0
R87
J10 HEADER 2
1 2
0
R93
C119
100NF-0603SMT
R102
1K-0402SMT
R98
0R-0402SMT
C113
100NF-0603SMT
C241
100NF-0402SMT
C112 27pF-0603SMT
R73
100R-0402SMT
C101
10uF/6V3/X7R-0805SMT
FB13
Z-600 ohm / 74279265
12
C123
10uF/6V3/X7R-0805SMT
R83
20R-0402SMT
R103 4_7K-0402SMT
R101
4_7K-0402SMT
FB11
Z-600 ohm / 74279265
12
FB8
Z-600 ohm / 74279265
1 2
4_7UF-16V-0805SMT
C127
Y2
25MHZ CRYSTAL
C120
100NF-0603SMT
0
R86
C117
10uF/6V3/X7R-0805SMT
0
R91
1 2 3 6 4 5 7 8
RJ45
Gr/Yel Yel
0826-1X1T-43-F
J9B
2_MDCCT
21
2_MDIC-
22
2_MDIC+
23
2_MDIB+
24
2_MDIB-
25 2_MDIBCT 26
2_MDDCT
27 2_MDID+ 28
2_MDID-
29
2_MDIA-
30
2_MDIA+
31
2_MDACT
32
2_LED1- 33
2_LED1+ 34
2_LED2- 35
2_LED2+ 36
2_SHLD1 37
2_SHLD2 38
R99
R74 100R-0402SMT
R92
20R-0402SMT
0
R78
R180
1_8K-0402SMT
C121
100NF-0603SMT
0
R95
0
R81
C129
100NF-0603SMT
C109
100NF-0603SMT
U9
88E1119R_72QFN
AVDDX
19
CTRL18
20
NC
21
MDIN[3]
22
MDIP[3]
23
AVDD
24
AVDD
25
MDIN[2]
26
MDIP[2]
27
MDIN[1]
28
MDIP[1]
29
AVDD
30
AVDD
31
AVDD
32
MDIN[0]
33
MDIP[0]
34
EPAD
73
CRS 54
COL 53
MDC 52
DVDD 51
VDDO 50
MDIO 49
TDO 48
TDI 47
TCK 46
TMS 45
TRST_n 44
DVDD 43
XTAL_OUT 42
XTAL_IN 41
AVDDC 40
HSDACP 39
TXD[2] 72
TXD[1] 71
TXD[0] 70
TX_EN 69
VDDOR 68
TX_CLK 67
RXD[7] 66
RXD[6] 65
RXD[5] 64
RXD[4] 63
RXD[3] 62
RXD[2] 61
RXD[1] 60
RXD[0] 59
VDDOR 58
RX_CLK 57
TXD[3]
1
TXD[4]
2
TXD[5]
3
TXD[6]
4
TXD[7]
5
GTX_CLK
6
DVDD
7
COMA_n
8
CLK125
9
LED[0]
10
LED[1]
11
VDDO
12
LED[2]
13
RESET_n
14
DIS_REG12
15
DVDD
16
AVDDR
17
AVDDR
18
TSTPT
35
RSET
36
HSDACN 38
AVDDC 37
RX_DV 56
RX_ER 55