Lattice Semiconductor ECP5 Versa User manual

ECP5 Versa Development Board User Guide
FPGA-EB-02021 Version 2.3, September 2018

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ECP5 Versa Development Board
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Introduction
The ECP5™ Versa Development Board allows designers to investigate and experiment with the features of the
ECP5 Field-Programmable Gate Array. The features of the ECP5 Versa Development Board can assist engineers
with rapid prototyping and testing of their specific designs. The ECP5 Versa Development Board is part of the
ECP5 Versa Development Kit. The guide is intended to be referenced in conjunction with demo user guides to
demonstrate the ECP5 FPGA.
Figure 1. ECP5 Versa Development Board, Top Side
JTAG
Interface
PCI Express x1
On-Board
Clock
Management
12 V DC
Power Input
Expansion Connectors
DDR3
Memory
SERDES Test
SMA Connectors
LED
Display
Push-buttons
User
Switches
Status LEDs
SPI Flash
Configuration
Memory
Configuration
Mode Switches
ECP5
Device
USB Programming
Dual RJ45
Ethernet Ports
Dual RJ45
Ethernet Ports
Features
• Half-length PCI Express form-factor
—Allows demonstration of PCI Express x1 interconnection
• Electrical testing of one full-duplex SERDES channel via SMA connections
• USB-B connection for UART and device programming
• Two RJ45 interfaces to 10/100/1000 Ethernet to RGMII
• On-board Boot Flash
—128M Serial SPI Flash
• DDR3-1866 memory components (64Mb/x16)*
• Expansion mezzanine interconnection for prototyping
• 14-segment alpha-numeric display
• Switches, LEDs and displays for demo purposes
•Diamond
®programming support
• On-board reference clock sources

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ECP5 Versa Development Board
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The contents of this user guide include top-level functional descriptions of the various portions of the evaluation
board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics.
*Note: The ECP5 FPGA supports DDR3 memory at data rates up to 800 Mbps.
Caution: The ECP5 Versa Development Board contains ESD-sensitive components. ESD safe practices should be
followed while handling and using the evaluation board.
ECP5 Device
This board features an ECP5 FPGA with a 1.1 V core supply. It can accommodate all pin-compatible ECP5 devices
in the 381 ball caBGA package. A complete description of this device can be found in FPGA-DS-02012, ECP5
Family Data Sheet.
Note: The connections referenced in this document refer to the LFE5UM-45F-8BG381C device.
Applying Power to the Board
The ECP5 Versa Development Board is ready to power on. The board can be supplied with power from a PCI
Express host system or standalone with an external wall power module.
The 12 V DC input power source is fused with a surface mounted fuse, as noted in Ta bl e 1.
Table 1. Board Power Supply Fuses (See Appendix A, Sheet 2, Figure 11- Voltage Regulators)
Fuse Designator Description
F1 12 V Input Supply Fuse
The board may be plugged into a host PC. Only plug the board into a PCI Express slot when the system is powered
off. Once inserted, the PC can be safely powered on.
Using the evaluation board outside of a PC chassis supply requires the factory-supplied wall supply module. Use of
other supplies is not suggested.
Figure 2. Power Distribution Scheme (See Appendix A, Sheet 2, Figure 11- Voltage Regulators)
12 V, 5 A fused
Status LED: D13
VCC Core: 1.1 V, 1.35 A
Status LED: D10
1.5 V, 1.1 A
Status LED: D11
3.3 V, 1.35 A
Status LED: D9
2.5 V, 1.1 A
Status LED: D31
SERDES VCCHTX0: 1.1 V, 0.5 A
SERDES VCCA0: 1.1 V, 0.5 A
Status LED: D12
SW
EN
SW
EN
LDO
SW
EN
SW
EN
LDO

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ECP5 Versa Development Board
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Programming/FPGA Configuration
The ECP5 Versa Development Board has a built-in download controller for programming the ECP5 FPGA. The
built-in module consists of a USB Type-B connector and a USB UART device. To use the built-in download cable,
simply connect a standard USB cable (a USB-B to USB-A cable is included with the ECP5 Versa Development Kit)
from J2 to your PC (with Diamond programming software installed). The USB hub on the PC will detect the addition
of the USB function, making the built-in cable available for use with the Diamond programming software. The USB
cable is connected in parallel to J3.
Alternate Programmer Download Interface
J3 is a 10 pin JTAG connector that is provided for use with an external Lattice download cable (available sepa-
rately). A USB download cable can be attached to the board using J3 to interface with the FPGA (U1).
Note: Resistors R38, R33, R32 and R36 need to be removed for programming with J3.
The same interface can be used to access the ispClock 5406D clock device (U13) by reconfiguring the jumpers on
J50 (See Appendix A, Sheet 3, Figure 12 - Programming). U13 is factory-programmed for use with the reference
designs and should only be altered for customized designs.
Table 2. JTAG Connector Pinout (J3) (See Appendix A, Sheet 3, Figure 12 - Programming)
Pin Function
1PWR
2TDO
3TDI
4PROGRAMn
5 N/C
6TMS
7GND
8TCK
9DONE
10 INITn
Diamond Programmer Requirements
Note: This board includes the built-in download module and only requires the USB cable included with the board.
After initial board setup, use the following procedure to program the board. Instructions assume that Diamond Pro-
grammer software has been installed on a local PC.
Requirements:
• PC with Diamond Programmer 3.5.1 (or later) programming software, installed with appropriate drivers (USB
driver for USB cable).
Note: An option to install these drivers is included as part of the Diamond Programmer setup.

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ECP5 Versa Development Board
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Setting the Configuration Mode
The ECP5 device on the ECP5 Versa Development Board supports a variety of configuration modes, including
1149.1 JTAG and Master SPI. Refer to TN1260, ECP5 sysCONFIG Usage Guide. On the PCB version Rev B, use
the CFG Setting Dip Switch SW4 described in Ta bl e 3.
Table 3.
Configuration Mode CFG[2:0] SW4.3 SW4.2 SW4.1
1149.1 JTAG only 000 Down Down Down
Slave SPI 001 Down Down Up
Master SPI 010 Down Up Down
SCM (Slave_Serial) 101 Up Down Up
SCM (Slave_Parallel) 111 Up Up Up
CFG[2:0] Selection – Rev B
Board Programming
Configuration Status Indicators
(See Appendix A, Sheet 3, Figure 12 - Programming)
Figure 3. ECP5 Status LEDs and Push-button Controls
The LEDs indicate the configuration status of the ECP5 FPGA.
•D17 (red) illuminated indicates that programming was aborted or reinitialized, driving the INITN output low.
•D20 (green) illuminated indicates the successful completion of configuration by releasing the open collector
DONE output pin.
•D19 (red) illuminated indicates that PROGRAMN is low.
•D18 (red) illuminated indicates that GSRN is low.

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ECP5 Versa Development Board
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PROGRAMN and GSRN
These push-button switches assert/de-assert the logic levels on PROGRAMN (SW2) and GSRN (SW1). Depress-
ing the button drives a logic level “0” to the device.
Programming Serial SPI Flash Memory
A serial SPI (16-pin TSSOP, 128M) Flash memory device (U52) is on-board for non-volatile configuration memory
storage. A Micron N25Q128A device is populated on-board.
The Serial SPI Flash memory device can be configured easily via the ECP5 JTAG port. This mode enables the
FPGA to be programmed at power-up or assertion of PROGRAMN with a bitstream stored in the memory device.
1. Connect the ECP5 Versa Development Board.
2. Scan the board or select the LFE5UM-45F device in the ECP5UM device family.
3. From the Edit pull down menu select Device Properties. Set the Access mode to SPI Flash Background Pro-
gramming and Operation to SPI Flash Erase, Program, Verify.
Figure 4. Diamond Programmer Main Screen
4. Under the SPI Flash Options, select Family to SPI Serial Flash, Vendor to Micron, Device to SPI-N25Q128A,
Package to 16-pin SO16.

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ECP5 Versa Development Board
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Figure 5. Device Properties Dialog Box
5. Click OK in the Device Properties dialog box. You will return to the main configuration screen.
6. Set J50 jumper to ECP5 programming (see Appendix A, sheet 3 "Programming").
7. Ensure the Configuration Mode is set to Master SPI using DIP Switch SW4 (see Ta bl e 3).
8. From the main programming window, select Program from the top toolbar. This begins the SPI Serial Flash
programming. Note that the SPI Flash Background Programming operation is only possible when the ECP5
device is either erased or the active design has the MASTER_SPI_PORT mode enabled. For more details see
TN1260, ECP5 sysCONFIG Usage Guide.

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ECP5 Versa Development Board
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On-Board Clock Capabilities
(See Appendix A, Sheet 9, Figure 18 - Reference Clock Generator)
The ECP5 Versa Development Board allows for several clock source options. Some of these options are controlled
via the ispClock5406D programmable clock manager device. The ispClock5406D enables the reference clock from
the PCI Express interface to provide a reference clock to the SERDES. This is true only when the board is in a PCI
Express host socket. When the board is not in a PCI Express host socket, the clock will be supplied by a 156.25
MHz clock on-board oscillator. Both clock inputs can be fanned out to the dedicated SERDES reference inputs,
FPGA inputs, and to the expansion connectors. The factory default programming only connects the SERDES refer-
ence clock inputs. Factory-defined demonstration designs will control and manage the clock.
Figure 6. Clock Controller Scheme
PCIE_PRSNT#
PCI Express
156.25 MHz
On-board
Oscillator
FPGA Clock
SERDES D0
Reference
Clock
SERDES D1
Reference
Clock
Expansion Interface
Clock(X3)
PCLKT0
A4
PCLKC0
A5
REFCLKP_D0
Y11
REFCLKN_D0
Y12
REFCLKP_D1
Y19
REFCLKN_D1
W20
Factory Default
Clock Programming
1
0

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ECP5 Versa Development Board
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General Purpose Clock Source
An on-board 100 MHz LVDS oscillator is provided for general purpose use. This clock source is connected to differ-
ential inputs P3 and P4 and must be used as LVDS inputs to the FPGA. This pin pair also provides optimal inter-
face to the FPGA PLL for customized use.
The PCI Express add-in card specification requires add-in boards to include capabilities to tell the host of its pres-
ence. The ECP5 Versa Development Board allows this optional connection via a board jumper. Using the board
with a PCI Express host requires the setting shown in Figure 7 below.
Figure 7. PCI Express PRSNT Control Connection
J4
1 2
3 4
5 6
PCI Express PRSNT
Jumper Selector
SERDES
The ECP5 Dual Channel Unit (DCU) SERDES FPGA is utilized on the board for several purposes. DCU0, Channel
0 is provisioned to provide a single, full-duplex PCI Express channel. The high-speed signals are connected to the
PCI Express edge connection. DCU0, Channel 1 is connected to the SMA connectors for external electrical dem-
onstrations.
Table 4. PCI Express Channel Interconnections
Signal Name SERDES Port FPGA Ball Number
PETp0 HDRXP0_D0CH0 Y5
PETn0 HDRXN0_D0CH0 Y6
PERp0 HDTXP0_D0CH0 W4
PERn0 HDTXN0_D0CH0 W5
Table 5. SMA Test Interconnections
Connector SERDES Port FPGA Ball Number
J5 HDRXP0_D0CH1 Y7
J6 HDRXN0_D0CH1 Y8
J7 HDTXP0_D0CH1 W8
J8 HDTXN0_D0CH1 W9

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ECP5 Versa Development Board
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FPGA Test Pins
(See Appendix A, Sheet 8, Figure 17 - LEDs and Switches)
General Purpose DIP Switches
General purpose FPGA pins are available for user applications. FPGA pins are connected to switch SW3, a SPST
slide-actuated DIP switch. The switches are connected to logic level 0 when moved to the ON position. Switch posi-
tion 1 is indicated with an arrow. Inputs 1-4 are within a 1.5 V bank and inputs 5-8 are within a 2.5 V bank. The user
must program inputs 1-4 to be the LVCMOS15 type and inputs 5-8 to be the LVCMOS25 type in the design.
Figure 9 shows the switches. Note the silk marking associated with SW3-7 is incorrect in revision B, SW3-7 is
mapped to K19, per Ta b le 6.
Figure 8. ECP5 Versa Development Board LEDs and Switches
The designated pins are connected according to Table 6.
Table 6. FPGA Ball to DIP Switch Position
FPGA Ball Number SW3 DIP Switch Position
H2 1
K3 2
G3 3
F2 4
J18 5
K18 6
K19 7
K20 8

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ECP5 Versa Development Board
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General Purpose LEDs
(See Appendix A, Sheet 8, Figure 17 - LEDs and Switches)
The LEDs provided on the ECP5 Versa Development Board are connected to general purpose FPGA I/Os. These
LEDs provide status for user designs and must be included in the design. The LEDs illuminate when the FPGA out-
put is driven LOW. Ta b l e 7 shows the LED and associated FPGA pins. These pins are within an I/O bank con-
nected to 2.5 V and the user should program these to be LVCMOS25 type outputs in the design.
Table 7. LED Definitions
LED Designator FPGA Ball Number LED Color
D25 E16 Ye l l o w
D24 D17 Ye l l o w
D22 D18 Green
D21 E18 Green
D26 F17 Red
D27 F18 Red
D28 E17 Red
D29 F16 Red
Alpha-numeric LED Display
(See Appendix A, Sheet 8, Figure 17 - LEDs and Switches)
A 14-segment alpha-numeric display is provided on the board (D23). These LED segments are connected to gen-
eral-purpose FPGA I/Os. The LEDs must be included in the FPGA design. The LEDs illuminate when the FPGA
output is driven LOW. Ta b l e 8 shows the LED and associated FPGA pins. These pins are within an I/O bank con-
nected to 2.5 V and the user should program these to be LVCMOS25 outputs in the design.
Figure 9. 14-Segment Display

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ECP5 Versa Development Board
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Table 8. Alpha-numeric LED Definitions
Display FPGA Ball Number Display FPGA Ball Number
AM20 JN18
BL18 KP17
CM19 LN17
DL16 MP16
EL17 NR16
FM18 PR17
GN16 DP U1
HM17
DDR3 Memory Device
(See Appendix A, Sheet 7, Figure 16 - DDR3 Memory)
• The ECP5 Versa Development Board is equipped with an SDRAM memory device (1.5 V, 64 Mb/x16, 96-ball
FBGA, 933 MHz, DDR3-1866) such as the Micron MT41K64M16TW-107:J device.
• The DDR3 memory includes a 16-bit wide memory controller interface.
• The board includes termination of data, address and command signals. It includes all power and external compo-
nents needed to demonstrate the memory controller of the ECP5 device.
• A 100 MHz on-board clock oscillator is available to provide a DDR3 reference clock.

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ECP5 Versa Development Board
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Table 9. DDR3 Memory Controller Interconnections
DDR3 Signal
FPGA Ball
Number DDR3 Signal
FPGA Ball
Number
DQ0 L5 A0 P2
DQ1 F1 A1 C4
DQ2 K4 A2 E5
DQ3 G1 A3 F5
DQ4 L4 A4 B3
DQ5 H1 A5 F4
DQ6 G2 A6 B5
DQ7 J3 A7 E4
DQ8 D1 A8 C5
DQ9 C1 A9 E3
DQ10 E2 A10 D5
DQ11 C2 A11 B4
DQ12 F3 A12 C3
DQ13 A2 K_0 M4
DQ14 E1 K_0# N5
DQ15 B1 CAS# L1
DQS0 K2 BA0 P5
DQS0# J1 BA1 N3
DQS1 H4 BA2 M3
DQS1# G5 ODT L2
CE0 N2 CS0# K1
RAS# P1 WE# M1
CLKP P3 VREF K5
CLKN P4 DM0 J4
RST# N4 DM1 H5

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ECP5 Versa Development Board
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Ethernet Interfaces
(See Appendix A, sheets 5 and 6 "10/100/1000-T PHY#x/RJ45")
Two Marvell 88E1512 Gigabit Ethernet transceiver devices (U14 and U15) are included on the board. These phys-
ical layer devices support 1000BASE-T, 100BASE-TX, and 10BASE-T applications via a standard media interface
to a dual RJ45 connection. The RJ45 connection includes network magnetics providing the proper signal condition-
ing, electro-magnetic interference suppression and signal isolation. Each connector includes two LEDs which are
controlled by the 88E1512 devices. Detailed descriptions are available in the Marvell device data sheet.
Table 10. PHY Status Indicators
LED Status Description
RJ45 (Yellow) Data RX/TX
RJ45 (Green/Orange) Link State
Each Marvell 88E1512 device communicates via a RGMII interface to the ECP5 device.
Table 11. FPGA GPIO to RGMII Interfaces
Signal Phy1 Phy2
CLK125 L19 J20
CLK125Pll U16 C18
Config T17 G20
Resetn U17 F20
TXCLK P19 C20
TX_D0 N19 J17
TX_D1 N20 J16
TX_D2 P18 D19
TX_D3 P20 D20
TXCTRL R20 E19
RXCLK L20 J19
RX_D0 T20 G18
RX_D1 U20 G16
RX_D2 T19 H18
RX_D3 R18 H17
RXCTRL U19 F19
MDIO U18 H20
MDC T18 G19

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ECP5 Versa Development Board
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Table 12. Expansion Connections
X3 Expansion Connector X4 Expansion Connector
Pin Signal
FPGA Ball
NumberPin Signal
FPGA Ball
Number
1GND —1RESOUT# A8
2NC —2GND —
32V5 —3IO0 A12
4IO29 B19 4IO1 A13
5IO30 B12 5IO2 B13
6IO31 B9 6IO3 C13
7IO32 E6 7IO4 D13
8IO33 D6 8IO5 E13
9IO34 E7 9IO6 A14
10 IO35 D7 10 IO7 C14
11 IO36 B11 11 IO8 D14
12 IO37 B6 12 IO9 E14
13 IO38 E9 13 IO10 D11
14 IO39 D9 14 IO11 C10
15 IO40 B8 15 IO12 A9
16 IO41 C8 16 IO13 B10
17 IO42 D8 17 IO14 D12
18 IO43 E8 18 IO15 E12
19 IO44 C7 19 GND —
20 IO45 C6 20 3V3 —
21 5VIN —21 IO16 B15
22 GND —22 GND —
23 2V5 —23 IO17 C15
24 GND —24 GND —
25 3V3 —25 IO18 D15
26 GND —26 GND —
27 3V3 —27 IO19 E15
28 GND —28 IO20 A16
29 OSC —29 IO21 B16
30 GND —30 GND —
31 CLKIN A10 31 IO22 C16
32 GND —32 IO23 D16
33 CLKOUT E11 33 IO24 B17
34 GND —34 GND —
35 3V3 —35 IO25 C17
36 GND —36 IO26 A17
37 3V3 —37 IO27 B18
38 GND —38 CARDSEL# A7
39 3V3 —39 IO28 A18
40 GND —40 GND —

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ECP5 Versa Development Board
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References
• FPGA-DS-02012, ECP5 and ECP5-5G Family Data Sheet
• FPGA-UG-02006, PCI Express Demos for the ECP5 and ECP5-5G Versa Development Board
• UG97, DDR3 Demo for the ECP5 Versa Development Board
• UG93, SERDES Eye Demo for the ECP5 Versa Development Board
• UG92, SEU (Single Event Upset) Demo for the ECP5 Versa Development Board
Ordering Information
Description Ordering Part Number
China RoHS Environment-Friendly
Use Period (EFUP)
ECP5 Versa Development Board LFE5UM-45F-VERSA-EVN
Technical Support Assistance
Submit a technical support case through www.latticesemi.com/techsupport.
Revision History
Date Version Change Summary
September 2018 2.3 Updated document number from EB98 to FPGA-EB-02021.
Updated ECP5 and ECP5-5G Family Data Sheet number to FPGA-DS-
02012.
Updated PCI Express Demos for the ECP5 and ECP5-5G Versa Devel-
opment Board number to FPGA-UG-02006.
March 2017 2.2 Updated Features section.
Added note to the “DDR3-1866 memory components (64Mb/x16)” fea-
ture.
Updated Programming Serial SPI Flash Memory section.
Added step 7 to the procedure.
November 2015 2.1 Updated Introduction section. Indicated Dual RJ45 Ethernet ports and
corrected USB Programming callout in Figure 1, ECP5 Versa Develop-
ment Board, Top Side.
Updated General Purpose LEDs section. Revised FPGA ball numbers
in Ta bl e 7, LED Definitions.
Updated Appendix A. Schematics section. Revised LEDs signal map in
Figure 17, LEDs and Switches.
Updated Appendix B. Bill of Materials section. Revised description of
item 111.
Updated Setting the Configuration Mode section in Appendix C.
Changed Figure 20, CFG[2:0] Setting Resistor Field – Revision A.
August 2015 2.0 Updated to support Rev B of development board.
July 2015 1.1 Added Setting the Configuration Mode section.
Updated Technical Support Assistance section.
Added ECP5 Versa Development Board Bill of Materials section.
March 2015 1.0 Initial release.
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.

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ECP5 Versa Development Board
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Appendix A. Schematics
Figure 10. Board Block Design
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
Power Device Power Pins
Programming 3.3V SPI
PCSA
Bank 8
ECP5
Bank 0
Bank 3
FPGA
Bank 6 Bank 7
Bank 1
Bank 2
SERDES
Designator U1 is the FPGA DUT.
PCIe X1 CH#0
CLK5406
REFERENCE
CLOCKS
PCIe RefClk 156.25M OSC
Expansion Port- 3.3V
1.5V 16-Bit DDR3
SERDES D0 RefClk General Clk
2.5V RGMII PHY#1 2.5V RGMII PHY#2
Expansion Port-3.3V
SMA Test CH#3
Expansion Clk
PLL
100.00M DIFF OSC
LED SEGMENT ARRAY
USER DIP SWITCH
USER LEDS
Revision History: Nov 13, 2014 Rev A Final Design JPB March 27, 2015 Rev B Final Design EK
Bank 2 Bank 6,7
Date: Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsu[email protected]
Board Rev
Project
B
B
111
Board Block Diagram
ECP5 VERSA Eval Board
B
Friday, August 21, 2015
Date: Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsu[email protected]
Board Rev
Project
B
B
111
Board Block Diagram
ECP5 VERSA Eval Board
B
Friday, August 21, 2015
Date: Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsu[email protected]
Board Rev
Project
B
B
111
Board Block Diagram
ECP5 VERSA Eval Board
B
Friday, August 21, 2015

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ECP5 Versa Development Board
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Figure 11. Voltage Regulators
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
Core Power
0.45 v drop at 500 mA max
+1.5v 1.1 A
POWER INPUT
+11vto +16v
1.2v/ms
1.2v/ms
1.2v/ms
Voltage Regulators
+3.3 v 1.35 A
SW
3_3V, +3.3 V, 1.35 A
Power Supply Block Diagram
12_0V
EN
+1.1 v 1.35 A
Vout = 0.8*(R15/R21+1) = 1.10 v
SW
(5A fused)
SW 1_5V, +1.5 V, 1.1 A EN
VCC_CORE, +1.1 V, 1.35 A
SW
Vout = 0.8*(R8/R13+1) = 3.28 v Vout = 0.8*(R16/R17+1) = 1.51 v
LDO SERDES VCCHTX0, +1.1 V, 0.5A
EN
DDR3
3.3V
1.2v/ms
+2.5v 1.1 A
Vout = 0.8*(R7/R9+1) = 2.52 v
2.5V
2_5V, +2.5V, 1.1 A
1.1V VCC_CORE 1.5V3.3V
1.1V Analog
12VINGOOD
2.5V
Schematic symbols rev 4.1 Schematic symbols rev 4.1
LDO SERDES VCCA0, +1.1 V, 0.5A
EN
SERDES VCCHTX 1.2VPower
+1.2 v 500 mA
SERDES VCCA 1.1VPower
+1.1 v 500 mA
NC NC NC NC
Right angle mount, cable to board edge
2_5V Current 3_3V Current
1_5V Current
1.5V
1_1V Current
VCCA current VCCHTX current
VCCA1 VCCA0
VCCAUX
VCCHTX0
12_0V
12_0VIN12_0V
12_0V
3_3V3_3V
3_3V2_5V
VCC_CORE
3_3V3_3V
1_5V
2_5V
VCC_CORE
3_3V12_0V
VCC_CORE
12_0V
1_5V
12_0V
VCCA
12_0V
12_0VIN
2_5V
2_5V 2_5V
VCCA VCCHTX
VCCA1
VCCA0
VCCA0
VCCA1 VCCHTX1
3_3V
Date: Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsu[email protected]
Board Rev
Project
C
B
112
Voltage Regulators
ECP5 VERSA Eval Board
B
Friday, August 21, 2015
Date: Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsu[email protected]
Board Rev
Project
C
B
112
Voltage Regulators
ECP5 VERSA Eval Board
B
Friday, August 21, 2015
Date: Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsu[email protected]
Board Rev
Project
C
B
112
Voltage Regulators
ECP5 VERSA Eval Board
B
Friday, August 21, 2015
R7 21_5K-0603SMT 1%
R19
30_1K-0402SMT
C23
100NF-0402SMT
TP5
C6
100NF-0402SMT
C392
10uF-6.3V-0805SMT
RLP-133
R22
1_8K-1206SMT
TP22
C394
1UF-16V-0805SMT
RLP-133
U53
LT3085
OUT_1 1 OUT_2 2 OUT_3 3
SET 4
IN_7
7IN_8 8
IN_6
6
VCtrl
5
Pad 9
C41
22uF,6.3V-0805SMT
RLP-133
C5
10NF-0402SMT
U54
LT3085
OUT_1 1 OUT_2 2 OUT_3 3
SET 4
IN_7
7IN_8 8
IN_6
6
VCtrl
5
Pad 9
R67
0.1
cr2010_alt1
1%
R28
10K-0603SMT
D2
1N4448W
21
R20
20K-0402SMT
R17 16_9K-0603SMT 1%
LFE5UM-45F-BG381
U1I
GND
B14
GND
B7
GND
C19
GND
D4
GND
F13
GND
F14
GND
F7
GND
F8
GND
G10
GND
G11
GND
G12
GND
G13
GND
G14
GND
G15
GND
G17
GND
G4
GND
G6
GND
G7
GND
G8
GND
G9
GND
H19
GND
J10
GND
J11
GND
J12
GND
J14
GND
J2
GND
J7
GND
J9
GND
K10
GND
K11
GND
K12
GND
K14
GND
K15
GND
K6
GND
K7
GND
K9
GND
L10
GND
L11
GND
L12
GND
L9
GND
M10
GND
M11
GND
M12
GND
M14
GND
M16
GND
M2
GND
M7
GND
M9
GND
N14
GND
N15
GND
N6
GND
N7
GND
P11
GND
P12
GND
P13
GND
P14
GND
P7
GND
P8
GND
R19
GNDA U10 GNDA U11 GNDA U12 GNDA U13 GNDA U14 GNDA U7 GNDA U8 GNDA U9 GNDA V12 GNDA V13 GNDA V14 GNDA V15 GNDA V16 GNDA V19 GNDA V20 GNDA V5 GNDA V6 GNDA V7 GNDA V8 GNDA V9 GNDA W12 GNDA W15 GNDA W16 GNDA W19 GNDA W6 GNDA W7
C8
100NF-0402SMT
R66
0.1
cr2010_alt1
1%
R18
63_4K-0402SMT
1%
TP20
G
D10
LED_GREEN_0603
U4 LT3508EUF
FB2 18
VC2 19
PG2 20
RT/SYNC
22
SHDN21
FB1
1
TRACK/SS1
2
BOOST1
7
SW1
8
VIN19
VC1
24
VIN210
PG1
23
SW211
BOOST2 12
TRACK/SS2 17
GND5
25
GND6
13
GND7
14
GND4
6GND3
5GND2
4GND1
3
GND8
15
GND9
16
C2
10NF-0402SMT
TP4
FB8
BLM41PG600SN1
L1
4.7uH-SPD62R-472M
TP21
R140 0.01
cr2512_alt11%
C20
10NF-0402SMT
C33
10NF-0402SMT
TP18
R12
51K-0402SMT
U3 LT3508EUF
FB2 18
VC2 19
PG2 20
RT/SYNC
22
SHDN21
FB1
1
TRACK/SS1
2
BOOST1
7
SW1
8
VIN19
VC1
24
VIN210
PG1
23
SW211
BOOST2 12
TRACK/SS2 17
GND5
25
GND6
13
GND7
14
GND4
6GND3
5GND2
4GND1
3
GND8
15
GND9
16
R23 1_8K-1206SMT
TP23
R184
121K-0603SMT
D5
1N4448W
21
C58
22uF,6.3V-0805SMT
RLP-133
C9
100NF-0402SMT
R15
3_83K-0603SMT
1%
TP19
C60
10pF-0402SMT
DNI
C45
330pF-0402SMT
C24
1UF-16V-0805SMT
C19
1UF-16V-0805SMT
R13 11_5K-0603SMT 1%
C42
22uF,6.3V-0805SMT
RLP-133
F1
F1251CT-ND
5A Fast-Blo SMT Socketed Fuse
LFE5UM-45F-BG381
U1J
VCC
H10
VCC
H11
VCC
H12
VCC
H13
VCC
H8
VCC
H9
VCC
J13
VCC
J8
VCC
K13
VCC
K8
VCC
L13
VCC
L8
VCC
M13
VCC
M8
VCC
N10
VCC
N11
VCC
N12
VCC
N13
VCC
N8
VCC
N9
VCCA0 T6 VCCA0 U6 VCCA1 T15 VCCA1 U15
VCCAUX F15 VCCAUX F6 VCCAUX P15 VCCAUX P6
VCCAUXA0 V10 VCCAUXA0 V11 VCCAUXA1 V17 VCCAUXA1 V18
RESERVED2 W11 RESERVED1 W10
NC1 K16 NC2 K17
R29
10K-0603SMT
C1
10NF-0402SMT
TP15
R179 220R-0603SMT C51
10uF,25V-1206SMT
RLP-134
R185
110K-0603SMT
C54
22uF,6.3V-0805SMT
RLP-133
R63 0.1
cr2010_alt1
1%
C103
1UF-16V-0805SMT
+
C18
22UF-16V-TANTBSMT
D3
DFLS220L
12
C62
330pF-0402SMT
C32
1NF-0402SMT
C31
1NF-0402SMT
R26 220R-0603SMT
G
D9
LED_GREEN_0603
D1
1N4448W
21
TP24
TP2
G
D31
LED_GREEN_0603
C21
10NF-0402SMT
C3
10NF-0402SMT
R25
1_8K-1206SMT
L4
4.7uH-SPD62R-472M
+
C104
22UF-16V-TANTBSMT
C64
22uF,6.3V-0805SMT
RLP-133
C28
100NF-0402SMT
C101
1UF-16V-0805SMT
G
D12 LED_GREEN_0603
R27
10K-0603SMT
C38 220NF-0402SMT 16V
C35
1UF-16V-0805SMT
C47
10pF-0402SMT
C4
10NF-0402SMT
R8
35_7K-0603SMT
1%
+
C102
22UF-16V-TANTBSMT
C53 220NF-0402SMT 16V
C55
22uF,6.3V-0805SMT
RLP-133
R24
1_8K-1206SMT
G
D13
LED_BLUE_0603
C29
10NF-0402SMT
R14 51K-0402SMT
D8
DFLS220L
12
R11
34K-0402SMT
1%
C40
22uF,6.3V-0805SMT
RLP-133
C61
10pF-0402SMT
DNI
C43 1000pF-0402SMT
FB4
BLM41PG600SN1
C245
100pF-0402SMT
J11
PJ-002A Male Power Jack 2.1mm
1
3
2
R16
15K-0603SMT
1%
+
C25
22UF-16V-TANTBSMT
D4
DFLS220L
12
TP25
FB7
BLM41PG600SN1
C57 1000pF-0402SMT
C94
1NF-0402SMT
R70 0.1
cr2010_alt1
1%
Q2
2N2222/SOT23
3
1
2
R6 51K-0402SMT
L3
4.7uH-SPD62R-472M
R64
0.1
cr2010_alt1
1%
+
C36
22UF-16V-TANTBSMT
D14 SCHOTTKY/VISHAY-V12P10
C11
100NF-0402SMT
C52
220NF-0402SMT
16V
R10
51K-0402SMT
TP3
L2
4.7uH-SPD62R-472M
C27
1UF-16V-0805SMT
C30
100NF-0402SMT
Q3
2N2222/SOT23
3
1
2
C49
22uF,6.3V-0805SMT
RLP-133
D6
1N4448W
21
C59
330pF-0402SMT
C247
100NFX5R-0402SMT
R9
10K-0603SMT
1%
C56 1000pF-0402SMT
C34
100NF-0402SMT
TP16
C39 220NF-0402SMT 16V
TP1
C48
330pF-0402SMT
C50
22uF,6.3V-0805SMT
RLP-133
C248
100NFX5R-0402SMT
Q1
2N2222/SOT23
3
1
2
D7
DFLS220L
12
C7
100NF-0402SMT
C95
10NF-0402SMT
C46
10pF-0402SMT
R21
10K-0603SMT
1%
+
C26
22UF-16V-TANTBSMT
TP17
C246
100pF-0402SMT
C37
10uF,25V-1206SMT
RLP-134
C44 1000pF-0402SMT
C22
100NF-0402SMT
C391
1UF-16V-0805SMT
RLP-133
G
D11 LED_GREEN_0603
FB2
BLM41PG600SN1
C393
10uF-6.3V-0805SMT
RLP-133
FB3
BLM41PG600SN1
C63
22uF,6.3V-0805SMT
RLP-133

19
ECP5 Versa Development Board
®
Figure 12. Programming
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
FPGA GSRN PROGRAMN
DONE indicator will light when configuration is successfully completed INITN indicator will light if an error occurs during configuration programming
CONFIG Status LEDs
PROGRAMN & GSRN Pushbuttons
DONE
INITN
GSRN PROGRAMN
USB Download
Local JTAG
header (ispVM)
TMS TCK DONE INITn +3.3V TDI GND TDO PROGRAMn
Schematic symbols rev 4.1
Remove internal names in symbol?
Bank 8
128Mb SPI Flash
Place R187 near U1
ECP5 + ispCLOCK
ECP5 only
ispCLOCK only
Default Jumper Settings:1&2, 3&4, 5&6
GSRN
PROGRAMN
INITN
DONE
GSRN
PROGRAMN
USB1_CS
USB_N_iUSB_N
FTDI_TCK
FPGA_WRITEN
USB1_D
FPGA_CSN
USB_P
FPGA_CS1N
DONE
INITN
FTDI_TDO FTDI_TDI FTDI_TMS
USB_P_i
USB1_CS USB1_SK USB1_Q
JTAG_ACT
JTAG_ACT
UART_ACT
UART_ACT
PROGRAMN INITN DONE FPGA_WRITEN SpiCSSPIN FPGA_CSN FPGA_CS1N
SpiMCLK
ECP5_TDO ECP5_TDI FTDI_TMS FTDI_TCK SEG14
PROGRAMn DONE INITn
TXD_UART RXD_UART
CFG2 CFG0 CFG1
DQ3
DQ2 SpiMCLK
SpiSO
SpiSI SpiCSSPIN
GSRN CLK_RESETn SpiSO SpiSI SDA SCL DQ2 DQ3
ECP5_TDO
FTDI_TDI
FTDI_TDO
FTDI_TMS FTDI_TCK
ECP5_TDI
3_3V
3_3V
3_3V3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
FTVCC1_8V
FTVCC1_8V 3_3V
3_3V
3_3V
3_3V
3_3V
3_3V3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
RXD_UART [9] TXD_UART [9]
SEG14 [8] CLK_RESETn [9]
SDA [9]
SCL [9]
FTDI_TMS [9] FTDI_TCK [9]
ispCLOCK_TDI [9] ispCLOCK_TDO [9]
Date: Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: [e-mail]
Board Rev
Project
C
B
113
Programming
ECP5 VERSA Eval Board
B
Friday, August 21, 2015
Date: Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: [e-mail]
Board Rev
Project
C
B
113
Programming
ECP5 VERSA Eval Board
B
Friday, August 21, 2015
Date: Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: [e-mail]
Board Rev
Project
C
B
113
Programming
ECP5 VERSA Eval Board
B
Friday, August 21, 2015
R130 0R-0402SMT
LFE5UM-45F-BG381
U1G
VCCIO8
P10
VCCIO8
P9
CCLK/MCLK/SCK U3
CFG_0 U4 CFG_1 T4 CFG_2 R4
DONEY3
INITNV3
PB11A/D1/MISO/IO1 V2 PB11B/D0/MOSI/IO0 W2
PB13A/SN/CSN/SCAN_SHFT_ENT2
PB13B/CS1NU2
PB15A/HOLDN/DI/BUSY/CSSPIN/CENR2
PB15B/DOUT/CSON/ATB_FORCE R3
PB18A/WRITEN/ATB_SENSE T3
PB4A/D7/IO7 R1 PB4B/D6/IO6 T1
PB6A/D5/MISO2/IO5 U1 PB6B/D4/MOSI2/IO4 V1
PB9A/D3/IO3 W1 PB9B/D2/IO2 Y2
PROGRAMNW3
TCK/TEST_CLK T5
TDI R5
TDO V4
TMS U5
C72 100NF-0402SMT
R31
220R-0603SMT
R37 15K-0603SMT-DNI DNI
R36 0R-0603SMT
TP51
R44 12K-0603SMT
C66 100NF-0402SMT
R56 680R-0603SMT
TP43
R69 10K-0402SMT
R46 4_7K-0603SMT
VCC GND
TDO TDI ispEN_N
NC
TMS TCK
DONE
INITN
J3 HEADER 10
12
3 4 5 6
7
8 9
10
C67
100NF-0402SMT
PTS645SM43SMTR92 LFS
SW1
A1
1
A2
2
B1 3 B2 4
FB5 MPZ1608Y600B DI
1 2
J2
SKT_MINIUSB_B_RA
VCC 1
D- 2
D+ 3
ID 4
GND5
6
6
7
7
99
88
R482_2K-0603SMT
DI
C79
12PF-0603SMT
DI
+
C65 4_7UF-10V-SMT
TP7
R380R-0603SMT
R39 0R-0402SMT
R60
680R-0603SMT
G
D15
LED_GREEN_0603
R58
4_7K-0603SMT
C70
100NF-0402SMT
R134 0R-0402SMT TP46
+
C74 3_3UF-10V-SMT
R45
4_7K-0603SMT
R53 10K-0402SMT
TP38
C243
10NF-0402SMT
R96
1K-0603SMT
RLP-101
R191
1K-0603SMT
G
D16
LED_GREEN_0603
L5
1UH-1206SMT
TP49
TP41
C77
100NF-0402SMT
TP44
C114 100NF-0402SMT
R61
220R-0603SMT
FTDI High-Speed USB FT2232H
FT2232HL U5
VREGIN
50
VREGOUT
49
DM
7
DP
8
REF
6
RESET#
14
EECS
63
EECLK
62
EEDATA
61
OSCI
2
OSCO
3
TEST
13
ADBUS0 16 ADBUS1 17 ADBUS2 18 ADBUS3 19
VPHY 4
VPLL 9
VCORE 12
VCORE 37
VCORE 64
VCCIO 20
VCCIO 31
VCCIO 42
VCCIO 56
AGND
10
GND
1
GND
5
GND
11
GND
15
GND
25
GND
35
GND
47
GND
51
PWREN#60
SUSPEND# 36
ADBUS4 21 ADBUS5 22 ADBUS6 23 ADBUS7 24 ACBUS0 26 ACBUS1 27 ACBUS2 28 ACBUS3 29 ACBUS4 30 ACBUS5 32 ACBUS6 33 ACBUS7 34 BDBUS0 38 BDBUS1 39 BDBUS2 40 BDBUS3 41 BDBUS4 43 BDBUS5 44 BDBUS6 45 BDBUS7 46 BCBUS0 48 BCBUS1 52 BCBUS2 53 BCBUS3 54 BCBUS4 55 BCBUS5 57 BCBUS6 58 BCBUS7 59
PTS645SM43SMTR92 LFS
SW2
A1
1
A2
2
B1 3 B2 4
R95
4_7K-0603SMT
RLP-101
R65
10K-0603SMT
R136
4_7K-0603SMT
RLP-101
C69
100NF-0402SMT
SW4
418311170804
4 2
5 1
3
6 7 8
R33 0R-0603SMT
R133 0R-0402SMT
R71
2_2K-0603SMT-DNI
DNI
C85
10NF-0402SMT
R129 0R-0402SMT
TP9
R131 0R-0402SMT
R40
4_7K-0402SMT
R51
10K-0402SMT
TP47
R42
10K-0402SMT
R47 4_7K-0603SMT
TP39
Y1 12MHZ
DI
1
133
G1
2G2 4
C287 20pF-0603SMT DNI
C286
20pF-0603SMT
DNI
TP50
+
C71 4_7UF-10V-SMT
C68
100NF-0402SMT
G
D20
LED_GREEN_0603
R30
220R-0603SMT
TP42
Y
D18
LED_RED_0603
FB6 MPZ1608Y600B DI
1 2
R135
4_7K-0603SMT
RLP-101
R187
50R-0603SMT
R59 4_7K-0603SMT
R50 1M-0603SMT DI
R190
1K-0603SMT
TP14
TP45
R192 1K-0603SMT
R55
680R-0603SMT
C81
100NF-0402SMT
R49 4_7K-0603SMT
C115 100NF-0402SMT
J50
HEADER 3X2
2 4 6
1 3 5
R68
10K-0402SMT
R76
0R-0603SMT-DNI
DNI
R41
10K-0402SMT
C244
100NFX5R-0402SMT
U52
N25QxxxA13xSF
S#
7
DQ1
8
W#/VPP/DQ2
9
VSS
10 DQ0 15
C16
HOLD#/DQ3 1
VCC 2
DNU_3
3
DNU_4
4
DNU_5
5
DNU_6
6
DNU_14 14 DNU_13 13 DNU_12 12 DNU_11 11
93LC56C-I/SN U6
CS 1
CLK 2
DI 3
DO 4
VSS
5ORG 6NU 7VCC 8
R
D17
LED_RED_0603
TP8
R43
10K-0402SMT R75
2_2K-0603SMT-DNI DNI
R57
4_7K-0603SMT
C78
100NF-0603SMT
TP48
C84
100NF-0603SMT
C249
20pF-0603SMT
DNI
C80 12PF-0603SMT DI
TP40
R35 0R-0402SMT
R32 0R-0603SMT
Q4
2N2222/SOT23
3
1
2
Y
D19 LED_RED_0603

20
ECP5 Versa Development Board
®
Figure 13. SERDES
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
X1 PCIe Board Fingers
All Nets to SMAs are 100-ohm differential pairs. The P and N traces shall be <20mil matched in length
All Nets are 85-ohm differential pairs. The P and N traces shall be <20mil matched in length
B side = Primary Component Side(TOP) A side = Secondary Component Side(BOTTOM)
Schematic symbols rev 4.1
SERDES
PHY 1 & 2 SGMII
SMA SMA
x1_PERp0 x1_PERn0
PRSNT3# PCIE_3V3
PRSNT1#
x1_PERp0 x1_PERn0
x1_PETp0 x1_PETn0
PCIE_3V3
HDRXN0_D0CH1HDRXP0_D0CH1
HDTXP0_D0CH1 HDTXN0_D0CH1
PCIE_CLKP PCIE_CLKN
PRSNT1# PRSNT3#
REFCLKP_D0 REFCLKN_D0
x1_PETp0 x1_PETn0
HDRXP0_D0CH1 HDRXN0_D0CH1 HDTXN0_D0CH0 HDTXP0_D0CH0 HDTXN0_D0CH1 HDTXP0_D0CH1 HDRXN0_D1CH1 HDRXP0_D1CH1 HDRXN0_D1CH0 HDRXP0_D1CH0 HDTXN0_D1CH0 HDTXP0_D1CH0 HDTXN0_D1CH1 HDTXP0_D1CH1
REFCLKP_D1 REFCLKN_D1
12_0VIN
VCCHTX0
3_3V
VCCA0
VCCHTX0 VCCA0
VCCHTX1
VCCA1
VCCHTX1 VCCA1
PCIE_CLKP[9] PCIE_CLKN[9]
PCIE_PERSTN[3]
PRSNT[9]
REFCLKP_D0 [9]
REFCLKN_D0 [9]
HDTXP0_D1CH0[5] HDTXN0_D1CH0[5] HDTXP0_D1CH1[6] HDTXN0_D1CH1[6] HDRXP0_D1CH0 [5] HDRXN0_D1CH0 [5] HDRXP0_D1CH1 [6] HDRXN0_D1CH1 [6]
REFCLKP_D1 [9]
REFCLKN_D1 [9]
Date: Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: [e-mail]
Board Rev
Project
B
B
11
SERDES
ECP5 VERSA Eval Board
B
Friday, August 21, 2015 4
Date: Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: [e-mail]
Board Rev
Project
B
B
11
SERDES
ECP5 VERSA Eval Board
B
Friday, August 21, 2015 4
Date: Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: [e-mail]
Board Rev
Project
B
B
11
SERDES
ECP5 VERSA Eval Board
B
Friday, August 21, 2015 4
C92
10NF-0402SMT
R72
4_7K-0603SMT
J5 SMA
12
3 4 5
C91
100NF-0402SMT
C89
10NF-0402SMT
C111
100NF-0402SMT
C90
1NF-0402SMT
CN1
PCI Express x1 Edge Finger Conn.
PRSNT1#
A1
+12V
A2
+12V
A3
GND
A4
JTAG2
A5
JTAG3
A6
JTAG4
A7
JTAG5
A8
+3.3V
A9
+3.3V
A10
PERST#
A11
GND
A12
REFCLK+
A13
REFCLK-
A14
GND
A15
PERp0
A16
PERn0
A17
GND
A18
+12VB1 +12VB2
RSVD_B3 B3
GNDB4
SMCLK B5
SMDAT B6
GNDB7
+3.3VB8
JTAG1 B9
3.3VauxB10
WAKE# B11
RSVD_B12 B12
GNDB13
PETp0 B14 PETn0 B15
GNDB16
PRSNT3# B17
GNDB18
LFE5UM-45F-BG381
U1H
VCCHTX0_D0CH0
T7
VCCHTX0_D1CH0
T11
VCCHTX1_D0CH1
T10
VCCHTX1_D1CH1
T14
VCCHRX0_D0CH0
T8
VCCHRX0_D1CH0
T12
VCCHRX1_D0CH1
T9
VCCHRX1_D1CH1
T13
HDTXP0_D0CH0 W4
HDTXN0_D0CH0 W5
HDTXP0_D0CH1 W8
HDTXN0_D0CH1 W9
HDTXP0_D1CH1 W17
HDTXN0_D1CH1 W18
HDTXP0_D1CH0 W13
HDTXN0_D1CH0 W14
REFCLKP_D0 Y11
REFCLKN_D0 Y12
HDRXP0_D0CH0 Y5
HDRXN0_D0CH0 Y6
HDRXP0_D0CH1 Y7
HDRXN0_D0CH1 Y8
HDRXP0_D1CH0 Y14
HDRXN0_D1CH0 Y15
HDRXP0_D1CH1 Y16
HDRXN0_D1CH1 Y17
REFCLKP_D1 Y19
REFCLKN_D1 W20
J8 SMA
12
3 4 5
C113
10NF-0402SMT
J4
HEADER 3X2
2 4 6
1 3 5
R178OPEN-0603SMT
C105
1NF-0402SMT
C87100NFX5R-0402SMT
TP6 Testpoint
1
C93
1NF-0402SMT
C112
1NF-0402SMT
C88
100NF-0402SMT
J7 SMA
12
3 4 5
J6 SMA
12
3 4 5
C110
10NF-0402SMT
C106
100NF-0402SMT
C86100NFX5R-0402SMT