Lattice Semiconductor MachXO5-NX Development Kit User manual

MachXO5-NX Development Board
Preliminary
Evaluation Board User Guide
FPGA-EB-02052-0.90
May 2022

MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-EB-02052-0.90
Disclaimers
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its
products for any particular purpose. All information herein is provided AS IS, with all faults and associated risk the responsibility entirely of the Buyer.
Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited
testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice
products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a
situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is
proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at
any time without notice.

MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02052-0.90 3
Contents
Acronyms in This Document.................................................................................................................................................6
1. Introduction..................................................................................................................................................................7
1.1. MachXO5-NX Development Board......................................................................................................................7
1.2. Features ..............................................................................................................................................................8
1.3. MachXO5-25 Device............................................................................................................................................9
2. Applying Power to the Board......................................................................................................................................10
3. Hard JTAG/I2C Programming ......................................................................................................................................12
3.1. JTAG Download Interface..................................................................................................................................12
3.2. I2C Download Interface .....................................................................................................................................14
4. Soft JTAG/UART User Interface ..................................................................................................................................15
4.1. Soft JTAG User Interface ...................................................................................................................................15
4.2. Soft UART User Interface ..................................................................................................................................15
5. MachXO5-25 Clock Sources........................................................................................................................................17
6. SGMII Ethernet Connections ......................................................................................................................................18
7. HyperRAM ..................................................................................................................................................................20
8. Headers and Test Connections ...................................................................................................................................21
8.1. Versa Headers ...................................................................................................................................................21
8.2. Arduino Board GPIO Headers............................................................................................................................23
8.3. FX12 Headers ....................................................................................................................................................24
8.4. Aardvark Header (DNI)......................................................................................................................................26
8.5. Raspberry Pi Board GPIO Header ......................................................................................................................26
8.6. PMOD Headers..................................................................................................................................................27
8.7. MIPI Camera Header .........................................................................................................................................28
8.8. User I2C Interface ..............................................................................................................................................29
8.9. ADC and Potentiometer ....................................................................................................................................30
8.10. Other Test Points ..............................................................................................................................................32
9. LEDs and Switches ......................................................................................................................................................33
9.1. Four-Position DIP Switch...................................................................................................................................33
9.2. General Purpose Push Buttons .........................................................................................................................34
9.3. General Purpose LEDs .......................................................................................................................................34
9.4. Seven-Segment Display.....................................................................................................................................34
10. Software Requirements..........................................................................................................................................36
11. Storage and Handling .............................................................................................................................................36
12. Ordering Information..............................................................................................................................................36
Technical Support Assistance ..............................................................................................................................................37
Appendix A. MachXO5-NX Development Board Schematics..............................................................................................38
Appendix B. MachXO5-NX Development Board Bill of Materials.......................................................................................49
Appendix C. User Defined Preference File Listing ..............................................................................................................56
Appendix D. MachXO5-NX Development Board Revision Information ..............................................................................60
References..........................................................................................................................................................................61
RevisionHistory...................................................................................................................................................................62

MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-EB-02052-0.90
Figures
Figure 1.1. Top View of MachXO5-NX Development Board .................................................................................................7
Figure 1.2. Bottom View of MachXO5-NX Development Board ...........................................................................................8
Figure 2.1. Board Power Supply..........................................................................................................................................10
Figure 3.1. JTAG/I2C Programming Architecture ................................................................................................................12
Figure 3.2. Radiant Programmer Detect Dual Ports ...........................................................................................................12
Figure 3.3. Level Shift for JTAG Download Interface ..........................................................................................................13
Figure 3.4. JTAG Test Header..............................................................................................................................................13
Figure 3.5. I2C Programming Mode ....................................................................................................................................14
Figure 4.1. JTAG/UART User Interfacing.............................................................................................................................15
Figure 5.1. Onboard Clock Resources.................................................................................................................................17
Figure 8.1. MIPI Camera Sensor Interface ..........................................................................................................................28
Figure 8.2. MIPI Camera Sensor Power Supply Header......................................................................................................29
Figure 8.3. Circuit Design for ADC0.....................................................................................................................................30
Figure 8.4. Circuit Design for ADC1.....................................................................................................................................31
Figure 8.5. Trimmer Wiper Description ..............................................................................................................................31
Figure 9.1. Four-Position DIP Switch Circuits......................................................................................................................33
Figure 9.2. Four-position DIP Switch ..................................................................................................................................33
Figure 9.3. Seven-Segment Display and its Symbol ............................................................................................................34
Figure A.1. Title Page ..........................................................................................................................................................38
Figure A.2. Block Diagram and Power Tree ........................................................................................................................39
Figure A.3. USB to Hard JTAG I/F ........................................................................................................................................40
Figure A.4. USB to Soft JTAG I/F (BANK1) ...........................................................................................................................41
Figure A.5. Versa Connector (BANK0/2) .............................................................................................................................42
Figure A.6. Arduino&Aardvark Header (BANK3/4).............................................................................................................43
Figure A.7. High Speed Header (BANK5/6) .........................................................................................................................44
Figure A.8. Raspberry Pi and LEDs (BANK7/8) ....................................................................................................................45
Figure A.9. HyperRam and ADC (BANK9)............................................................................................................................46
Figure A.10. Power Rails .....................................................................................................................................................47
Figure A.11. Power Regulators ...........................................................................................................................................48

MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02052-0.90 5
Tables
Table 2.1. Onboard Major Power Rails...............................................................................................................................11
Table 2.2. MachXO5-25 IO Bank Power Rails Stuff.............................................................................................................11
Table 2.3. MachXO5-25 Major Power Rails Stuff................................................................................................................11
Table 3.1. Config JTAG Connections ...................................................................................................................................13
Table 3.2. Other Config JTAG Control Signals .....................................................................................................................14
Table 3.3. Download I2C Connections.................................................................................................................................14
Table 4.1. Soft JTAG Connections .......................................................................................................................................15
Table 4.2. Soft UART Connections ......................................................................................................................................16
Table 5.1. Input Clock Options............................................................................................................................................17
Table 6.1. SGMII Ethernet PHY Connections ......................................................................................................................18
Table 7.1. HyperRAM Pin Mapping.....................................................................................................................................20
Table 8.1. Versa J8 Header Pin Connections.......................................................................................................................21
Table 8.2. Versa J9 Header Pin Connections.......................................................................................................................22
Table 8.3. Arduino J2 Pin Connections ...............................................................................................................................23
Table 8.4. Arduino J3 Pin Connections ...............................................................................................................................23
Table 8.5. Arduino J4 Pin Connections ...............................................................................................................................23
Table 8.6. Arduino J5 Pin Connections ...............................................................................................................................24
Table 8.7. FX12 U4 Header Pin Connections ......................................................................................................................24
Table 8.8. FX12 U5 Header Pin Connections ......................................................................................................................25
Table 8.9. Aardvark J7 Header Pin Connections .................................................................................................................26
Table 8.10. Raspberry Pi J6 Header Pin Connections .........................................................................................................26
Table 8.11. J15 Header Pin Connections ............................................................................................................................27
Table 8.12. J16 Header Pin Connections ............................................................................................................................28
Table 8.13. MIPI Camera Sensor Interconnections ............................................................................................................28
Table 8.14. I2C Connections................................................................................................................................................30
Table 8.15. J28 (DNI) Header Pin Connections ...................................................................................................................31
Table 8.16. Test Point Connections ....................................................................................................................................32
Table 9.1. Four-Position DIP Switch Signals........................................................................................................................33
Table 9.2. Push Button Switch Signals ................................................................................................................................34
Table 9.3. LED Signals .........................................................................................................................................................34
Table 9.4. Seven-segment Display Connections .................................................................................................................35
Table 12.1 Ordering Information........................................................................................................................................36

MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 FPGA-EB-02052-0.90
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
CMOS
Complementary Metal-Oxide Semiconductor
DNI
Do Not Install
FTDI
Future Technology Devices International
GPIO
General Purpose Input/Output
I2C
Inter-Integrated Circuit
LDO
Low Dropout
LVDS
Low-Voltage Differential Signaling
SPI
Serial Peripheral Interface

MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02052-0.90 7
1. Introduction
The Lattice Semiconductor MachXO5™-NX Development Board allows you to investigate and experiment with the
features of the MachXO5-25 device. The features of the MachXO5-NX Development Board can assist you with the rapid
prototyping and testing of their specific designs.
The MachXO5-NX Development Board is part of the MachXO5-NX Development Kit, which includes the following:
MachXO5-NX Development Board pre-loaded with the demo design
12 V AC/DC Power adapter
Mini USB cable
Quick Start Guide
The contents of this user guide include top-level functional descriptions of the various portions of the development
board, descriptions of the onboard headers, diodes and switches, and a complete set of schematics.
1.1. MachXO5-NX Development Board
Along with the MachXO5-25 device, the MachXO5-NX Development Board also includes features to expand the
usability of the MachXO5-25 with Arduino, Raspberry, FX12, Versa, and Aardvark headers.
Figure 1.1 shows the top view of the MachXO5-NX Development Board.
Figure 1.2 shows the bottom view of this board.
MachXO5-25
Device (U3)
DIP Switches
(SW1)
FX12 Header
(U4) FX12 Header (U5)
Versa Headers (J8, J9)
JTAG
Header (J1)
Push Buttons
(SW2~SW5)
Trimmer 10K
(POT1)
Segment Displayer (D20)
PMOD Header
(J16)
PMOD Header
(J15)
Power Switch
(SW6)
MIPI
Header
(J27)
User LEDs
(D1~D8)
HyperRam
(U6, U9)
Figure 1.1. Top View of MachXO5-NX Development Board

MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8 FPGA-EB-02052-0.90
Config USB
Header (J11)
User USB
Header (J19)
Config FTDI
Device (U1)
User FTDI
Device (U18) 27MHz
Clock (X4)
125MHz
Clock (X5)
12V DC Power
Jack (J17)
Figure 1.2. Bottom View of MachXO5-NX Development Board
1.2. Features
On board MachXO5-25 Device
Optional SGMII, Gbe PHY RJ45 connector (Check Appendix D for the board revision information)
HyperRAM upto 166MHz, x16 bits
Versa Headers bridge with Lattice ASC Demo Board to support L-ASC10
General Purpose Input/Output (GPIO) interface with PMOD, Arduino and Raspberry Pi boards
USB-B connection for device programming with JTAG and Inter-Integrated Circuit (I2C) utility
Additional USB-B connection for user with Soft JTAG and UART utility
7-Segment Blue LED, 4-position DIP Switches, 4 push buttons, and 8 red LEDs for demo purposes
ADC interface with 10K POT
Two Hirose FX12-40 headers
Multiple reference clock sources
Optional Aardvark header
Lattice Radiant®programming support
Note:
DNI stands for “Do NOT Install” parts and DI stands for “Do Install” parts for assembly.
Caution: The MachXO5-NXDevelopment Board contains ESD-sensitive components. ESD safe
practices should be followed while handling and using the development board.

MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02052-0.90 9
1.3. MachXO5-25 Device
The MachXO5-NX Development Board features the MachXO5-25 in a 400-ball caBGA package. This device offers a
variety of features and programmability that enhances Secure Control PLD functionality with Multiple Boot capabilities.
Its cryptographic engine supports user-mode security features. Along with the cryptographic engine, numerous system
functions are included such as two PLLs and 432 kbits of embedded RAM plus hardened implementations of I2C and SPI.
Flexible, high performance I/O support numerous single-ended and differential standards including LVDS and MIPI. For
more information on the capabilities of MachXO5-25device, see MachXO5-NXFamily Data Sheet (FPGA-DS-02102).

MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10 FPGA-EB-02052-0.90
2. Applying Power to the Board
The MachXO5-NX Development Board comes ready to power up with onboard DC/DC switching regulators and Low
Dropout (LDO) generators powered by an external 12 V DC power source. The external power supply can be connected
with the DC power input jack J17, which is fused with a surface mounted fuse U10. The 1.25A fuse prevents the crashed
current from flowing into the internal circuits and cause serious damage. 12 V DC power also supply Arduino Header J4
and FX12 headers U4/U5 for the board extension, as shown in Figure 2.1.
Fuse (U10)
12V DC
USB Header
(J11)
5V DC
5V Regulator
(U11)
Slide Switch
(SW6)
5V
5V
12V
1.0V Regulator
(U12) VCC Core(U3)
1.0V
2.5V LDO
(U13)
3.3V LDO (U8)
1.8V LDO
(U15)
1.2V LDO
(U16)
2.5V
1.2V
Raspberry Pi
Header(J6)
Arduino
Header(J4)
JP7
2.8V LDO
(U20)
VCCIO0/2(U3)
VCCIO1(U3)
JP6
J25
3.3V
3.3V
VCCIO3(U3)
2.5V
J26
3.3V
3.3V
VCCIO8(U3)
J23
3.3V
3.3V
VCCIO7(U3)
J22
3.3V
1.8V
VCCIO4(U3)
J29
1.2V
2.5V
VCCIO6(U3)
J21
1.2V
1.8V
VCCIO5(U3)
J20
1.8V
1.2V
5V
VCCIO9(U3)
1.8V
VCCAUX/VCCAUXA/VCCAUX
H/VCCADC (U3)
1.8V FX12 Headers
(U4/U5)
Power Jack
(J17)
12V
5V
3.3V
1.8V
HyperRAM
(U6/U9)
JTAG(J1)
PMOD(J15)
JTAG(J18)
PMOD(J16)
SMGIIVDDIO(U7)
PMOD(J28)
30-pin
Header(J27)
2.8V
Figure 2.1. Board Power Supply
The onboard 5 V power regulator U11 provide 90% power convert efficiency from 12 V when output current between
50 mA and 3 A. It is distributed to 3.3 V, 2.8 V, 2.5 V LDOs and 1.0 V regulator through one side of slide switch SW6 to
support onboard devices. Through another side of SW6, this board can also take the 5 V power from USB header J11 as
well, for some low power application. It is user’s responsibility to ensure all 5 V power rails on board consume less than
500mA per PC’s USB port output capability when take power from J11.
For the board extension, 5 V DC power can also supply FX12 adapter, Raspberry Pi and Arduino boards through the
jumpers and onboard headers, to consolidate AC/DC adapters for stack boards system. Conversely, 5V DC power can
be either supplied from mated boards with correct jumper settings. However, maintain the 5 V DC power is the basic
requirement to bring up this board, by quick check the power good blue LED D18.
The onboard 1.2 V and 1.8 V LDOs take the power from 3.3 V and 2.5 V LDO correspondently.
Table 2.1 summarizes onboard major power rails and their test points.

MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02052-0.90 11
Table 2.1. Onboard Major Power Rails
Power Net Name
Primary Source
Test Point
+12V
DC Power Jack (J17)
TP20
PS_5V
DC/DC Regulator (U11 )
—
VBUS_5V
Mini-USB (J11)
—
+5.0V
Selected by Slide switch (SW6)
TP14
+3.3V
LDO (U8)
TP15
+1.2V
LDO (U16)
TP18
+2.5V
LDO (U13)
TP16
+1.8V
LDO (U15)
TP17
+2.8V
LDO (U20)
TP19
+1.0V
DC/DC Regulator (U12)
TP21
+3.3V_RASP
Raspberry Pi Header (J6)
—
+3.3V_AR
Arduino Header (J4)
—
As shown in Figure 2.1, this board provides multiple power options for I/O bank voltage flexibility. Table 2.2
summarizes the VCCIO support matrix on this board. For an example, VCCIO0 and VCCIO2 share the same three
positions jumper J25 and short its Pin 1 and Pin 2 can bring the 3.3 V LDO output to both I/O bank 0 and bank 2. For
power consumption evaluation, this board facilitate some two-position jumpers with 1 Ωsense resistors to measure
the voltage drop on each power rail, then the supply current can be calculated.
Table 2.2. MachXO5-25 IO Bank Power Rails Stuff
MachXO5-25 Power (U3)
Jumpers
3.3V
2.5V
1.8V
1.2V
Ext 3.3V
Power Test
Point
Sense Resistor
of 1 Ω
VCCIO0
J25
Pin 1-2
Pin 2-3
—
—
—
JP19
R132
VCCIO1
—
Fixed
—
—
—
—
JP16
R133
VCCIO2
J25
Pin 1-2
Pin 2-3
—
—
—
JP20
R134
VCCIO3
J26
Pin 1-2
—
—
Pin 2-3
JP21
R235
VCCIO4
J29
—
Pin 1-2
—
Pin 2-3
—
JP22
R236
VCCIO5
J20
—
—
Pin 2-3
Pin 1-2
—
JP23
R237
VCCIO6
J21
—
—
Pin 2-3
Pin 1-2
—
JP24
R238
VCCIO7
J22
Pin 1-2
—
Pin 2-3
—
—
JP25
R239
VCCIO8
J23
Pin 1-2
—
—
—
Pin 2-3
JP26
R240
VCCIO9
—
—
—
Fixed
—
—
JP15
R138
Other than power rail for each I/O Bank, this board also provides some test points to evaluate the major power
consumptions for MachXO5-25 device.
Table 2.3. MachXO5-25 Major Power Rails Stuff
MachXO5-25 Power (U3)
Power Test Point
Voltage Drop Resistor
Resistance
VCC_CORE
JP18
R112
0.01 Ω
VCC_AUX/VCC_AUXH/VCCAUXA
JP14
R131
1 Ω
VCC_ADC
JP17
R137
1 Ω

MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12 FPGA-EB-02052-0.90
3. Hard JTAG/I2C Programming
The hardened JTAG/I2C programming architecture of the MachXO5-NX Development Board is shown in Figure 3.1. The
board has a built-in download controller for programming the MachXO5-25 device. It uses an FT2232H Future
Technology Devices International (FTDI) part U1 to convert USB to JTAG from port A, or convert USB to I2C from port B.
Using Detect Cable function with Radiant programming software installed, you can detect dual ports after power up
the board and connect the mini USB to USB-A cable from J11 to your PC ensuring FTDI reset control jumper JP9 is not
populated as default. The software select option FTUSB-0 is dedicate for hard JTAG and FTUSB-1 is dedicate for hard I2C
which is mapping with port A and port B from hardware perspective, as shown in Figure 3.2.
Mini-USB
(J11)USB FT2232H
(U1)
Port A
Port B
MachXO5-NX (U3)
Level
Shift
(U14)
rst#
JP9
GND
FTDI_SCL
FTDI_SDA
SCL0
SDA0
JP12 JP13
TDI
TCK
TMS
TDO NX_TDI
NX_TCK
NX_TMS
NX_TDO
OEN
Config JTAGHeader (J1)
JP1
3.3V
Figure 3.1. JTAG/I2C Programming Architecture
Figure 3.2. Radiant Programmer Detect Dual Ports
3.1. JTAG Download Interface
A level shifter SN74AVC4T774 U14 from TI is inserted between Config FTDI Port A and MachXO5-25 JTAG port to make
sure the FTDI fixed I/O voltage can adapt with flexible voltage selection of FPGA’s bank 2, as shown in Figure 3.3. An
8-pin header J1 as shown in Figure 3.4 allowing you not only to probe the JTAG signals, but also to access MachXO5-25
JTAG port from external JTAG host such as external Lattice HW-USBN-2B Programming Cable (available separately), or
access SSPI port from external SPI host. In those cases, jumper JP1 must be added to pull OEN high and ensure U14 to

MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02052-0.90 13
output tri-state mode, avoiding multi-drivers on those shared signals. The JTAG connections between J1 and
MachXO5-25 are listed in Table 3.1.
Figure 3.3. Level Shift for JTAG Download Interface
Figure 3.4. JTAG Test Header
Table 3.1. Config JTAG Connections
J1 Pin Number
JTAG Net Name
MachXO5-25 Ball Location
for JTAG
Optional SSPI Function
1
VCCIO2
—
—
2
NX_TDO
E20
SSI
3
NX_TDI
E18
SSO
4
—
—
—
5
—
—
—
6
NX_TMS
F16
SCSN
7
GND
—
—
8
NX_TCK
G16
SCLK

MachXO5-NX Development Board
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14 FPGA-EB-02052-0.90
The MachXO5-NX Development Board also provides test points for other dedicated JTAG configuration pins as shown
in Table 3.2.
Table 3.2. Other Config JTAG Control Signals
Net Name
MachXO5-25 Ball Location
LED Indicator
Test Point
JTAGEN
B20
—
Pin 1 of JP2
PROGRAMN
F12
—
Pin 1 of JP5
INITN
E13
D11
TP5
DONE
F13
D10
TP6
JP2 for JTAGEN is used to pull down the JTAGEN for enabling JTAG port when JTAG_PORT is disabled by software. JP5
can bridge push button PB4 with PROGRAMN when PROGRAMN_PORT function is enabled by software.
3.2. I2C Download Interface
The USB hub on the PC can also detect the addition of the USB function on Config FTDI Port B and you can select the
port FTUSB-1 on the programmer interface for the accessing from Config FTDI Port B to the MachXO5-25 dedicated I2C
download port (Figure 3.2) that is named as FTDI_SDA/FTDI_SCL with 2.2 kΩpull up resistor each. The Diode D21 is
inserted to support I2Cclock stretching mode. Figure 3.5 details the design of Config FTDI Port B for dedicated I2C
download interface. Table 3.3 summarizes the interconnection with MachXO5-25 and its supported circuits. JP12 and
JP13 are used to connect the dedicated I2C download port of MachXO5-25 with the bridge I2C bus SDA0/SCL0 cross the
whole board, in case you need access I2C download port from other on board headers other than Config FTDI part. For
the detail connection from other headers to bridge I2C bus SDA0/SCL0, refer to the User I2C Interface section.
Figure 3.5. I2C Programming Mode
Table 3.3. Download I2C Connections
Download I2C Net Name
MachXO5-25 Ball
Location for JTAG
2.2 kΩPull up Resistor
Bridge I2C Net
Name
Bridge Jumper
FTDI_SCL
G15
R33
SCL0
JP12
FTDI_SDA
F15
R34
SDA0
JP13
For more information on MachXO5-25 JTAG/ I2C programming, refer to MachXO5-NX Programming and Configuration
User Guide (FPGA-TN-02271).

MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
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FPGA-EB-02052-0.90 15
4. Soft JTAG/UART User Interface
The soft JTAG/UART user interface for the MachXO5-NX Development Board is shown in Figure 4.1. Supposedly it also
uses an FT2232H FTDI part U18 to convert USB to user JTAG from port A, or convert USB to UART from port B. Using
Detect Cable function with Radiant programming software installed and ensuring FTDI reset control jumper JP8 is not
populated in default, as shown in Figure 3.2, you can detect other dual ports after power up the board. You can then
connect the mini USB to USB-A cable from J19 to your PC. The software select option FTUSB-0 is targeted for user JTAG,
and FTUSB-1 is targeted for UART that is mapped with port A and port B from hardware perspective.
Mini-USB
(J19)USB FT2232H
(U18)
Port A
Port B
MachXO5-NX
(U3)
rst#
JP8
GND
RS232_RX_TTL
UTDI
UTCK
UTMS
UTDO
User JTAG Header (J18)
RS232_TX_TTL
Figure 4.1. JTAG/UART User Interfacing
4.1. Soft JTAG User Interface
User FTDI Port A is connected with GPIOs in Bank 1 directly, but you need allocate GPIOs for adaption with JTAG signals
by programmable logic, which is defined by FTDI Port A when converting USB to JTAG through FTUSB-0. J18 is an 8-pin
standalone JTAG header that is used with an external Lattice download cable (available separately) when the FTDI part
is disabled from the JTAG chain after setting JP8. J18 can also be used as test point when USB to JTAG is working.
Table 4.1. Soft JTAG Connections
J18 Pin Number
FTDI Signal
JTAG Net Name
MachXO5-25 Ball Location
1
—
VCCIO1
—
2
UADBUS2
UTDO
A12
3
UADBUS1
UTDI
A11
4
—
—
—
5
—
—
—
6
UADBUS3
UTMS
A13
7
—
GND
—
8
UADBUS0
UTCK
A14
4.2. Soft UART User Interface
User FTDI Port B is also connected with GPIOs in Bank 1 directly, but you need allocate GPIOs for adaption with UART
signals by programmable logic, which is defined by FTDI Port B when converting USB to UART through FTUSB-1.

MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16 FPGA-EB-02052-0.90
Table 4.2. Soft UART Connections
FTDI Signal
UART Net Name
MachXO5-25 Ball Location for Port A
UBDBUS0
RS232_RX_TTL
B11
UBDBUS1
RS232_TX_TTL
B12
UBDBUS2
RTSn
B13
UBDBUS3
CTSn
B14
UBDBUS4
DTRn
B15
UBDBUS5
DSRn
B16
UBDBUS6
DCDn
B17
UBDBUS7
RI
C11

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FPGA-EB-02052-0.90 17
5. MachXO5-25 Clock Sources
The MachXO5-NX Development Board has multiple external clock options for the MachXO5-25applications as shown in
Figure 5.1.
12 MHz from U1 (FTDI)
12 MHz from U18 (FTDI)
25 MHz from U7 (SGMII PHY)
27 MHz from X4 (OSC MEM)
125 MHz from X5 (OSC MEM)
External clock source from J10 (SMA)
J8
12MHz
U1
U18
U7
X4
X5
J10
EXT_CLK
125M_OSC_OUT
27M_OSC_OUT
SGMII_CLK_OUT
U12MHz
JP10
R159
JP11
EXPCON_OSC
J11
J19
USB
USB
Clock
Generator
SMA
Figure 5.1. Onboard Clock Resources
You need take care that only 27 MHz and 125 MHz clocks are active in default after board power up. Both 12 MHz
clocks from the FT2232H FTDI U1 and U18 device are not always on without some hardware configuration. 25 MHz of
SGMII and external clock need source from other devices. Refer to Table 5.1 for those clock utilization and enable
conditions.
Table 5.1. Input Clock Options
Clock
Frequency
Net Name
MachXO5-25
Ball Location
Clock
Source
Always
On?
Enable Conditions
12 MHz
12MHZ
E16
U1
No
Need add R159 and JP11. USB header J11 connected
with power on.
12 MHz
U12MHZ
E14
U18
No
Need add JP10. USB header J19 connected with
power on.
25 MHz
SGMII_CLK_OUT
T7
U7
No
Power on. U7 populated and enabled.
27 MHz
27M_OSC
B1
X4
Yes
Power on. Force 27M_EN high if R161 populated.
125 MHz
125M_OSC
V1
X5
Yes
Power on. Force 125M_EN high if R232 populated.
Customer
EXT_CLK
D19
J10
No
Need add J10. Connect to external clock generator
through SMA cable.

MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18 FPGA-EB-02052-0.90
6. SGMII Ethernet Connections
This section describes the MachXO5-NX Development Board SGMII application for Ethernet connections.
Table 6.1. SGMII Ethernet PHY Connections
U7 Pin Number
U7 Signal Name
Net Name
MachXO5-25 Ball Location
Application Notes
1
TD_P_A
SGMII_MD0_P
—
To RJ45
2
TD_M_A
SGMII_MD0_N
—
To RJ45
3
VDDA2P5
+2.5V
—
2.5 V Power
4
TD_P_B
SGMII_MD1_P
—
To RJ45
5
TD_M_B
SGMII_MD1_N
—
To RJ45
6
VDD1P0
VCCA_1V_PHY
—
1.0 V Power
7
TD_P_C
SGMII_MD2_P
—
To RJ45
8
TD_M_C
SGMII_MD2_N
—
To RJ45
9
VDDA2P5
+2.5V
—
2.5 V Power
10
TD_P_D
SGMII_MD3_P
—
To RJ45
11
TD_M_D
SGMII_MD3_P
—
To RJ45
12
RBIAS
—
—
Pull down to GND
13
VDDA1P8
SGMII_PHY_D1V8
—
1.8 V Power
14
XO
SGMII_XO
—
25 MHz Crystal Output
15
XI
SGMII_XI
—
25 MHz Crystal Input
16
MDC
SGMII_MDIO_CLK
U1
Optional pull up to
VDDIO
17
MDIO
SGMII_MDIO_DATA
U2
Pull up to VDDIO
18
CLK_OUT
SGMII_CLK_OUT
T7
With 22 Ωdebounce
resistor
19
VDDIO
SGMII_VDDIO
—
VCCIO7 selectable
20
JTAG_CLK
—
—
Pull down to GND
21
JTAG_TDO
—
—
Pull up to VDDIO
22
JTAG_TMS
—
—
Pull up to VDDIO
23
JTAG_TDI
—
—
Pull up to VDDIO
24
VDD1P0
VCCA_1V_PHY
—
1.0 V Power
25
TX_D3
—
—
Pull down to GND
26
TX_D2
—
—
Pull down to GND
27
TX_D1/SGMII_SIP
SGMII_PHY_SIP
N8
0.1 µF AC coupling
28
TX_D0/SGMII_SIN
SGMII_PHY_SIN
P8
0.1 µF AC coupling
29
GTX_CLK
—
—
Pull down to GND
30
VDDIO
SGMII_VDDIO
—
VCCIO7 selectable
31
VDD1P0
VCCA_1V_PHY
—
1.0 V Power
32
RX_CLK
—
—
—
33
RX_D0/SGMII_COP
SGMII_PHY_COP
U9
0.1 µF AC coupling
34
RX_D1/SGMII_CON
SGMII_PHY_CON
V9
0.1 µF AC coupling
35
RX_D2/SGMII_SOP
SGMII_PHY_SOP
N9
0.1 µF AC coupling
36
RX_D3/SGMII_SON
SGMII_PHY_SON
P9
0.1 µF AC coupling
37
TX_CTRL
—
—
Pull down to GND
38
RX_CTRL
—
—
—
39
GPIO_0
—
—
Pull down to GND
40
GPIO_1
—
—
Pull down to GND
41
VDDIO
SGMII_VDDIO
—
VCCIO7 selectable
42
VDD1P0
VCCA_1V_PHY
—
1.0 V Power

MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02052-0.90 19
U7 Pin Number
U7 Signal Name
Net Name
MachXO5-25 Ball Location
Application Notes
43
RESET#
SGMII_RST_N
T6
Default Pull down
44
INT/PWDN
SGMII_INT
T5
Default pull up. Shunt
JP3 to pull down.
45
LED_2
SGMII_LED_2
—
Drive Red LED D15
46
LED_1
SGMII_LED_1
—
Drive Red LED D14
47
LED_0
SGMII_LED_0
—
Drive Red LED D13
48
VDDA1P8
SGMII_PHY_D1V8
—
1.8 V Power

MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20 FPGA-EB-02052-0.90
7. HyperRAM
This section describes MachXO5-25 interconnection with 2 HyperRAM device on MachXO5-NX Development Board.
Table 7.1. HyperRAM Pin Mapping
Cypress HyperRAM™in 24-Ball FBGA
Connection for HyperRAM0 (U6)
Connection for HyperRAM1 (U9)
Symbol Name
Ball Location
Net Name
MachXO5-25 Ball
Location
Net Name
MachXO5-25 Ball
Location
RFU1
A2
—
—
—
—
RFU2
A5
—
—
—
—
CS#
A3
HR0_CS
J3
HR1_CS
G6
RESET#
A4
HR_RST
D2
HR_RST
D2
CK#
B1
HR0_CKN
J1
HR1_CKN
K4
CK
B2
HR0_CK
J2
HR1_CK
K5
VSS
B3
GND
—
GND
—
VSSQ
C1
GND
—
GND
—
VSSQ
E5
GND
—
GND
—
VCC
B4
VRAM
—
VRAM
—
VCCQ
E4
VRAM
—
VRAM
—
VCCQ
D1
VRAM
—
VRAM
—
RFU3
B5
—
—
—
—
RFU4
C2
—
—
—
—
RFU5
C5
—
—
—
—
RWDS
C3
HR0_RW
D1
HR1_RW
G5
DQ0
D3
HR0_DQ0
H1
HR1_DQ0
E1
DQ1
D2
HR0_DQ1
H2
HR1_DQ1
E2
DQ2
C4
HR0_DQ2
J4
HR1_DQ2
E3
DQ3
D4
HR0_DQ3
J5
HR1_DQ3
F1
DQ4
D5
HR0_DQ4
J6
HR1_DQ4
G1
DQ5
E3
HR0_DQ5
J7
HR1_DQ5
G2
DQ6
E2
HR0_DQ6
J8
HR1_DQ6
G3
DQ7
E1
HR0_DQ7
K8
HR1_DQ7
G4