Motorola DigitalDNA ColdFire MCF5272 User manual

MCF5272UM/D
Rev. 0, 02/2001
MCF5272 ColdFire
®
Integrated Microprocessor
User’s Manual

© Motorola Inc., 2001. All rights reserved.
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http://www.motorola.com/ColdFire

GLO
IND
B
Overview
ColdFire Core
Hardware Multiply/Accumulate (MAC) Unit
Local Memory
Debug Support
System Integration Module ( SIM)
Interrupt Controller
Chip-Select Module
SDRAM Controller
DMA Controller Module
Ethernet Module
Universal Serial Bus (USB)
Physical Layer Interface Controller (PLIC)
Queued Serial Peripheral Interface (QSPI) Module
Timer Module
UART Modules
General-Purpose I/O Module
Pulse-Width Modulation (PWM) Module
Signal Descriptions
Bus Operation
Appendix B: Buffering and Impedence Matching
Index
Appendix A: List of Memory Maps
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
17
18
19
A
6
20
B
IND
21
23
22
IEEE 1149.1 Test Access Port (JTAG)
Mechanical Data
Electrical Characteristics
IND

Overview
ColdFire Core
Hardware Multiply/Accumulate (MAC) Unit
Local Memory
Debug Support
System Integration Module ( SIM)
Interrupt Controller
Chip-Select Module
SDRAM Controller
DMA Controller Module
Ethernet Module
Universal Serial Bus (USB)
Physical Layer Interface Controller (PLIC)
Queued Serial Peripheral Interface (QSPI) Module
Timer Module
UART Modules
General-Purpose I/O Module
Pulse-Width Modulation (PWM) Module
Signal Descriptions
Bus Operation
Appendix B: Buffering and Impedence Matching
Index
Appendix A: List of Memory Maps
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
17
18
19
A
6
20
B
IND
21
23
22
IEEE 1149.1 Test Access Port (JTAG)
Mechanical Data
Electrical Characteristics

CONTENTS
Paragraph
Number Title Page
Number
Contents v
About This Book
Chapter 1
Overview
1.1 MCF5272 Key Features...................................................................................... 1-1
1.2 MCF5272 Architecture....................................................................................... 1-4
1.2.1 Version 2 ColdFire Core................................................................................. 1-4
1.2.2 System Integration Module (SIM).................................................................. 1-5
1.2.2.1 External Bus Interface ................................................................................ 1-5
1.2.2.2 Chip Select and Wait State Generation ...................................................... 1-5
1.2.2.3 System Configuration and Protection......................................................... 1-5
1.2.2.4 Power Management .................................................................................... 1-6
1.2.2.5 Parallel Input/Output Ports ......................................................................... 1-6
1.2.2.6 Interrupt Inputs ........................................................................................... 1-6
1.2.3 UART Module................................................................................................ 1-6
1.2.4 Timer Module................................................................................................. 1-7
1.2.5 Test Access Port.............................................................................................. 1-7
1.3 System Design ................................................................................................... 1-7
1.3.1 System Bus Configuration.............................................................................. 1-7
1.4 MCF5272-Specific Features............................................................................... 1-8
1.4.1 Physical Layer Interface Controller (PLIC).................................................... 1-8
1.4.2 Pulse-Width Modulation (PWM) Unit ........................................................... 1-8
1.4.3 Queued Serial Peripheral Interface (QSPI)..................................................... 1-8
1.4.4 Universal Serial Bus (USB) Module .............................................................. 1-9
Chapter 2
ColdFire Core
2.1 Features and Enhancements.............................................................................. 2-11
2.1.1 Decoupled Pipelines ...................................................................................... 2-11
2.1.1.1 Instruction Fetch Pipeline (IFP)................................................................ 2-12
2.1.1.2 Operand Execution Pipeline (OEP).......................................................... 2-13
2.1.1.2.1 Illegal Opcode Handling....................................................................... 2-13
2.1.1.2.2 Hardware Multiply/Accumulate (MAC) Unit...................................... 2-13

vi MCF5272 User’s Manual
CONTENTS
Paragraph
Number Title Page
Number
2.1.1.2.3 Hardware Divide Unit .......................................................................... 2-14
2.1.2 Debug Module Enhancements...................................................................... 2-14
2.2 Programming Model......................................................................................... 2-15
2.2.1 User Programming Model ............................................................................ 2-16
2.2.1.1 Data Registers (D0–D7) ........................................................................... 2-16
2.2.1.2 Address Registers (A0–A6)...................................................................... 2-16
2.2.1.3 Stack Pointer (A7, SP).............................................................................. 2-17
2.2.1.4 Program Counter (PC).............................................................................. 2-17
2.2.1.5 Condition Code Register (CCR)............................................................... 2-17
2.2.1.6 MAC Programming Model....................................................................... 2-18
2.2.2 Supervisor Programming Model................................................................... 2-18
2.2.2.1 Status Register (SR).................................................................................. 2-18
2.2.2.2 Vector Base Register (VBR) .................................................................... 2-19
2.2.2.3 Cache Control Register (CACR) .............................................................. 2-19
2.2.2.4 Access Control Registers (ACR0–ACR1)................................................ 2-20
2.2.2.5 ROM Base Address Register (ROMBAR)............................................... 2-20
2.2.2.6 RAM Base Address Register (RAMBAR)............................................... 2-20
2.2.2.7 Module Base Address Register (MBAR) ................................................. 2-20
2.3 Integer Data Formats......................................................................................... 2-20
2.4 Organization of Data in Registers..................................................................... 2-20
2.4.1 Organization of Integer Data Formats in Registers...................................... 2-21
2.4.2 Organization of Integer Data Formats in Memory ....................................... 2-22
2.5 Addressing Mode Summary ............................................................................. 2-22
2.6 Instruction Set Summary................................................................................... 2-23
2.6.1 Instruction Set Summary .............................................................................. 2-26
2.7 Instruction Timing ............................................................................................ 2-29
2.7.1 MOVE Instruction Execution Times............................................................ 2-30
2.7.2 Execution Timings—One-Operand Instructions.......................................... 2-32
2.7.3 Execution Timings—Two-Operand Instructions.......................................... 2-33
2.7.4 Miscellaneous Instruction Execution Times................................................. 2-34
2.7.5 Branch Instruction Execution Times ............................................................ 2-35
2.8 Exception Processing Overview....................................................................... 2-36
2.8.1 Exception Stack Frame Definition................................................................ 2-38
2.8.2 Processor Exceptions.................................................................................... 2-39
Chapter 3
Hardware Multiply/Accumulate (MAC) Unit
3.1 Overview............................................................................................................. 3-1
3.1.1 MAC Programming Model............................................................................. 3-2
3.1.2 General Operation........................................................................................... 3-3
3.1.3 MAC Instruction Set Summary ...................................................................... 3-4

CONTENTS
Paragraph
Number Title Page
Number
Contents vii
3.1.4 Data Representation........................................................................................ 3-5
3.2 MAC Instruction Execution Timings.................................................................. 3-5
Chapter 4
Local Memory
4.1 Interactions between Local Memory Modules ................................................... 4-1
4.2 Local Memory Registers..................................................................................... 4-2
4.3 SRAM Overview ................................................................................................ 4-2
4.3.1 SRAM Operation............................................................................................ 4-2
4.3.2 SRAM Programming Model........................................................................... 4-2
4.3.2.1 SRAM Base Address Register (RAMBAR)............................................... 4-3
4.3.2.2 SRAM Initialization.................................................................................... 4-4
4.3.2.3 Programming RAMBAR for Power Management ..................................... 4-5
4.4 ROM Overview................................................................................................... 4-5
4.4.1 ROM Operation .............................................................................................. 4-5
4.4.2 ROM Programming Model............................................................................. 4-6
4.4.2.1 ROM Base Address Register (ROMBAR)................................................. 4-6
4.4.2.2 Programming ROMBAR for Power Management ..................................... 4-7
4.5 Instruction Cache Overview ............................................................................... 4-7
4.5.1 Instruction Cache Physical Organization........................................................ 4-7
4.5.2 Instruction Cache Operation........................................................................... 4-9
4.5.2.1 Interaction with Other Modules.................................................................. 4-9
4.5.2.2 Cache Coherency and Invalidation............................................................. 4-9
4.5.2.3 Caching Modes........................................................................................... 4-9
4.5.2.3.1 Cacheable Accesses.............................................................................. 4-10
4.5.2.3.2 Cache-Inhibited Accesses..................................................................... 4-10
4.5.2.4 Reset ......................................................................................................... 4-11
4.5.2.5 Cache Miss Fetch Algorithm/Line Fills ................................................... 4-11
4.5.3 Instruction Cache Programming Model........................................................ 4-12
4.5.3.1 Cache Control Register (CACR) .............................................................. 4-13
4.5.3.2 Access Control Registers (ACR0 and ACR1).......................................... 4-15
Chapter 5
Debug Support
5.1 Overview............................................................................................................. 5-1
5.2 Signal Description............................................................................................... 5-2
5.3 Real-Time Trace Support.................................................................................... 5-2
5.3.1 Begin Execution of Taken Branch (PST = 0x5)............................................. 5-4
5.4 Programming Model........................................................................................... 5-5
5.4.1 Revision A Shared Debug Resources............................................................. 5-7

viii MCF5272 User’s Manual
CONTENTS
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Number Title Page
Number
5.4.2 Address Attribute Trigger Register (AATR).................................................. 5-7
5.4.3 Address Breakpoint Registers (ABLR, ABHR)............................................. 5-9
5.4.4 Configuration/Status Register (CSR).............................................................. 5-9
5.4.5 Data Breakpoint/Mask Registers (DBR, DBMR)......................................... 5-11
5.4.6 Program Counter Breakpoint/Mask Registers (PBR, PBMR)...................... 5-12
5.4.7 Trigger Definition Register (TDR)............................................................... 5-13
5.5 Background Debug Mode (BDM).................................................................... 5-15
5.5.1 CPU Halt....................................................................................................... 5-16
5.5.2 BDM Serial Interface.................................................................................... 5-17
5.5.2.1 Receive Packet Format ............................................................................. 5-18
5.5.2.2 Transmit Packet Format............................................................................ 5-18
5.5.3 BDM Command Set...................................................................................... 5-19
5.5.3.1 ColdFire BDM Command Format............................................................ 5-20
5.5.3.1.1 Extension Words as Required............................................................... 5-20
5.5.3.2 Command Sequence Diagrams................................................................. 5-21
5.5.3.3 Command Set Descriptions ...................................................................... 5-22
5.5.3.3.1 Read A/D Register (rareg/rdreg) .......................................................... 5-23
5.5.3.3.2 Write A/D Register (wareg/wdreg) ...................................................... 5-24
5.5.3.3.3 Read Memory Location (read).............................................................. 5-25
5.5.3.3.4 Write Memory Location (write) ........................................................... 5-26
5.5.3.3.5 Dump Memory Block (dump).............................................................. 5-28
5.5.3.3.6 Fill Memory Block (fill)....................................................................... 5-30
5.5.3.3.7 Resume Execution (go) ........................................................................ 5-32
5.5.3.3.8 No Operation (nop)............................................................................... 5-33
5.5.3.3.9 Read Control Register (rcreg)............................................................... 5-34
5.5.3.3.10 Write Control Register (wcreg)............................................................ 5-35
5.5.3.3.11 Read Debug Module Register (rdmreg) ............................................... 5-36
5.5.3.3.12 Write Debug Module Register (wdmreg)............................................. 5-37
5.6 Real-Time Debug Support................................................................................ 5-37
5.6.1 Theory of Operation...................................................................................... 5-38
5.6.1.1 Emulator Mode......................................................................................... 5-39
5.6.2 Concurrent BDM and Processor Operation.................................................. 5-39
5.7 Processor Status, DDATA Definition............................................................... 5-40
5.7.1 User Instruction Set ...................................................................................... 5-40
5.7.2 Supervisor Instruction Set............................................................................. 5-44
5.8 Motorola-Recommended BDM Pinout............................................................. 5-45
Chapter 6
System Integration Module (SIM)
6.1 Features............................................................................................................... 6-1
6.2 Programming Model........................................................................................... 6-3

CONTENTS
Paragraph
Number Title Page
Number
Contents ix
6.2.1 SIM Register Memory Map............................................................................ 6-3
6.2.2 Module Base Address Register (MBAR) ....................................................... 6-4
6.2.3 System Configuration Register (SCR)............................................................ 6-5
6.2.4 System Protection Register (SPR).................................................................. 6-6
6.2.5 Power Management Register (PMR).............................................................. 6-7
6.2.6 Activate Low-Power Register (ALPR)......................................................... 6-10
6.2.7 Device Identification Register (DIR)............................................................ 6-11
6.2.8 Software Watchdog Timer............................................................................ 6-12
6.2.8.1 Watchdog Reset Reference Register (WRRR)......................................... 6-13
6.2.8.2 Watchdog Interrupt Reference Register (WIRR) ..................................... 6-13
6.2.8.3 Watchdog Counter Register (WCR)......................................................... 6-14
6.2.8.4 Watchdog Event Register (WER)............................................................. 6-14
Chapter 7
Interrupt Controller
7.1 Overview............................................................................................................. 7-1
7.2 Interrupt Controller Registers............................................................................. 7-2
7.2.1 Interrupt Controller Registers......................................................................... 7-3
7.2.2 Interrupt Control Registers (ICR1–ICR4) ...................................................... 7-4
7.2.2.1 Interrupt Control Register 1 (ICR1) ........................................................... 7-4
7.2.2.2 Interrupt Control Register 2 (ICR2) ........................................................... 7-5
7.2.2.3 Interrupt Control Register 3 (ICR3) ........................................................... 7-5
7.2.2.4 Interrupt Control Register 4 (ICR4) ........................................................... 7-6
7.2.3 Interrupt Source Register (ISR)...................................................................... 7-6
7.2.4 Programmable Interrupt Transition Register (PITR)...................................... 7-7
7.2.5 Programmable Interrupt Wakeup Register (PIWR)........................................ 7-8
7.2.6 Programmable Interrupt Vector Register (PIVR)........................................... 7-9
Chapter 8
Chip Select Module
8.1 Overview............................................................................................................. 8-1
8.1.1 Features........................................................................................................... 8-1
8.1.2 Chip Select Usage........................................................................................... 8-1
8.1.3 Boot CS0 Operation........................................................................................ 8-2
8.2 Chip Select Registers.......................................................................................... 8-2
8.2.1 Chip Select Base Registers (CSBR0–CSBR7)............................................... 8-3
8.2.2 Chip Select Option Registers (CSOR0–CSOR7) ........................................... 8-5

x MCF5272 User’s Manual
CONTENTS
Paragraph
Number Title Page
Number
Chapter 9
SDRAM Controller
9.1 Overview............................................................................................................. 9-1
9.2 SDRAM Controller Signals................................................................................ 9-1
9.3 Interface to SDRAM Devices............................................................................. 9-5
9.4 SDRAM Banks, Page Hits, and Page Misses..................................................... 9-6
9.5 SDRAM Registers .............................................................................................. 9-7
9.5.1 SDRAM Configuration Register (SDCR) ...................................................... 9-7
9.5.2 SDRAM Timing Register (SDTR)................................................................. 9-9
9.6 Auto Initialization............................................................................................. 9-10
9.7 Power-Down and Self-Refresh......................................................................... 9-10
9.8 Performance...................................................................................................... 9-11
9.9 Solving Timing Issues with SDCR[INV]......................................................... 9-13
9.10 SDRAM Interface............................................................................................. 9-16
9.10.1 SDRAM Read Accesses ............................................................................... 9-17
9.10.2 SDRAM Write Accesses .............................................................................. 9-19
9.10.3 SDRAM Refresh Timing.............................................................................. 9-21
Chapter 10
DMA Controller
10.1 DMA Data Transfer Types ............................................................................... 10-1
10.2 DMA Address Modes....................................................................................... 10-2
10.3 DMA Controller Registers................................................................................ 10-2
10.3.1 DMA Mode Register (DMR)........................................................................ 10-2
10.3.2 DMA Interrupt Register (DIR)..................................................................... 10-4
10.3.3 DMA Source Address Register (DSAR)...................................................... 10-5
10.3.4 DMA Destination Address Register (DDAR).............................................. 10-6
10.3.5 DMA Byte Count Register (DBCR)............................................................. 10-6
Chapter 11
Ethernet Module
11.1 Overview........................................................................................................... 11-1
11.1.1 Features......................................................................................................... 11-1
11.2 Module Operation............................................................................................. 11-2
11.3 Transceiver Connection.................................................................................... 11-3
11.4 FEC Frame Transmission ................................................................................. 11-4
11.4.1 FEC Frame Reception................................................................................... 11-5
11.4.2 CAM Interface.............................................................................................. 11-6
11.4.3 Ethernet Address Recognition...................................................................... 11-7