Motorola MC68030 User manual

ENHANCED 32-BIT
MICROPROCESSOR
USER'S MANUAL
THIRD EDITIO
® MOTOROLA

Introduction
Data Organization and Addressing Capabilities
Instruction Set Summary
Processing States
Signal Description
On-Chip Cache Memories
Bus Operation
Exception Processing
Memory Management Unit
Coprocessor Interface Description
Instruction Execution Timing
Applications Information
Electrical Characteristics
Ordering Information and Mechani~al Data
M68000 Family Summary'
Index

® MOTOROLA
MC68030
ENHANCED 32-811
MICROPROCESSOR USER'S
MANUAL
Third Edition
Motorola reserves the right to make changes without further notice to any products herein
to improve reliability, function or design. Motorola does not assume any liability arising out
of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights
nor the rights of others. Motorola products are not author-
ized
for use as components in life support devices or systems intended for surgical implant
into the body or intended to support or sustain life. Buyer agrees to notify Motorola of any
such intended end use whereupon Motorola shall determine availability and suitabtlity
of its
product
or products for the use intended. Motorola and ® are registered trademarks of
Motorola, Inc. Motorola, Inc. is an Equal Employment Opportunity/Affirmative Action
Employer.
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© 1990 MOlOROLA, INC.
Published by Prentice-Hall, Inc.
A Division of Simon &Schuster
El')glewood Cliffs, New Jersey 07632
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Printed in the United States of America
10 9 8 7 6 5 4 3 2
ISBN
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Prentice-Hall International (UK) limited, London
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Simon & Schuster Asia Pte. Ltd., Singapore
Editora Prentice-Hall do Brasil, Ltda., Rio de Janeiro

TABLE OF CONTENTS
Paragraph
Number
Title Page
Number
Section 1
Introduction
1.1 Features ................................................................................. 1-3
1.2 MC68030 Extensions to the M68000 Family............................... 1-4
1.3 Programming Model
............................................................... 1-4
1.4 Data Types and Addressing Modes........................................... 1-10
1.5 Instruction Set Overview......................................................... 1-10
1.6 Virtual Memory and Virtual Machine Concepts.......................... 1-12
1.6.1 Virtual Memory· ................................................................ 1-12
1.6.2 Virtual Machine ................................................................ 1-14
1.7 The Memory Management Unit................................................ 1-15
1.8 Pipelined Architecture
..................................................... ,........ 1-16
1.9 The Cache
Memories.............................................................. 1-16
Section 2
Data Organization and Addressing Capabilities
2.1 Instruction Operands............................................................... 2-1
2.2 Organization of Data in Registers............................................. 2-2
2.2.1 Data Registers ........................ ~......................................... 2-2
2.2.2 Address Registers............................................................. 2-4
2.2.3 Control Registers.............................................................. 2-4
2.3 Organization of Data in Memory............................................... 2-5
2.4 Addressing Modes........................:......................................... 2-8
2.4.1 Data Register Direct Mode................................................. 2-9
2.4.2 Address Register Direct Mode.................................. .......... 2-10
2.4.3 Address Register Indirect Mode.......................................... 2-10
2.4.4 Address Register Indirect with Postincrement Mode............. 2-10
2.4.5 Address Register Indirect with Predecrement Mode.............. 2-11
2.4.6 Address Register Indirect with Displacement Mode.............. 2-12
2.4.7 Address Register Indirect with Index (8-Bit Displacement)
Mode
............................................................................ 2-12
2.4.8 Address Register Indirect with Index
(Base Displacement)
Mode
............................................................................ 2-13
2.4.9
Memory Indirect Postindexed Mode................................... 2-14
MOTOROLA
MC68030 USER'S MANUAL
iii

TABLE OF CONTENTS (Continued)
Paragraph
Number Title Page
Number
2.4.10
2.4.11
2.4.12
2.4.13
2.4.14
2.4.15
2.4.16
2.4.17
2.4.18
2.5
2.6
2.6.1
2.6.2
2.7
2.8
2.8.1
2.8.2
2.8.3
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
3.2.10
3.2.11
3.3
3.3.1
iv
Memory Indirect Preindexed Mode..................................... 2-15
Program Counter Indirect with Displacement Mode.............. 2-16
Program Counter Indirect with Index (8-Bit Displacement)
Mode ............................................................................ 2-16
Program Counter Indirect with Index (Base Displacement)
Mode ............................................................................ 2-17
Program Counter Memory Indirect Postindexed Mode.......... 2-18
Program Counter Memory Indirect Preindexed Mode ........... 2-19
Absolute Short Addressing Mode....................................... 2-20
Absolute Long Addressing Mode........................................ 2-20
Immediate Data................................................................ 2-21
Effective Address Encoding Summary....................................... 2-22
Programmer's View of Addressing Modes................................. 2-24
Addressing Capabilities.....................................................
2-25
General Addressing Mode Summary........ .......................... 2-31
M68000 Family Addressing Compatibility.................................. 2-36
Other Data Structures
........................................................ ;..... 2-36
System
Stack................................................................... 2-36
User Program Stacks......................................................... 2-38
Queues............................................................................
2-39
Section 3
Instruction Set Summary
Instruction Format ................................................................... 3-1
Instruction Summary............................................................... 3-2
Data Movement Instructions.............................................. 3-4
Integer Arithmetic Instructions........................................... 3-5
Logical Instructions........................................................... 3-6
Shift and Rotate Instructions.............................................. 3-7
Bit Manipulation Instructions ............................................. 3-8
Bit Field Instructions......................................................... 3-9
Binary-Coded Decimal Instructions ..................................... 3-10
Program Control Instructions ............................................. 3-11
System Control Instructions............................................... 3-12
Memory Management Unit Instructions.............................. 3-13
Multiprocessor Instructions ................................................ 3-13
Integer Condition Codes .......................................................... 3-14
Condition Code
Computation............................................. 3-15
MC68030 USER'S MANUAL MOTOROLA

TABLE OF CONTENTS (Continued)
Paragraph
Number
Title Page
Number
3.3.2 Conditional Tests.............................................................. 3-17
3.4 Instruction Set
Summary ......................................................... 3-18
3.5 Instruction Examples............................................................... 3-25
3.5.1 Using the CAS and CAS2 Instructions....................................... 3-25
3.5.2 Nested Subroutine
Calls.......................................................... 3-30
3.5.3 Bit Field
Operations................................................................ 3-31
3.5.4 Pipeline Synchronization with the NOP Instruction..................... 3-32
Section 4
Processing States
4.1 Privilege Levels...................................................................... 4-2
4.1.1 Supervisor Privilege Level................................................. 4-2
4.1.2 User Privilege
Level.......................................................... 4-3
4.1.3 Changing Privilege
Level................................................... 4-4
4.2 Address Space
Types.............................................................. 4-5
4.3 Exception
Processing.............................................................. 4-6
4.3.1 Exception Vectors............................................................. 4-6
4.3.2 Exception Stack Frame....
.......................... ........................ 4-7
5.1
5.2
5.3
5.4
5.5
5.6
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.6.7
5.6.8
5.6.9
5.7
5.7.1
MOTOROLA
Section 5
Signal Description
Signal Index .......................................................................... .
Function Code Signals
(FCO-FC2) ........................................... ..
Address Bus (AO-A31) ............................................................ .
Oata Bus (00-031 )...................................................................
Transfer Size Signals
(SIZO, SIZ1) ............................................ .
Bus Control Signals
............................................................... .
Operand Cycle Start (OCS) ................................................ .
External Cycle Start (ECS). ............................................... ..
Read/Write (R/W) ............................................................. .
Read-Modify-Write Cycle (RMC) ................;
...................... ..
Address Strobe (AS) ........................................................ .
Data Strobe
(OS) .............................................................. .
Oata Buffer Enable (OBEN) ................................................ .
Oata Transfer and Size Acknowledge (OSACKO, OSACK1) .....
Synchronous Termination (STERM)
.................................. ..
Cache Control Signals ............................................................ .
Cache Inhibit Input (CIIN) .................................................. .
MC68030 USER'S MANUAL
5-2
5-4
5-4
5-4
5-4
5-5
5-5
5-5
5-5
5-5
5-5
5-6
5-6
5-6
5-6
5-7
5-7
v

Paragraph
Number
5.7.2
5.7.3
5.7.4
5.8
5.8.1
5.8.2
5.8.3
5.9
5.9.1
5.9.2
5.9.3
5.10
5.10.1
5.10.2
5.10.3
5.11
5.11.1
5.11.2
5.11.3
5.11.4
5.12
5.13
5.14
6.1
6.1.1
6.1.2
6.1.2.1
6.1.2.2
6.1.3
6.1.3.1
6.1.3.2
6.2
6.3
6.3.1
6.3.1.1
vi
TABLE OF CONTENTS (Continued)
Title
Page
Number
Cache Inhibit Output
(ClODf).... .............. ...... ..................... 5-7
Cache Burst Request (CBREQ) ............................................ 5-7
Cache Burst Acknowledge (CBACK) .................................... 5-7
Interrupt Control Signals......................................................... 5-8
Interrupt Priority level Signals........................................... 5-8
Interrupt Pending (lPEND).................................................. 5-8
Autovector (AVEC) ............................................................ 5-8
Bus Arbitration Control Signals................................................ 5-8
Bus Request (BR).............................................................. 5-8
Bus Grant (BG) ................................................................. 5-9
Bus Grant Acknowledge (BGACK) ....................................... 5-9
Bus Exception Control Signals ................................................. 5-9
Reset (RESET) .................................................................. 5-9
Halt (HALT) ...................................................................... 5-9
Bus Error (BERR) .............................................................. 5-9
Emulator Support Signals........................................................ 5-10
Cache Disable (CiSlS).......... ............................................... 5-10
MMU Disable (MMUDIS) ................................................... 5-10
Pipeline Refill (REFill) ....................................................... 5-10
Internal Microsequencer Status (STATUS)........................... 5-10
Clock (ClK) ................................ ~........................................... 5-11
Power Supply Connections ...................................................... 5-11
Signal Summary..................................................................... 5-11
Section 6
On-Chip Cache Memories
On-Chip Cache Organization and Operation...............................
6-3
Instruction Cache.............................................................. 6-4
Data Cache.......................................;............................... 6-6
Write Allocation.......................................................... 6-8
Read-Modify-Write Accesses........................................ 6-10
Cache Filling.................................................................... 6-10
Single Entry Mode...................................................... 6-10
Burst Mode Filling ...................................................... 6-15
Cache Reset .. :..•..................................................................... 6-20
Cache ControL........................................................................ 6-20
Cache Control Register...................................................... 6-20
Write Allocate............................................................. 6-21
MC68030 USER'S MANUAL MOTOROLA

Paragraph
Number
6.3.1.2
6.3.1.3
6.3.1.4
6.3.1.5
6.3.1.6
6.3.1.7
6.3.1.8
6.3.1.9
6.3.1.10
6.3.1.11
6.3.2
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
7.3
7.3.1
7.3.2
7.3.3
7.3.4
MOTOROLA
TABLE Of CONTENTS (Continued)
Title Page
Number
Data Burst Enable ....................................................... 6-21
Clear Data Cache........................................................ 6-21
Clear Entry in Data Cache............................................ 6-21
Freeze Data Cache ...................................... ;............... 6-22
Enable Data Cache...................................................... 6-22
Instruction Burst Enable.............................................. 6-22
Clear Instruction Cache................................................ 6-22
Clear Entry in Instruction Cache................................... 6-22
Freeze Instruction Cache.............................................. 6-23
Enable Instruction Cache ............................................. 6-23
Cache Address Register ..................................................... 6-23
Section 7
Bus Operation
Bus Transfer Signals ............................. ~ ................................ .
Bus Control Signals
......................................................... .
Address
Bus .................................................................... .
Address Strobe
................................................................ .
Data Bus
......................................................................... .
Data Strobe
..................................................................... .
Data Buffer Enable
........................................................... .
Bus Cycle.Termination Signals
.......................................... .
Data Transfer Mechanism
....................................................... .
Dynamic
Bus Sizing ......................................................... .
Misaligned Operands ....................................................... .
Effects
of Dynamic Bus Sizing and Operand Misalignment ....
Address, Size, and Data Bus Relationships ........................ ..
MC68030 versus MC68020 Dynamic Bus Sizing.................. ..
Cache Filling ................................................................... .
Cache Interactions ........................................................... .
Asynchronous Operation
.................................................. .
Synchronous Operation
with DSACKx ................................ .
Synchronous Operation
with STERM ................................ ..
Data Transfer Cycles .............................................................. .
Asynchronous
Read Cycle ............................................... ..
Asynchronous Write Cycle ............................................... ..
Asynchronous Read-Modify-Write Cycle ............................ ..
Synchronous Read Cycle .................................................. .
MC68030 USER'S MANUAL
7-1
7-3
7-4
7-4
7-5
7-5
7-5
7-5
7-6
7-6
7-13
7-19
7-22
7-24
7-24
7-26
7-27
7-28
7-29
7-30
7-31
7-37
7-43
7-48
vii

Paragraph
Number
7.3.5
7.3.6
7.3.7
7.4
7.4.1
7.4.1.1
7.4.1.2
7.4.1.3
7.4.2
7.4.3
7.5
7.5.1
7.5.2
7.5.3
7.5.4
7.6
7.7
7.7.1
7.7.2
7.7.3
7.7.4
7.8
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.1.8
8.1.9
8.1.10
8.1.11
viii
TABLE OF CONTENTS (Continued)
Title Page
Number
Synchronous Write Cycle................................................... 7-51
Synchronous Read-Modify-Write Cycle............................... 7-54
Burst Operation Cycles...................................................... 7-59
CPU Space Cycles................................................................... 7-68'
Interrupt Acknowledge Bus Cycles...................................... 7-69
Interrupt Acknowledge Cycle -Terminated Normally.... 7-70
Autovector Interrupt Acknowledge Cycle.......................
7-71
Spurious Interrupt Cycle .............................................. 7-74
Breakpoint Acknowledge Cycle
................................ ;.......... 7-74
Coprocessor Communication Cycles................................... 7-74
Bus Exception Control Cycles ................................................... 7-75
Bus Errors........................................................................ 7-82
Retry Operation ..................
;; ............................................ 7-89
Halt Operation.................................................................. 7-91
Double Bus Fault .............................................................. 7-94
Bus Synchronization............................................................... 7-95
Bus Arbitration....................................................................... 7-96
Bus Request..................................................................... 7-98
Bus Grant ........................................................... .... .......... 7-99
Bus Grant Acknowledge .................................................... 7-100
Bus Arbitration Control...................................................... 7-100
Reset Operation
...................................................................... 7-103
Section 8
Exception Processing
Exception Processing Sequence .......:.......................................
8-1
Reset Exception................................................................ 8-5
Bus Error Exception .............................;............................ 8-7
Address Error Exception.................................................... 8-8
Instruction Trap Exception ................................................. 8-9
Illegal Instruction and Unimplemented Instruction
Exceptions..................................................................... 8-9
Privilege Violation Exception.................................'............. 8-11
Trace Exception................................................................ 8-12
Format Error Exception ...........................;......................... 8-14
Interrupt Exceptions .......................................................... 8-14
MMU Configuration Exception ........................................... 8-21
Breakpoint Instruction Exception .....;.................................. 8-22
MC68030 USER'S MANUAL
MOTOROLA