Motorola MC68030 User manual

ENHANCED 32-BIT
MICROPROCESSOR
USER'S MANUAL
THIRD EDITIO
® MOTOROLA

Introduction
Data Organization and Addressing Capabilities
Instruction Set Summary
Processing States
Signal Description
On-Chip Cache Memories
Bus Operation
Exception Processing
Memory Management Unit
Coprocessor Interface Description
Instruction Execution Timing
Applications Information
Electrical Characteristics
Ordering Information and Mechani~al Data
M68000 Family Summary'
Index

® MOTOROLA
MC68030
ENHANCED 32-811
MICROPROCESSOR USER'S
MANUAL
Third Edition
Motorola reserves the right to make changes without further notice to any products herein
to improve reliability, function or design. Motorola does not assume any liability arising out
of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights
nor the rights of others. Motorola products are not author-
ized
for use as components in life support devices or systems intended for surgical implant
into the body or intended to support or sustain life. Buyer agrees to notify Motorola of any
such intended end use whereupon Motorola shall determine availability and suitabtlity
of its
product
or products for the use intended. Motorola and ® are registered trademarks of
Motorola, Inc. Motorola, Inc. is an Equal Employment Opportunity/Affirmative Action
Employer.
PRENTICE HALL, Englewood Cliffs, N.J. 07632

© 1990 MOlOROLA, INC.
Published by Prentice-Hall, Inc.
A Division of Simon &Schuster
El')glewood Cliffs, New Jersey 07632
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Inc.
College Technical and Reference Division
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All rights reserved. No part of this book may be
reproduced, in any form or by any means,
without permission in writing from the publisher.
Printed in the United States of America
10 9 8 7 6 5 4 3 2
ISBN
0-13-566423-3
Prentice-Hall International (UK) limited, London
Prentice-Hall of Australia Pty. limited, Sydney
Prentice-Hall Canada Inc., Toronto
Prentice-Hall Hispanoamericana, S.A., Mexico
Prentice-Hall of India Private Limited, New Delhi
Prentice-Hall of Japan, Inc., Tokyo
Simon & Schuster Asia Pte. Ltd., Singapore
Editora Prentice-Hall do Brasil, Ltda., Rio de Janeiro

TABLE OF CONTENTS
Paragraph
Number
Title Page
Number
Section 1
Introduction
1.1 Features ................................................................................. 1-3
1.2 MC68030 Extensions to the M68000 Family............................... 1-4
1.3 Programming Model
............................................................... 1-4
1.4 Data Types and Addressing Modes........................................... 1-10
1.5 Instruction Set Overview......................................................... 1-10
1.6 Virtual Memory and Virtual Machine Concepts.......................... 1-12
1.6.1 Virtual Memory· ................................................................ 1-12
1.6.2 Virtual Machine ................................................................ 1-14
1.7 The Memory Management Unit................................................ 1-15
1.8 Pipelined Architecture
..................................................... ,........ 1-16
1.9 The Cache
Memories.............................................................. 1-16
Section 2
Data Organization and Addressing Capabilities
2.1 Instruction Operands............................................................... 2-1
2.2 Organization of Data in Registers............................................. 2-2
2.2.1 Data Registers ........................ ~......................................... 2-2
2.2.2 Address Registers............................................................. 2-4
2.2.3 Control Registers.............................................................. 2-4
2.3 Organization of Data in Memory............................................... 2-5
2.4 Addressing Modes........................:......................................... 2-8
2.4.1 Data Register Direct Mode................................................. 2-9
2.4.2 Address Register Direct Mode.................................. .......... 2-10
2.4.3 Address Register Indirect Mode.......................................... 2-10
2.4.4 Address Register Indirect with Postincrement Mode............. 2-10
2.4.5 Address Register Indirect with Predecrement Mode.............. 2-11
2.4.6 Address Register Indirect with Displacement Mode.............. 2-12
2.4.7 Address Register Indirect with Index (8-Bit Displacement)
Mode
............................................................................ 2-12
2.4.8 Address Register Indirect with Index
(Base Displacement)
Mode
............................................................................ 2-13
2.4.9
Memory Indirect Postindexed Mode................................... 2-14
MOTOROLA
MC68030 USER'S MANUAL
iii

TABLE OF CONTENTS (Continued)
Paragraph
Number Title Page
Number
2.4.10
2.4.11
2.4.12
2.4.13
2.4.14
2.4.15
2.4.16
2.4.17
2.4.18
2.5
2.6
2.6.1
2.6.2
2.7
2.8
2.8.1
2.8.2
2.8.3
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
3.2.10
3.2.11
3.3
3.3.1
iv
Memory Indirect Preindexed Mode..................................... 2-15
Program Counter Indirect with Displacement Mode.............. 2-16
Program Counter Indirect with Index (8-Bit Displacement)
Mode ............................................................................ 2-16
Program Counter Indirect with Index (Base Displacement)
Mode ............................................................................ 2-17
Program Counter Memory Indirect Postindexed Mode.......... 2-18
Program Counter Memory Indirect Preindexed Mode ........... 2-19
Absolute Short Addressing Mode....................................... 2-20
Absolute Long Addressing Mode........................................ 2-20
Immediate Data................................................................ 2-21
Effective Address Encoding Summary....................................... 2-22
Programmer's View of Addressing Modes................................. 2-24
Addressing Capabilities.....................................................
2-25
General Addressing Mode Summary........ .......................... 2-31
M68000 Family Addressing Compatibility.................................. 2-36
Other Data Structures
........................................................ ;..... 2-36
System
Stack................................................................... 2-36
User Program Stacks......................................................... 2-38
Queues............................................................................
2-39
Section 3
Instruction Set Summary
Instruction Format ................................................................... 3-1
Instruction Summary............................................................... 3-2
Data Movement Instructions.............................................. 3-4
Integer Arithmetic Instructions........................................... 3-5
Logical Instructions........................................................... 3-6
Shift and Rotate Instructions.............................................. 3-7
Bit Manipulation Instructions ............................................. 3-8
Bit Field Instructions......................................................... 3-9
Binary-Coded Decimal Instructions ..................................... 3-10
Program Control Instructions ............................................. 3-11
System Control Instructions............................................... 3-12
Memory Management Unit Instructions.............................. 3-13
Multiprocessor Instructions ................................................ 3-13
Integer Condition Codes .......................................................... 3-14
Condition Code
Computation............................................. 3-15
MC68030 USER'S MANUAL MOTOROLA

TABLE OF CONTENTS (Continued)
Paragraph
Number
Title Page
Number
3.3.2 Conditional Tests.............................................................. 3-17
3.4 Instruction Set
Summary ......................................................... 3-18
3.5 Instruction Examples............................................................... 3-25
3.5.1 Using the CAS and CAS2 Instructions....................................... 3-25
3.5.2 Nested Subroutine
Calls.......................................................... 3-30
3.5.3 Bit Field
Operations................................................................ 3-31
3.5.4 Pipeline Synchronization with the NOP Instruction..................... 3-32
Section 4
Processing States
4.1 Privilege Levels...................................................................... 4-2
4.1.1 Supervisor Privilege Level................................................. 4-2
4.1.2 User Privilege
Level.......................................................... 4-3
4.1.3 Changing Privilege
Level................................................... 4-4
4.2 Address Space
Types.............................................................. 4-5
4.3 Exception
Processing.............................................................. 4-6
4.3.1 Exception Vectors............................................................. 4-6
4.3.2 Exception Stack Frame....
.......................... ........................ 4-7
5.1
5.2
5.3
5.4
5.5
5.6
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.6.7
5.6.8
5.6.9
5.7
5.7.1
MOTOROLA
Section 5
Signal Description
Signal Index .......................................................................... .
Function Code Signals
(FCO-FC2) ........................................... ..
Address Bus (AO-A31) ............................................................ .
Oata Bus (00-031 )...................................................................
Transfer Size Signals
(SIZO, SIZ1) ............................................ .
Bus Control Signals
............................................................... .
Operand Cycle Start (OCS) ................................................ .
External Cycle Start (ECS). ............................................... ..
Read/Write (R/W) ............................................................. .
Read-Modify-Write Cycle (RMC) ................;
...................... ..
Address Strobe (AS) ........................................................ .
Data Strobe
(OS) .............................................................. .
Oata Buffer Enable (OBEN) ................................................ .
Oata Transfer and Size Acknowledge (OSACKO, OSACK1) .....
Synchronous Termination (STERM)
.................................. ..
Cache Control Signals ............................................................ .
Cache Inhibit Input (CIIN) .................................................. .
MC68030 USER'S MANUAL
5-2
5-4
5-4
5-4
5-4
5-5
5-5
5-5
5-5
5-5
5-5
5-6
5-6
5-6
5-6
5-7
5-7
v

Paragraph
Number
5.7.2
5.7.3
5.7.4
5.8
5.8.1
5.8.2
5.8.3
5.9
5.9.1
5.9.2
5.9.3
5.10
5.10.1
5.10.2
5.10.3
5.11
5.11.1
5.11.2
5.11.3
5.11.4
5.12
5.13
5.14
6.1
6.1.1
6.1.2
6.1.2.1
6.1.2.2
6.1.3
6.1.3.1
6.1.3.2
6.2
6.3
6.3.1
6.3.1.1
vi
TABLE OF CONTENTS (Continued)
Title
Page
Number
Cache Inhibit Output
(ClODf).... .............. ...... ..................... 5-7
Cache Burst Request (CBREQ) ............................................ 5-7
Cache Burst Acknowledge (CBACK) .................................... 5-7
Interrupt Control Signals......................................................... 5-8
Interrupt Priority level Signals........................................... 5-8
Interrupt Pending (lPEND).................................................. 5-8
Autovector (AVEC) ............................................................ 5-8
Bus Arbitration Control Signals................................................ 5-8
Bus Request (BR).............................................................. 5-8
Bus Grant (BG) ................................................................. 5-9
Bus Grant Acknowledge (BGACK) ....................................... 5-9
Bus Exception Control Signals ................................................. 5-9
Reset (RESET) .................................................................. 5-9
Halt (HALT) ...................................................................... 5-9
Bus Error (BERR) .............................................................. 5-9
Emulator Support Signals........................................................ 5-10
Cache Disable (CiSlS).......... ............................................... 5-10
MMU Disable (MMUDIS) ................................................... 5-10
Pipeline Refill (REFill) ....................................................... 5-10
Internal Microsequencer Status (STATUS)........................... 5-10
Clock (ClK) ................................ ~........................................... 5-11
Power Supply Connections ...................................................... 5-11
Signal Summary..................................................................... 5-11
Section 6
On-Chip Cache Memories
On-Chip Cache Organization and Operation...............................
6-3
Instruction Cache.............................................................. 6-4
Data Cache.......................................;............................... 6-6
Write Allocation.......................................................... 6-8
Read-Modify-Write Accesses........................................ 6-10
Cache Filling.................................................................... 6-10
Single Entry Mode...................................................... 6-10
Burst Mode Filling ...................................................... 6-15
Cache Reset .. :..•..................................................................... 6-20
Cache ControL........................................................................ 6-20
Cache Control Register...................................................... 6-20
Write Allocate............................................................. 6-21
MC68030 USER'S MANUAL MOTOROLA

Paragraph
Number
6.3.1.2
6.3.1.3
6.3.1.4
6.3.1.5
6.3.1.6
6.3.1.7
6.3.1.8
6.3.1.9
6.3.1.10
6.3.1.11
6.3.2
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
7.3
7.3.1
7.3.2
7.3.3
7.3.4
MOTOROLA
TABLE Of CONTENTS (Continued)
Title Page
Number
Data Burst Enable ....................................................... 6-21
Clear Data Cache........................................................ 6-21
Clear Entry in Data Cache............................................ 6-21
Freeze Data Cache ...................................... ;............... 6-22
Enable Data Cache...................................................... 6-22
Instruction Burst Enable.............................................. 6-22
Clear Instruction Cache................................................ 6-22
Clear Entry in Instruction Cache................................... 6-22
Freeze Instruction Cache.............................................. 6-23
Enable Instruction Cache ............................................. 6-23
Cache Address Register ..................................................... 6-23
Section 7
Bus Operation
Bus Transfer Signals ............................. ~ ................................ .
Bus Control Signals
......................................................... .
Address
Bus .................................................................... .
Address Strobe
................................................................ .
Data Bus
......................................................................... .
Data Strobe
..................................................................... .
Data Buffer Enable
........................................................... .
Bus Cycle.Termination Signals
.......................................... .
Data Transfer Mechanism
....................................................... .
Dynamic
Bus Sizing ......................................................... .
Misaligned Operands ....................................................... .
Effects
of Dynamic Bus Sizing and Operand Misalignment ....
Address, Size, and Data Bus Relationships ........................ ..
MC68030 versus MC68020 Dynamic Bus Sizing.................. ..
Cache Filling ................................................................... .
Cache Interactions ........................................................... .
Asynchronous Operation
.................................................. .
Synchronous Operation
with DSACKx ................................ .
Synchronous Operation
with STERM ................................ ..
Data Transfer Cycles .............................................................. .
Asynchronous
Read Cycle ............................................... ..
Asynchronous Write Cycle ............................................... ..
Asynchronous Read-Modify-Write Cycle ............................ ..
Synchronous Read Cycle .................................................. .
MC68030 USER'S MANUAL
7-1
7-3
7-4
7-4
7-5
7-5
7-5
7-5
7-6
7-6
7-13
7-19
7-22
7-24
7-24
7-26
7-27
7-28
7-29
7-30
7-31
7-37
7-43
7-48
vii

Paragraph
Number
7.3.5
7.3.6
7.3.7
7.4
7.4.1
7.4.1.1
7.4.1.2
7.4.1.3
7.4.2
7.4.3
7.5
7.5.1
7.5.2
7.5.3
7.5.4
7.6
7.7
7.7.1
7.7.2
7.7.3
7.7.4
7.8
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.1.8
8.1.9
8.1.10
8.1.11
viii
TABLE OF CONTENTS (Continued)
Title Page
Number
Synchronous Write Cycle................................................... 7-51
Synchronous Read-Modify-Write Cycle............................... 7-54
Burst Operation Cycles...................................................... 7-59
CPU Space Cycles................................................................... 7-68'
Interrupt Acknowledge Bus Cycles...................................... 7-69
Interrupt Acknowledge Cycle -Terminated Normally.... 7-70
Autovector Interrupt Acknowledge Cycle.......................
7-71
Spurious Interrupt Cycle .............................................. 7-74
Breakpoint Acknowledge Cycle
................................ ;.......... 7-74
Coprocessor Communication Cycles................................... 7-74
Bus Exception Control Cycles ................................................... 7-75
Bus Errors........................................................................ 7-82
Retry Operation ..................
;; ............................................ 7-89
Halt Operation.................................................................. 7-91
Double Bus Fault .............................................................. 7-94
Bus Synchronization............................................................... 7-95
Bus Arbitration....................................................................... 7-96
Bus Request..................................................................... 7-98
Bus Grant ........................................................... .... .......... 7-99
Bus Grant Acknowledge .................................................... 7-100
Bus Arbitration Control...................................................... 7-100
Reset Operation
...................................................................... 7-103
Section 8
Exception Processing
Exception Processing Sequence .......:.......................................
8-1
Reset Exception................................................................ 8-5
Bus Error Exception .............................;............................ 8-7
Address Error Exception.................................................... 8-8
Instruction Trap Exception ................................................. 8-9
Illegal Instruction and Unimplemented Instruction
Exceptions..................................................................... 8-9
Privilege Violation Exception.................................'............. 8-11
Trace Exception................................................................ 8-12
Format Error Exception ...........................;......................... 8-14
Interrupt Exceptions .......................................................... 8-14
MMU Configuration Exception ........................................... 8-21
Breakpoint Instruction Exception .....;.................................. 8-22
MC68030 USER'S MANUAL
MOTOROLA

Paragraph
Number
8.1.12
8.1.13
8.2
8.2.1
8.2.2
8.2.3
8.3
8.4
9.1
9.1.1
9.1.2
9.2
9.2.1
9.2.2
9.2.3
9.3
9.4
9.5
9.5.1
9.5.1.1
9.5.1.2
9.5.1.3
9.5.1.4
9.5.1.5
9.5.1.6
9.5.1.7
9.5.1.8
9.5.1.9
9.5.1.10
9.5.1.11
9.5.1.12
9.5.2
9.5.3
9.5.3.1
9.5.3.2
MOTOROLA
TABLE OF CONTENTS (Continued)
Title Page
Number
Multiple Exceptions........................................................... 8-23
Return
from Exception ............................................ '.......... 8-24
Bus Fault Recovery................................................................. 8-27
Special Status Word (SSW).............................. .................. 8-28
Using Software To Complete the Bus Cycles....................... 8-29
Completing the Bus Cycles
with RTE .................................. 8-31
Coprocessor Considerations..................................................... 8-32
Exception Stack Frame
Formats............................................... 8-32
Section 9
Memory Management Unit
Translation Table Structure ..................................................... .
Translation Control
.......................................................... .
Translation Table Descriptors
............................................ .
Address Translation
............................................................... .
General Flow
for Address Translation ................................ .
Effect
of RESET on MMU .................................................. .
Effect
of MMUDIS on Address Translation .......................... .
Transparent Translation
.......................................................... .
Address Translation Cache
.................................................... ..
Translation Table Details
........................................................ .
Descriptor Details
............................................................ .
Descriptor Field Definitions
........................................ ..
Root Pointer Descriptor .............................................. .
Short-Format Table Descriptor
.................................... .
Long-Format Table Descriptor
.................................... ..
Short-Format Early Termination Page Descriptor.......... ..
Long-Format Early Termination Page Descriptor ............
Short-Format
Page Descriptor .................................... ..
Long-Format
Page Descriptor ...................................... .
Short-Format Invalid Descriptor.
.................................. .
Long-Format Invalid Descriptor
.................................. ..
Short-Format Indirect Descriptor
................................ ..
Long-Format Indirect Descriptor
.................................. .
General Table Search
....................................................... .
Variations in Translation Table Structure
............................ .
Early Termination and Contiguous
Memory .................. .
Indirection ................................................................. .
MC68030 USER'S MANUAL
9-6
9-8
9-10
9-13
9-13
9-15
9-15
9-16
9-17
9-20
9-20
9-20
9-23
9-24
9-24
9-25
9-25
9-26
9-26
9-26
9-27
9-27
9-28
9-28
9-33
9-33
9-34
ix

Paragraph
Number
9.5.3.3
9.5.3.4
9.5.3.5
9.5.4
9.5.5
9.5.5.1
9.5.5.2
9.5.5.3
9.5.5.4
9.6
9.7
9.7.1
9.7.2
9.7.3
9.7.4
9.7.5
9.7.5.1
9.7.5.2
9.7.5.3
9.8
TABLE OF CONTENTS (Continued)
Title Page
Number
Table Sharing between Tasks....................................... 9-37
Paging of Tables......................................................... 9-37
Dynamic Allocation
of Tables....................................... 9-40
Detail
of Table Search Operations...................................... 9-40
Protection........................................................................ 9-43
Function Code Lookup................................................. 9-45
Supervisor Translation Tree
......................................... 9-48
Supervisor Only.......................................................... 9-48
Write Protect.............................................................. 9-48
MC68030 and MC68851 MMU Differences .................................
9-51
Registers................................................................................ 9-52
Root Pointer Registers....................................................... 9-52
Translation Control Register............................................... 9-54
Transparent Translation Registers...................................... 9-57
MMU Status Register ......................................................... 9-59
Register Programming Considerations................................
9-61
Register Side Effects................................................... 9-61
MMU Status Register Decoding.................................... 9-61
MMU Configuration Exception ..................................... 9-62
MMU Instructions..................................... '" .................. -.. ....... 9-63
Defining and Using
Page Tables in an Operating System............ 9-65
Root Pointer Registers....................................................... 9-65
Task
Memory Map Definition............................................. 9-66
Impact of MMU Features on Table Definition....................... 9-68
Number
of Table Levels .............................................. 9-68
Initial Shift Count...............................;........................ 9-69
Limit Fields ................................................................ 9-70
Early Termination
Page Descriptors .............................. 9-70
Indirect Descriptors..................................................... 9-71
Using Unused Descriptor Bits ...................................... 9-71
9.9
9.9.1
9.9.2
9.9.3
9.9.3.1 .
9.9.3.2
9.9.3.3
9.9.3.4
9.9.3.5
9.9.3.6
9.10
9.10.1
9.10.2
9.10.3
An Example of Paging Implementation in an Operating System.. 9-72
System Description ........................................................... 9-72
Allocation Routines ........................................................... 9-78
Bus Error Handler Routine................................................. 9-82
x MC68030 USER'S
MANUAL
MOTOROLA

Paragraph
Number
TABLE OF CONTENTS (Continued)
Title
Section
10
Coprocessor Interface Description
Page
Number
10.1
10.1.1
10.1.2
10.1.3
10.1.4
10.1.4.1
10.1.4.2
10.1.4.3
10.2
10.2.1
10.2.1.1
10.2.1.2
10.2.2
10.2.2.1
10.2.2.1.1
10.2.2.1.2
10.2.2.2
10.2.2.2.1
10.2.2.2.2
10.2.2.3
Introduction
........................................................................... 10-1
Interface Features ............................................................. 10-2
Concurrent Operation
Support ........................................... 10-3
Coprocessor Instruction Format.
......................................... 10-4
Coprocessor System Interface
............................................ 10-5
Coprocessor Classification
........................................... 10-5
Processor-Coprocessor Interface
................................... 10-6
Coprocessor Interface Register Selection
....................... 10-8
Coprocessor Instruction Types
................................................. 10-9
10.2.2.3.1
10.2.2.3.2
10.2.2.4
10.2.2.4.1
10.2.2.4.2
10.2.3
10.2.3.1
10.2.3.2
10.2.3.2.1
10.2.3.2.2
10.2.3.2.3
10.2.3.2.4
10.2.3.3
10.2.3.3.1
10.2.3.3.2
MOTOROLA
Coprocessor General Instructions ....................................... 10-9
Format.
...................................................................... 10-10
Protocol
..................................................................... 10-11
Coprocessor Conditional Instructions .................................. 10-12
Branch
On Coprocessor Condition Instruction ................ 10-13
Format.
................................................................ 10-14
Protocol ............................................................... 10-15
Set On Coprocessor Condition Instruction ..................... 10-15
Format.
................................................................ 10-15
Protocol ............................................................... 10-16
Test Coprocessor Condition, Decrement and
Branch Instruction
.................................................... 10-17
Format.
................................................................ 10-17
Protocol ............................................................... 10-18
Trap
On Coprocessor Condition ................................... 10-18
Format.
............................. ' ................................... 10-18
Protocol ............................................................... 10-19
Coprocessor Save and Restore Instructions
......................... 10-20
Coprocessor Internal State Frames ............................... 10-20
Coprocessor Format Words ......................................... 10-22
Empty/Reset Format
Word ..................................... 10-22
Not I;leady Format Word ........................................ 10-23
Invalid Format Word ............................................. 10-23
Valid Format Word
................................................ 10-24
Coprocessor Context Save Instruction
........................... 10-24
Format.
................................................................ 10-24
Protocol ............................................................... 10-25
MC68030 USER'S MANUAL xi

TABLE OF CONTENTS (Continued)
Paragraph
Number
Title Page
Number
10.2.3.4
10.2.3.4.1
10.2.3.4.2
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.3.7
10.3.8
10.3.9
10.3.10
10.3.11
10.4
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
10.4.7
10.4.8
10.4.9
10.4.10
10.4.11
10.4.12
10.4.13
10.4.14
10.4.15
10.4.16
10.4.17
10.4.18
10.4.19
10.4.20
10.5
10.5.1
xii
Coprocessor Context Restore Instruction ....................... 10-27
Format. ................................................................ 10-27
Protocol
............................................................... 10-28
Coprocessor Interface Register Set ........................................... 10-29
Response CIR ................................... , ............................... 10-29
Control
CI R ...................................................................... 10-30
Save CI R .......................................................................... 10-30
Restore CIR ...................................................................... 10-31
Operation Word CIR .......................................................... 10-31
Command CIR .................................................................. 10-31
Condition CIR ................................................................... 10-31
Operand CIR ..................................................................... 10-32
Register Select CIR ............................................................ 10-32
Instruction Address
CIR ..................................................... 10-33
Operand Address
CIR ........................................................ 10-33
Coprocessor Response Primitives ............................................. 10-33
ScanPC ............................................................................ 10-34
Coprocessor Response Primitive General Format ................. 10-35
Busy Primitive"',' .............................................................. 10-36
Null Primitive
................................................................... 10-37
Supervisor Check Primitive ................................................ 10-40
Transfer Operation Word Primitive ..................................... 10-40
Transfer from Instruction Stream Primitive, .......................... 10-41
Evaluate and Transfer Effective Address Primitive ................ 10-42
Evaluate Effective Address and Transfer Data Primitive ........ 10-43
Write to Previously Evaluated Effective Address Primitive..... 10-46
Take Address and Transfer Data Primitive ........................... 10-48
Transfer to/from Top of Stack Primitive ............................... 10-49
Transfer Single Main Processor Register Primitive ............... 10-50
Transfer Main Processor Control Register Primitive .............. 10-50
Transfer Multiple Main Processor Registers Primitive ........... 10-52
Transfer Multiple Coprocessor Registers Primitive ................ 10-52
Transfer Status Register and ScanPC Primitive .................... 10-55
Take Pre-Instruction Exception Primitive .............................. 10-56
Take Mid:'lnstruction Exception Primitive ............................. 10-58
Take Post-Instruction Exception Primitive ............................ 10-60
Exceptions ............................................................................. 10-61
Coprocessor-Detected Exceptions ....................................... 10-61
MC68030 USER'S MANUAL
MOTOROLA

TABLE OF CONTENTS (Continued)
Paragraph
Number Title Page Number
10.5.1.1
10.5.1.2
10.5.1.3
10.5.1.4
10.5.1.5
10.5.2
10.5.2.1
10.5.2.2
10.5.2.3
10.5.2.4
10.5.2.5
10.5.2.6
10.5.2.7
10.5.2.8
10.5.3
10.6
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.5.1
11.2.5.2
11.2.5.3
11.2.6
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.4
11.5
Coprocessor-Detected Protocol Violations
..................... 10-62
Coprocessor-Detected Illegal Command or Condition
Words .................................................................... 10-63
Coprocessor Data-Processing Exceptions .... ~ ................. 10-63
Coprocessor System-Related Exceptions ....................... 10-64
Format Errors ............................................................. 10-64
Main-Processor-Detected Exceptions ................................... 10-65
Protocol Violations
...................................................... 10-65
F-Line Emulator Exceptions .......................................... 10-68
Privilege Violations
..................................................... 10-69
cpTRAPcc Instruction Traps ......................................... 10-69
Trace Exceptions ........................................................ 10-70
Interrupts
................................................................... 10-71
Format Errors ............................................................. 10-71
Address and Bus Errors ............................................... 10-72
Coprocessor Reset ............................................................ 10-72
Coprocessor Summary ........................ : ................................... 10-72
Section 11
Instruction Execution Timing
Performance Tradeoffs ............................................................ 11-1
Resource Scheduling ............................................................... 11-2
Microsequencer
...................................................... ;......... 11-2
Instruction Pipe ................................................................ 11-2
Instruction Cache .............................................................. 11-4
Data Cache
....................................................................... 11-4
Bus Controller Resources
................................................... 11-4
Instruction Fetch Pending Buffer ................................... 11-5
Write Pending Buffer
................................................... 11-5
Micro Bus Controller ................................................... 11-5
Memory Management Unit ................................................ 11-6
Instruction Execution Timing Calculations ................................. 11-6
Instruction-Cache
Case ...................................................... 11-6
Overlap and Best Case ...................................................... 11-7
Average No-Cache
Case .................................................... 11-8
Actual Instruction-Cache-Case Execution Time Calculations... 11-11
Effect of Data Cache ................................................................ 11-16
Effect
of Wait States ................................................................ 11-18
MOTOROLA MC68030 USER'S MANUAL xiii

TABLE OF CONTENTS (Continued)
Paragraph
Number Title .Page
Number
11.6
11.6.1
11.6.2
11.6.3
11.6.4
11.6.5
11.6.6
11.6.7
11.6.8
11.6.9
11.6.10
11.6.11
11.6.12
11.6.13
11.6.14
11.6.15
11.6.16
11.6.17
11.6.18
11.7
11.7.1
11.7.2
11.8
11.9
Instruction Timing Tables .......... : ............................................. 11-24
Fetch Effective Address (fea) ...;
.......................................... 11-26
Fetch
Immediate Effective Address (fiea) ............................. 11-28
Calculate Effective Address (cea) ........................................ 11-30
Calculate
Immediate Effective Address Mode (ciea). ............. 11-32
Jump Effective Address ..................................................... 11-35
MOVE Instruction .............................................................. 11-37
Special-Purpose MOVE
Instruction ...................................... 11-39
Arithmetical/Logical Instructions ......................................... 11-40
Immediate Arithmetical/Logical Instructions ......................... 11-42
Binary-Coded Decimal and Extended Instructions
................. 11-43
Single Operand Instructions ............................................... 11-44
Shift/Rotate Instructions
.................................................... 11-45
.Bit
Manipulation Instructions ............................................. 11-46
Bit Field
Manipulation Instructions ....: ................................. 11-47
Conditional Branch Instructions ........... · ............................... 11-48
Control Instructions ........................................................... 11·:-49
Exception-Related Instructions and Operations .................... 11-50
Save and Restore Operations ............................................. 11-51
Address Translation Tree Search
Timing ................................... 11-51
MMU Effective Address Calculation .................................... 11-58
MMU Instruction Timing .................................................... 11-60
Interrupt Latency .................................................................... 11-61
Bus
Arbitration Latency ............................................................ 11-62
Section 12
Applications Information
12.1 Adapting the MC68030 to MC68020 Designs .............................. 12-1
12.1.1 Signal Routing .................................................................. 12-2
12.1.2
Hardware Differences ........................................................ 12-3
12.1.3
Software Differences ......................................................... 12-4
12.2 Floating-Point Units
................................................................. 12-5
12.3 Byte Select Logic
for the MC68030 ........................................... 12-9
12.4
Memory Interface ................................................................... 12-11
12.4.1 Access
Time Calculations .................................................. 12-14
12.4.2 Burst
Mode Cycles ............................................................ 12-17
12.5 Static RAM
Memory Banks ...................................................... 12-18
12.5.1 A
Two Clock Synchronous Memory Bank Using SRAMs ....... 12-18
xiv MC68030 USER'S
MANUAL
MOTOROLA

Paragraph
Number
TABLE OF CONTENTS (Concluded)
Title Page
Number
A 2-1-1-1 Burst Mode Memory Bank Using SRAMs .............. 12-24
A 3-1-1-1 Burst Mode Memory Bank Using SRAMs ............... 12-27
12.5.2
12.5.3
12.6
12.6.1
12.6.2
12.7
12.7.1
12.7.2
12.8
External Caches
...................................................................... 12-30
Cache Implementation
....................................................... 12-32
Instruction-Only External Cache Implementations................. 12-35
Debugging Aids
...................................................................... 12-35
STATUS and
REFILL .......................................................... 12-36
Real-Time Instruction Trace
............................................... 12-39
Power and Ground Considerations ........................................... 12-43
Section 13
Electrical Characteristics
13.1 Maximum Ratings ................................................................... 13-1
13.2 Thermal Characteristics - PGA Package ................................... 13-1
Section 14
Ordering Information and Mechanical Data
14.1 Standard MC68030 Ordering Information .................................. 14-1
14.2 Pin Assignments - Pin Grid Array (RC Suffix)........................... 14-2
14.3
Pin Assignments -Ceramic Surface Mount (FE Suffix) .............. 14-3
14.4 Package Dimensions
............................................................... 14-4
MOTOROLA
Appendix A
M68000 Family Summary
Index
MC68030 USER'S MANUAL xv

Figure
Number
1-1
1-2
1-3
1-4
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
3-1
3-2
3-3
3-4
3-5
4-1
5-1
6-1
6-2
6-3
LIST OF ILLUSTRATIONS
Page
Title
Number
Block Diagram ..................................................................... 1-2
User Programming Model .................................................... 1-6
Supervisor Programming Model Supplement .........................
1-7
Status Register.................................................................... 1-8
Memory Operand Address.................................................... 2-6
Memory Data Organization .. ................................................. 2-7
Single Effective Address Instruction Operation Word............... 2-8
Effective Address Specification Formats................................. 2-23
Using
SIZE in the Index Selection.......................................... 2-25
Using Absolute Address
with Indexes.................................... 2-26
Addressing Array
Items........................................................ 2-27
Using Indirect Absolute
Memory Addressing.......................... 2-28
Accessing
an Item in a Structure Using Pointer...... ~................ 2-28
Indirect Addressing, Suppressed Index Register...................... 2-29
Preindexed Indirect Addressing............................................. 2-29
Postindexed Indirect Addressing ........................................... 2-30
Preindexed Indirect Addressing with Outer Displacement........ 2-30
Postindexed Indirect Addressing with Outer Displacement....... 2-31
M68000 Family Address Extension Words.............................. 2-37
Instruction Word General Format .......................................... 3-1
Linked List Insertion............................................................. 3-26
Linked List Deletion.............................................................. 3-27
Doubly Linked List Insertion.................................................. 3-29
Doubly Linked List
Deletion.................................................. 3-30
General Exception Stack Frame .............................................
4-7
Functional Signal Groups ..................................................... 5-1
Internal Caches and the MC68030.......................................... 6-2
On-Chip Instruction Cache Organization................................. 6-5
On-Chip Data Cache Organization.......................................... 6-7
MOTOROLA MC68030 USER'S
MANUAL
xvii

Figure
Number
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15.
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
7-17
7-18
7-19
xviii
LIST OF ILLUSTRATIONS (Continued)
Page
Title Number
No-Write-Allocation and Write-Allocation Mode Exampl~s ....... 6-9
Single Entry Mode Operation -8-Bit Port.............................. 6-11
Single Entry Mode Operation -16-Bit Port............................ 6-12
Single Entry Mode Operation -32-Bit Port............................ 6-12
Single Entry Mode Operation - ~Misaligned Long Word and
8-Bit Port.........................................................................
6-13
Single Entry Mode Operation -Misaligned Long Word and
16-Bit Port........................................................................ 6-14
Single Entry Mode Operation -Misaligned Long Word and
32-Bit DSACKx Port...........................................................
6-15
Burst Operation Cycles and Burst Mode................................. 6-17
Burst Filling Wraparound Example........................................ 6-17
Deferred Burst Filling Example.............................................. 6-18
Cache Control Register......................................................... 6-21
Cache Address Register........................................................ 6-23
Relationship Between External and Internal Signals................ 7-2
Asynchronous Input Sample Window.................................... 7-3
Internal Operand Representation........................................... 7-8
MC68030 Interface to Various Port Sizes................................ 7-9
Example of Long-Word Transfer to Word Port ........................ 7-11
Long-Word Operand Write Timing (16-Bit Data Port) ............... 7-12
Example of Word Transfer to Byte Port.................................. 7-13
Word Operand Write Timing (8-Bit Data Port) ......................... 7-14
Misaligned Long-Word Transfer to Word Port Example........... 7-15
Misaligned Long-Word Transfer to Word Port.......................... 7-16
Misaligned Cachable Long-Word Transfer from Word Port
Example .............................................'............................. 7-17
Misaligned Word Transfer to Word Port Example.................... 7-17
Misaligned Word Transfer to Word Port................................. 7-18
Example
of Misaligned Cachable Word Transfer from Word
Bus ................................................................................. 7-20
Misaligned Long-Word Transfer to Long-Word Port................. 7-20
Misaligned Write Cycles to Long-Word Port............................ 7-21
Misaligned Cachable Long-Word Transfer from Long-Word
Bus ................................................................................. 7-22
Byte Data Select Generation
for 16- and 32-Bit Ports ............... 7-25
Asynchronous Long-Word
Read Cycle Flowchart.................... 7-32
MC68030 USER'S MANUAL MOTOROLA