Motorola MVME162FX User manual

MVME162FX
Embedded Controller
Programmer’s
Reference Guide
V162FXA/PG1

Notice
While reasonable efforts have been made to assure the accuracy of this
document, Motorola, Inc. assumes no liability resulting from any omissions in
this document, or from the use of the information obtained therein. Motorola
reserves the right to revise this document and to make changes from time to
time in the content hereof without obligation of Motorola to notify any person
of such revision or changes.
No part of this material may be reproduced or copied in any tangible medium,
or stored in a retrieval system, or transmitted in any form, or by any means,
radio, electronic, mechanical, photocopying, recording or facsimile, or
otherwise, without the prior written permission of Motorola, Inc.
It is possible that this publication may contain reference to, or information
about Motorola products (machines and programs), programming, or services
that are not announced in your country. Such references or information must
not be construed to mean that Motorola intends to announce such Motorola
products, programming, or services in your country.
Restricted Rights Legend
If the documentation contained herein is supplied, directly or indirectly, to the
U.S. Government, the following notice shall apply unless otherwise agreed to
in writing by Motorola, Inc.
Use, duplication, or disclosure by the Government is subject to restrictions as
set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and
Computer Software clause at DFARS 252.227-7013.
Motorola, Inc.
Computer Group
2900 South Diablo Way
Tempe, Arizona 85282

Preface
This manual provides board level information and detailed ASIC chip
information including register bit descriptions for the MVME162FX
Embedded Controller. The information contained in this manual applies to the
following MVME162FX models:
This manual is intended for anyone who wants to program these boards in
order to design OEM systems, supply additional capability to an existing
compatible system, or work in a lab environment for experimental purposes.
A basic knowledge of computers and digital logic is assumed.
To use this manual, you should be familiar with the publications listed below
in Related Documentation .
MVME162-410 MVME162-420 MVME162-430
MVME162-411 MVME162-421 MVME162-431
MVME162-412 MVME162-422 MVME162-432
MVME162-413 MVME162-423 MVME162-433
MVME162-440 MVME162-450 MVME162-460
MVME162-441 MVME162-451 MVME162-461
MVME162-442 MVME162-452 MVME162-462
MVME162-443 MVME162-453 MVME162-463
MVME162-510A MVME162-520A MVME162-530A
MVME162-511A MVME162-521A MVME162-531A
MVME162-512A MVME162-522A MVME162-532A
MVME162-513A MVME162-523A MVME162-533A

Manual Terminology
Throughout this manual, a convention is used which precedes data and
address parameters by a character identifying the numeric format as follows:
For example, "12" is the decimal number twelve, and "$12" is the decimal
number eighteen.
Unless otherwise specified, all address references are in hexadecimal.
An asterisk (*) following the signal name for signals which are level significant
denotes that the signal is true or valid when the signal is low. An asterisk (*)
following the signal name for signals which are edge significant denotes that the
actions initiated by that signal occur on high to low transition.
In this manual, assertion and negation are used to specify forcing a signal to a
particular state. In particular, assertion and assert refer to a signal that is active
or true; negation and negate indicate a signal that is inactive or false. These
terms are used independently of the voltage level (high or low) that they
represent.
Data and address sizes are defined as follows:
❏ A byte is eight bits, numbered 0 through 7, with bit 0 being the least
significant.
❏ A word is 16 bits, numbered 0 through 15, with bit 0 being the least
significant.
❏ A longword is 32 bits, numbered 0 through 31, with bit 0 being the least
significant.
The terms control bit, status bit, true, and false are used extensively in this
document. The term control bit is used to describe a bit in a register that can be
set and cleared under software control. The term true is used to indicate that a
bit is in the state that enables the function it controls. The term false is used to
indicate that the bit is in the state that disables the function it controls. In all
tables, the terms 0 and 1 are used to describe the actual value that should be
written to the bit, or the value that it yields when read. The term status bit is
used to describe a bit in a register that reflects a specific condition. The status
bit can be read by software to determine operational or exception conditions.
$ dollar speciÞes a hexadecimal character
% percent speciÞes a binary number
& ampersand speciÞes a decimal number

The computer programs stored in the Read Only Memory of this device contain
material copyrighted by Motorola Inc., Þrst published 1990, and may be used only
under a license such as the License for Computer Programs (Article 14) contained in
Motorola's Terms and Conditions of Sale, Rev. 1/79.
!
WARNING
This equipment generates, uses, and can radiate radio
frequency energy and if not installed and used in
accordance with the instructions manual, may cause
interference to radio communications. It has been tested
and found to comply with the limits for a Class A
Computing Device pursuant to Subpart J of part 15 of FCC
rules, which are designed to provide reasonable protection
against such interference when operated in a commercial
environment. Operation of this equipment in a residential
area is likely to cause interference in which case the user, at
the userÕs own expense, will be required to take whatever
measures necessary to correct the interference.

Related Documentation
The publications in the table below are applicable to the MVME162FX and
may provide additional helpful information. If not shipped with this product,
they may be purchased by contacting your local Motorola sales office.
Notes
Although not shown in the above list, each Motorola
Computer Group manual publication number is
suffixed with characters which represent the revision
level of the document, such as "/ xx 2" (the second
revision of a manual); a supplement bears the same
number as a manual but has a suffix such as "/
xx 2A1"
(the first supplement to the second edition of the
manual).
You can obtain connector interconnect signal information, parts lists, and
schematics for the MVME162FX free of charge by contacting your local
Motorola sales office. They will relay the information.
Document Title Motorola
Publication Number
MVME162FX Embedded Controller Installation and Use V162FXA/IH
MVME162Bug Diagnostics Manual V162DIAA/UM
Debugging Package for Motorola 68K CISC CPUs User's
Manual
68KBUG1/D and
68KBUG2/D
Single Board Computers SCSI Software User's Manual SBCSCSI/D
MVME712M Transition Module and P2 Adapter Board User's
Manual
MVME712M/D
MVME712-12, MVME712-13, MVME712A, MVME712AM, and
MVME712B Transition Modules and LCP2 Adapter Board
User's Manual
MVME712A/D
SIMM09 Serial Interface Module Installation Guide SIMM09A/IH
M68040 Microprocessors User's Manual M68040UM
M68000 Family Reference Manual M68000FR

The following publications are also available from the sources indicated.
Versatile Backplane Bus: VMEbus , ANSI/IEEE Std 1014-1987, The Institute of
Electrical and Electronics Engineers, Inc., 345 East 47th Street, New York, NY 10017
(VMEbus Specification). (This is also
Microprocessor System Bus for 1 to 4 Byte Data ,
IEC 821 BUS, Bureau Central de la Commission Electrotechnique Internationale; 3,
rue de VarembŽ, Geneva, Switzerland.)
ANSI Small Computer System Interface-2 (SCSI-2) , Draft Document X3.131-198X,
Revision 10c; Global Engineering Documents, P.O. Box 19539, Irvine, CA 92714.
IndustryPack Logic Interface Specification, Revision 1.0 ; GreenSpring Computers, Inc.,
1204 O'Brien Drive, Menlo Park, CA 94025.
Z85230 Serial Communications Controller data sheet ; Zilog, Inc., 210 Hacienda Ave.,
Campbell, California 95008-6609.
82596CA Local Area Network Coprocessor data sheet , Order Number 290218; and
82596 User's Manual, Order Number 296443-001; Intel Corporation, Literature
Sales, P.O. Box 58130, Santa Clara, CA 95052-8130.
NCR 53C710 SCSI I/O Processor, data manual document #SCSIP-53C710 ; NCR
Corporation, Microelectronics Products Division, Colorado Springs, CO.
MK48T08(B) Timekeeper TM and 8Kx8 Zeropower TM RAM data sheet in Static RAMs
Databook
, Order Code DBSRAM71; SGS-THOMPSON Microelectronics Group;
North & South American Marketing Headquarters, 1000 East Bell Road, Phoenix,
AZ 85022-2699.
28F008SA Flash Memory Data Sheet , Order Number 290435-001; Intel Literature
Sales, P.O. Box 7641, Mt. Prospect, IL 60056-7641.
Motorola
¨
and the Motorola symbol are registered trademarks of Motorola,
Inc.
Delta Series
TM
, MC68040, VMEexec
TM
,VMEmodule
TM
, and VMEsystem
TM
are
trademarks of Motorola, Inc.
IndustryPack
TM
and IP
TM
are trademarks of GreenSpring Computers, Inc.
PowerPC
TM
is a trademark of IBM Corp, and is used by Motorola, Inc. under
license from IBM Corp.
Timekeeper
TM
and Zeropower
TM
are trademarks of Thompson Components.
All other products mentioned in this document are trademarks or registered
trademarks of their respective holders.

©
Copyright Motorola, Inc. 1996
All Rights Reserved
Printed in the United States of America
August 1996

xi
Contents
Chapter 1 Board Description and Memory Maps
Introduction ..........................................................................................................1-1
Overview.........................................................................................................1-1
Requirements..................................................................................................1-3
Features ...........................................................................................................1-3
Block Diagram ......................................................................................................1-5
Functional Description ........................................................................................1-5
No-VMEbus-Interface Option......................................................................1-6
VMEbus Interface and VMEchip2...............................................................1-7
Memory Maps.......................................................................................................1-8
Local Bus Memory Map................................................................................1-8
Normal Address Range......................................................................... 1-8
Detailed I/O Memory Maps............................................................... 1-13
BBRAM/TOD Clock Memory Map .................................................. 1-31
Interrupt Acknowledge Map.............................................................. 1-37
VMEbus Memory Map ...............................................................................1-37
VMEbus Accesses to the Local Bus ................................................... 1-37
VMEbus Short I/O Memory Map ..................................................... 1-37
Software Support Considerations....................................................................1-38
Interrupts ......................................................................................................1-38
Cache Coherency .........................................................................................1-38
Sources of Local BERR*...............................................................................1-39
Local Bus Time-out .............................................................................. 1-39
VMEbus Access Time-out................................................................... 1-39
VMEbus BERR* ....................................................................................1-39
Local DRAM Parity Error ................................................................... 1-40
VMEchip2.............................................................................................. 1-40
Bus Error Processing............................................................................ 1-40
Description of Error Conditions on the MVME162FX ...........................1-41
MPU Parity Error ................................................................................. 1-41
MPU Off-board Error .......................................................................... 1-41
MPU TEA - Cause Unidentified ........................................................ 1-42
MPU Local Bus Time-out.................................................................... 1-42
DMAC VMEbus Error......................................................................... 1-43

xii
DMAC Parity Error ............................................................................. 1-43
DMAC Off-board Error....................................................................... 1-44
DMAC LTO Error ................................................................................ 1-44
DMAC TEA - Cause Unidentified..................................................... 1-45
LAN Parity Error ................................................................................. 1-45
LAN Off-board Error........................................................................... 1-46
LAN LTO Error .................................................................................... 1-46
SCSI Parity Error.................................................................................. 1-46
SCSI Off-board Error........................................................................... 1-47
SCSI LTO Error..................................................................................... 1-47
Example of the Proper Use of Bus Timers ............................................... 1-48
MVME162FX MC68040 Indivisible Cycles.............................................. 1-49
Illegal Access to IP Modules from External VMEbus Masters.............. 1-50
Chapter 2 VMEchip2
Introduction .......................................................................................................... 2-1
Summary of Major Features......................................................................... 2-1
Functional Blocks ................................................................................................. 2-4
Local Bus to VMEbus Interface ................................................................... 2-4
Local Bus to VMEbus Requester.......................................................... 2-8
VMEbus to Local Bus Interface ................................................................... 2-9
Local Bus to VMEbus DMA Controller.................................................... 2-11
No Address Increment DMA Transfers ........................................... 2-13
DMAC VMEbus Requester ................................................................ 2-14
Tick and Watchdog Timers......................................................................... 2-15
Prescaler ................................................................................................ 2-15
Tick Timers ........................................................................................... 2-16
Watchdog Timer .................................................................................. 2-17
VMEbus Interrupter.................................................................................... 2-17
VMEbus System Controller........................................................................ 2-18
Arbiter ................................................................................................... 2-18
IACK Daisy-Chain Driver .................................................................. 2-19
Bus Timer .............................................................................................. 2-19
Reset Driver .......................................................................................... 2-19
Local Bus Interrupter and Interrupt Handler ......................................... 2-20
Global Control and Status Registers......................................................... 2-22
LCSR Programming Model .............................................................................. 2-22
Programming the VMEbus Slave Map Decoders................................... 2-28

xiii
VMEbus Slave Ending Address Register 1 ...................................... 2-31
VMEbus Slave Starting Address Register 1 ..................................... 2-31
VMEbus Slave Ending Address Register 2 ...................................... 2-31
VMEbus Slave Starting Address Register 2 ..................................... 2-32
VMEbus Slave Address Translation Address Offset Register 1.... 2-32
VMEbus Slave Address Translation Select Register 1.................... 2-33
VMEbus Slave Address Translation Address Offset Register 2.... 2-34
VMEbus Slave Address Translation Select Register 2.................... 2-34
VMEbus Slave Write Post and Snoop Control Register 2 .............. 2-35
VMEbus Slave Address Modifier Select Register 2......................... 2-36
VMEbus Slave Write Post and Snoop Control Register 1 .............. 2-37
VMEbus Slave Address Modifier Select Register 1......................... 2-38
Programming the Local Bus to VMEbus Map Decoders.......................2-39
Local Bus Slave (VMEbus Master) Ending Address Register 1 .... 2-42
Local Bus Slave (VMEbus Master) Starting Address Register 1 ... 2-42
Local Bus Slave (VMEbus Master) Ending Address Register 2 .... 2-42
Local Bus Slave (VMEbus Master) Starting Address Register 2 ... 2-43
Local Bus Slave (VMEbus Master) Ending Address Register 3 .... 2-43
Local Bus Slave (VMEbus Master) Starting Address Register 3 ... 2-43
Local Bus Slave (VMEbus Master) Ending Address Register 4 .... 2-44
Local Bus Slave (VMEbus Master) Starting Address Register 4 ... 2-44
Local Bus Slave (VMEbus Master) Address Translation
Address Register 4 .............................................................................. 2-44
Local Bus Slave (VMEbus Master) Address Translation
Select Register 4 ...................................................................................2-45
Local Bus Slave (VMEbus Master) Attribute Register 4................. 2-45
Local Bus Slave (VMEbus Master) Attribute Register 3................. 2-46
Local Bus Slave (VMEbus Master) Attribute Register 2................. 2-46
Local Bus Slave (VMEbus Master) Attribute Register 1................. 2-47
VMEbus Slave GCSR Group Address Register ............................... 2-48
VMEbus Slave GCSR Board Address Register ................................ 2-48
Local Bus to VMEbus Enable Control Register ............................... 2-49
Local Bus to VMEbus I/O Control Register..................................... 2-50
ROM Control Register......................................................................... 2-51
Programming the VMEchip2 DMA Controller .......................................2-52
DMAC Registers................................................................................... 2-53
PROM Decoder, SRAM and DMA Control Register ...................... 2-54
Local Bus to VMEbus Requester Control Register.......................... 2-55

xiv
DMAC Control Register 1 (bits 0-7) .................................................. 2-56
DMAC Control Register 2 (bits 8-15) ................................................ 2-57
DMAC Control Register 2 (bits 0-7) .................................................. 2-59
DMAC Local Bus Address Counter.................................................. 2-60
DMAC VMEbus Address Counter.................................................... 2-61
DMAC Byte Counter ........................................................................... 2-61
Table Address Counter ....................................................................... 2-62
VMEbus Interrupter Control Register .............................................. 2-62
VMEbus Interrupter Vector Register ................................................ 2-63
MPU Status and DMA Interrupt Count Register............................ 2-64
DMAC Status Register ........................................................................ 2-65
Programming the Tick and Watchdog Timers ........................................ 2-66
VMEbus Arbiter Time-out Control Register.................................... 2-66
DMAC Ton/Toff Timers and VMEbus Global Time-out
Control Register .................................................................................. 2-67
VME Access, Local Bus, and Watchdog Time-out
Control Register .................................................................................. 2-68
Prescaler Control Register .................................................................. 2-69
Tick Timer 1 Compare Register ......................................................... 2-70
Tick Tim
er
1 Counter ........................................................................... 2-70
Tick Timer 2 Compare Register ......................................................... 2-71
Tick Timer 2 Counter............................................................................ 2-71
Tick Timer 2 Compare Register ......................................................... 2-72
Tick Timer 2 Counter........................................................................... 2-72
Board Control Register........................................................................ 2-73
Watchdog Timer Control Register .................................................... 2-74
Tick Timer 2 Control Register............................................................ 2-75
Tick Timer 1 Control Register............................................................ 2-76
Prescaler Counter................................................................................. 2-76
Programming the Local Bus Interrupter.................................................. 2-77
Local Bus Interrupter Status Register (bits 24-31)........................... 2-80
Local Bus Interrupter Status Register (bits 16-23)........................... 2-81
Local Bus Interrupter Status Register (bits 8-15)............................. 2-82
Local Bus Interrupter Status Register (bits 0-7)............................... 2-83
Local Bus Interrupter Enable Register (bits 24-31).......................... 2-84
Local Bus Interrupter Enable Register (bits 16-23).......................... 2-85
Local Bus Interrupter Enable Register (bits 8-15)............................ 2-86
Local Bus Interrupter Enable Register (bits 0-7).............................. 2-87

xv
Software Interrupt Set Register (bits 8-15)........................................ 2-88
Interrupt Clear Register (bits 24-31) .................................................. 2-88
Interrupt Clear Register (bits 16-23) .................................................. 2-89
Interrupt Clear Register (bits 8-15) .................................................... 2-90
Interrupt Level Register 1 (bits 24-31)............................................... 2-90
Interrupt Level Register 1 (bits 16-23)............................................... 2-91
Interrupt Level Register 1 (bits 8-15)................................................. 2-91
Interrupt Level Register 1 (bits 0-7)................................................... 2-92
Interrupt Level Register 2 (bits 24-31)............................................... 2-92
Interrupt Level Register 2 (bits 16-23)............................................... 2-93
Interrupt Level Register 2 (bits 8-15)................................................. 2-93
Interrupt Level Register 2 (bits 0-7)................................................... 2-94
Interrupt Level Register 3 (bits 24-31)............................................... 2-94
Interrupt Level Register 3 (bits 16-23)............................................... 2-95
Interrupt Level Register 3 (bits 8-15)................................................. 2-95
Interrupt Level Register 3 (bits 0-7)................................................... 2-96
Interrupt Level Register 4 (bits 24-31)............................................... 2-96
Interrupt Level Register 4 (bits 16-23)............................................... 2-97
Interrupt Level Register 4 (bits 8-15)................................................. 2-97
Interrupt Level Register 4 (bits 0-7)................................................... 2-98
Vector Base Register ............................................................................ 2-98
I/O Control Register 1......................................................................... 2-99
I/O Control Register 2....................................................................... 2-100
I/O Control Register 3 .......................................................................2-100
Miscellaneous Control Register ....................................................... 2-100
GCSR Programming Model............................................................................2-103
Programming the GCSR ...........................................................................2-105
VMEchip2 Revision Register............................................................ 2-107
VMEchip2 ID Register....................................................................... 2-107
VMEchip2 LM/SIG Register ............................................................ 2-107
VMEchip2 Board Status/Control Register..................................... 2-109
General Purpose Register 0............................................................... 2-110
General Purpose Register 1............................................................... 2-110
General Purpose Register 2............................................................... 2-111
General Purpose Register 3............................................................... 2-111
General Purpose Register 4............................................................... 2-112
General Purpose Register 5............................................................... 2-112

xvi
Chapter 3 MC2 Chip
Introduction .......................................................................................................... 3-1
Summary of Major Features......................................................................... 3-1
Functional Description........................................................................................ 3-2
MC2 chip Initialization................................................................................. 3-2
Flash and EPROM Interface......................................................................... 3-2
BBRAM Interface........................................................................................... 3-3
82596CA LAN Interface................................................................................ 3-3
MPU Port and MPU Channel Attention............................................. 3-3
MC68040-Bus Master Support for 82596CA ...................................... 3-4
LANC Bus Error..................................................................................... 3-5
LANC Interrupt ..................................................................................... 3-5
53C710 SCSI Controller Interface................................................................ 3-5
SRAM Memory Controller........................................................................... 3-6
DRAM Memory Controller.......................................................................... 3-6
Z85230 SCC Interface.................................................................................... 3-7
Tick Timers ..................................................................................................... 3-8
Watchdog Timer............................................................................................. 3-8
Local Bus Timer ............................................................................................. 3-9
Memory Map of the MC2 chip Registers ......................................................... 3-9
Programming Model ......................................................................................... 3-11
MC2 chip ID Register.................................................................................. 3-11
MC2 chip Revision Register....................................................................... 3-12
General Control Register............................................................................ 3-12
Interrupt Vector Base Register................................................................... 3-14
Programming the Tick Timers ................................................................... 3-16
Tick Timer 1 and 2 Compare and Counter Registers ..................... 3-16
LSB Prescaler Count Register............................................................. 3-18
Prescaler Clock Adjust Register......................................................... 3-18
Tick Timer 1 and 2 Control Registers................................................ 3-19
Tick Timer Interrupt Control Registers ............................................ 3-21
DRAM Parity Error Interrupt Control Register...................................... 3-23
SCC Interrupt Control Register................................................................. 3-24
Tick Timer 3 and 4 Control Registers........................................................ 3-25
Tick Timer 4 Control Register............................................................ 3-25
Tick Timer 3 Control Register............................................................ 3-25
DRAM and SRAM Memory Controller Registers .................................. 3-26
DRAM Space Base Address Register ................................................ 3-26

xvii
SRAM Space Base Address Register ................................................. 3-27
DRAM Space Size Register ................................................................. 3-28
DRAM/SRAM Options Register ....................................................... 3-29
SRAM Space Size Register .................................................................. 3-31
LANC Error Status Register.......................................................................3-32
82596CA LANC Interrupt Control Register.............................................3-33
LANC Bus Error Interrupt Control Register ...........................................3-34
SCSI Error Status Register ..........................................................................3-35
General Purpose Inputs Register...............................................................3-36
MVME162FX Version Register...................................................................3-37
SCSI Interrupt Control Register.................................................................3-38
Tick Timer 3 and 4 Compare and Counter Registers..............................3-39
Bus Clock Register.......................................................................................3-40
EPROM Access Time Control Register.....................................................3-41
Flash Parameter Register............................................................................3-42
ABORT Switch Interrupt Control Register ..............................................3-43
RESET Switch Control Register.................................................................3-44
Watchdog Timer Control Register.............................................................3-45
Access and Watchdog Time Base Select Register ....................................3-46
DRAM Control Register..............................................................................3-47
MPU Status Register....................................................................................3-49
32-bit Prescaler Count Register..................................................................3-50
Chapter 4 IP2 Chip
Introduction ..........................................................................................................4-1
Summary of Major Features.........................................................................4-1
Functional Description ........................................................................................4-2
General Description.......................................................................................4-2
Cache Coherency ...........................................................................................4-2
Local Bus to IndustryPack DMA Controllers ............................................4-3
Clocking Environments and Performance.................................................4-5
Pacer Clock .....................................................................................................4-6
Error Reporting ..............................................................................................4-7
Error Reporting as a Local Bus Slave .................................................. 4-7
Error Reporting as a Local Bus Master ............................................... 4-7
IndustryPack Error Reporting.............................................................. 4-7
Interrupts ........................................................................................................4-8
Overall Memory Map ..........................................................................................4-9

xviii
Programming Model ......................................................................................... 4-10
Chip ID Register .......................................................................................... 4-17
Chip Revision Register ............................................................................... 4-17
Vector Base Register .................................................................................... 4-18
IP_a, IP_b, IP_c, IP_d Memory Base Address Registers ........................ 4-19
IP_a or Double Size IP_ab Memory Base Address Registers ........ 4-20
IP_b Memory Base Address Registers .............................................. 4-20
IP_c or Double Size IP_cd Memory Base Address Registers......... 4-21
IP_d Memory Base Address Registers.............................................. 4-21
IP_a, IP_b, IP_c, IP_d Memory Size Registers......................................... 4-22
IP_a, IP_b, IP_c, and IP_d; IRQ0 and IRQ1 Interrupt
Control Registers ........................................................................................ 4-23
IP_a, IP_b, IP_c, and IP_d; General Control Registers........................... 4-25
IP Clock Register.......................................................................................... 4-29
DMA Arbitration Control Register ........................................................... 4-30
IP RESET Register........................................................................................ 4-31
Programming the DMA Controllers......................................................... 4-31
DMA Enable Function......................................................................... 4-33
DMA Control and Status Register Set Definition ........................... 4-34
Programming the Pacer Clock ........................................................... 4-44
Local Bus to IndustryPack Addressing........................................................... 4-47
8-Bit Memory Space .................................................................................... 4-47
16-Bit Memory Space .................................................................................. 4-48
32-Bit Memory Space .................................................................................. 4-49
IP_a I/O Space............................................................................................. 4-50
IP_ab I/O Space........................................................................................... 4-51
IP_a ID Space ............................................................................................... 4-52
IP to Local Bus Data Routing ........................................................................... 4-53
Memory Space Accesses ............................................................................. 4-53
I/O and ID Space Accesses ........................................................................ 4-55
Chapter 5 Serial Port Connections
Introduction .......................................................................................................... 5-1
Appendix A Using Interrupts on the MVME162FX
Introduction .........................................................................................................A-1
VMEchip2 Tick Timer 1 Periodic Interrupt Example.....................................A-1

Figures
xix
Figure 1-1. MVME162FX Block Diagram.........................................................1-5
Figure 2-1. VMEchip2 Block Diagram..............................................................2-5
Figure 5-1. MVME162FX Port 1 EIA-232 DCE, MVME712M
Port 2 DTE ............................................................................................................5-3
Figure 5-2. MVME162FX Port 1 EIA-232 DCE, MVME712M
Port 2 DCE............................................................................................................5-4
Figure 5-3. MVME162FX Port 2 EIA-232 DTE, MVME712M
Port 4 DTE ............................................................................................................5-5
Figure 5-4. MVME162FX Port 2 EIA-232 DCE, MVME712M
Port 4 DCE............................................................................................................5-6
Figure 5-5. MVME162FX Port 2 EIA-232 DTE, MVME712M
Port 4 DCE............................................................................................................5-7
Figure 5-6. MVME162FX Port 2 EIA-232 DCE, MVME712M
Port 4 DTE ............................................................................................................5-8
Figure 5-7. MVME162FX Port 2 EIA-530 DTE.................................................5-9
Figure 5-8. MVME162FX Port 2 EIA-530 DCE ..............................................5-10
Figure 5-9. MVME162FX Port 1 EIA-232 DCE,
MVME712A/AM/-12/-13 Port 2 DTE .......................................................... 5-11
Figure 5-10. MVME162FX Port 1 EIA-232 DCE, MVME712AM/-13
Port 2 as Modem Port .......................................................................................5-12
Figure 5-11. MVME162FX Port 2 EIA-232 DTE,
MVME712A/AM/-12/-13 Port 4DTE ...........................................................5-13
Figure 5-12. MVME162FX Port 2 EIA-232 DCE,
MVME712A/AM/-12/-13 Port 4DTE ...........................................................5-14
Figure 5-13. MVME162FX EIA-485/EIA-422 Connections ..........................5-15

xx