Murata Type1XK User manual

Specification Number: SP-CJ1XK-L
< Specification may be changed by Murata without notice >
Murata Manufacturing Co., Ltd.
W-LAN+Bluetooth Combo Module Data Sheet
NXP IW416 Chipset
for 802.11a/b/g/n + Bluetooth 5.2
Design Name: Type1XK
P/N :LBEE5CJ1XK-687

Specification Number: SP-CJ1XK-L
P. 1/84
< Specification may be changed by Murata without notice >
Murata Manufacturing Co., Ltd.
Revision History
Revision
Code
Date
Description
Comments
-
2020.12.16
First Issue
A
2021.03.23
Top page
4.Block Diagram
9. Operating Conditions
11.2 High-speed UART specifications
12. DC/RF Characteristics
- Removed “ac”
- Updated
- Updated operating temperature.
- Added default baud rate information.
- Added 802.11n 40MHz in 2.4GHz.
- Added Tx power values.
B
2021.03.31
14. Reference Circuit
15. Tape and Reel Packing
- Added circuit for dedicated BT antenna.
- Added
C
2021.04.05
2. Key feature & 5.2 Bluetooth Qualification
7.1PinAssignments
7.2 Pin Descriptions
- Added a comment on supported Bluetooth functions
- Corrected pin number
- Corrected pin number
D
2021.04.14
14. Reference Circuit
- Corrected circuit for dedicated BT antenna
E
2021.05.19
2. Key Features
7.5 Pin States
14. Reference Circuit
12.8 DC/RF Characteristics for Bluetooth
12.9 DC/RF Characteristics for Bluetooth Low
Energy
- Added Weight
- Added Internal pull values
- Corrected circuit for Shard BT antenna
- Updated Output Power
- Updated Output Power
F
2021.06.10
12. DC/RF Characteristics
- Delete 802.11n 40MHz in 2.4GHz.
G
2021.07.30
5. Certification Information
9. Operating Conditions
14. Reference Circuit
- Added Certification Information
- Added DC current
- Removed dedicated BT antenna
H
2021.09.15
13. Land patterns
- Updated figure
I
2021.10.14
3. Ordering Information
7. Module Pin Descriptions
12. DC / RF Characteristics
14. Reference Circuit
- Added part number for MP
- Updated description of GPIOs and WCI IF
- Corrected values of WiFi Current consumption.
- Corrected typo
J
2021.11.19
11.1.2 High Speed Mode
15. Tape and Reel Packing
- Corrected the note on SDIO 2.0 mode.
- Corrected Dimensions of Tape
K
2021.11.25
6. Dimensions, Marking and Terminal
Configurations
- Corrected Dimensions
e1: 0.38 →0.375
e3: 0.48 →0.475
L
2021.12.14
7.2 Pin Descriptions
7.4 Pin States
9.1 Operating Conditions
9.2 External Sleep Clock Requirements
10. Power Sequence
14. Reference Circuit
- Added comments to pin 10
- Added SLP_CLK_IN, WCI-2_SIN and WCI-2_SOUT.
- Defined IO current and Peak current
- Added a comment
- Defined timing parameters
- Pull-down RF_CNTL2_N and updated descriptions.

Specification Number: SP-CJ1XK-L
P. 2/84
Murata Manufacturing Co., Ltd.
TABLE OF CONTENTS
1. Scope ..................................................................................................................................................... 4
2. Key Features.......................................................................................................................................... 4
3. Ordering Information .............................................................................................................................. 4
4. Block Diagram........................................................................................................................................ 4
5. Certification Information ......................................................................................................................... 5
5.1. Radio Certification........................................................................................................................... 5
5.2. Bluetooth Qualification..................................................................................................................... 5
6. Dimensions, Marking and Terminal Configurations ............................................................................... 6
7. Module Pin Descriptions ........................................................................................................................ 7
7.1. Pin Assignments.............................................................................................................................. 7
7.2. Pin Descriptions............................................................................................................................... 8
7.3. Configuration Pins......................................................................................................................... 10
7.4. Pin States .......................................................................................................................................11
8. Absolute Maximum Ratings.................................................................................................................. 13
9. Operating Conditions............................................................................................................................ 13
9.1. Operating conditions...................................................................................................................... 13
9.2. External Sleep Clock Requirements.............................................................................................. 13
9.3. Digital I/O Requirements ............................................................................................................... 13
10. Power Sequence................................................................................................................................ 14
10.1. Power On Sequence ................................................................................................................... 14
10.2. Power Off Sequence ................................................................................................................... 14
11. Interface Timing.................................................................................................................................. 15
11.1. SDIO Timing................................................................................................................................. 15
11.1.1. Default Speed Mode ............................................................................................................. 15
11.1.2. High Speed Mode ................................................................................................................. 15
11.1.3. SDR12,SDR25,SDR50 Modes(up to 100 MHz)(1.8V)......................................................... 16
11.1.4. DDR50 Mode(50MHz)(1.8V)................................................................................................. 17
11.2. UART Timing (Default Mode)....................................................................................................... 19
11.3. Bluetooth PCM Timing................................................................................................................. 19
11.3.1. Master mode ......................................................................................................................... 19
11.3.2. Slave mode ........................................................................................................................... 20
12. DC / RF Characteristics ..................................................................................................................... 21
12.1. DC/RF Characteristics for IEEE802.11b - 2.4GHz...................................................................... 21
12.1.1. High Rate Condition for IEEE802.11b –2.4GHz.................................................................. 21
12.1.2. Low Rate Condition for IEEE802.11b –2.4GHz................................................................... 22
12.2. DC/RF Characteristics for IEEE802.11g - 2.4GHz...................................................................... 23
12.2.1. High Rate Condition for IEEE802.11g –2.4GHz.................................................................. 23
12.2.2. Low Rate Condition for IEEE802.11g –2.4GHz................................................................... 24
12.3. DC/RF Characteristics for IEEE802.11n - 2.4GHz...................................................................... 25
12.3.1. High Rate Condition for IEEE802.11n 20MHz BW –2.4GHz .............................................. 25
12.3.2. Low Rate Condition for IEEE802.11n 20MHz BW –2.4GHz............................................... 26
12.4. DC/RF Characteristics for IEEE802.11a - 5GHz......................................................................... 27
12.4.1. High Rate Condition for IEEE802.11a –5GHz..................................................................... 27
12.4.2. Low Rate Condition for IEEE802.11a –5GHz...................................................................... 28
12.5. DC/RF Characteristics for IEEE802.11n(HT20) - 5GHz ............................................................. 29
12.5.1. High Rate Condition for IEEE802.11n(HT20) –5GHz.......................................................... 29
12.5.2. Low Rate Condition for IEEE802.11n(HT20) –5GHz .......................................................... 30
12.6. DC/RF Characteristics for IEEE802.11n(HT 40MHz) - 5GHz..................................................... 31
12.6.1. High Rate Condition for IEEE802.11n(HT40) –5GHz.......................................................... 31
12.6.2. Low Rate Condition for IEEE802.11n(HT40) –5GHz .......................................................... 32
12.7. DC/RF Characteristics for Bluetooth........................................................................................... 33
12.7.1. Basic Data Rate Condition.................................................................................................... 33
12.7.2. Enhanced Data Rate Condition............................................................................................ 34
12.8. DC/RF Characteristics for Bluetooth Low Energy....................................................................... 35
12.8.1. 1Mbps PHY Condition........................................................................................................... 35
12.8.2. 2Mbps PHY Condition........................................................................................................... 36
13. Land Patterns..................................................................................................................................... 37

Specification Number: SP-CJ1XK-L
P. 3/84
Murata Manufacturing Co., Ltd.
14. Reference Circuit................................................................................................................................ 38
15. Tape and Reel Packing ...................................................................................................................... 40
16. Notice ................................................................................................................................................. 43
16.1. Storage Conditions:..................................................................................................................... 43
16.2. Handling Conditions: ................................................................................................................... 43
16.3. Standard PCB Design (Land Pattern and Dimensions):............................................................. 43
16.4. Notice for Chip Placer:................................................................................................................. 43
16.5. Soldering Conditions: .................................................................................................................. 44
16.6. Cleaning:...................................................................................................................................... 44
16.7. Operational Environment Conditions: ......................................................................................... 44
17. Preconditions to Use Our Products.................................................................................................... 45
APPENDIX ............................................................................................................................................... 46
Please be aware that an important notice concerning availability, standard warranty and use in critical
applications of Murata products and disclaimers thereto appears at the end of this specification sheet.

Specification Number: SP-CJ1XK-L
P. 4/84
Murata Manufacturing Co., Ltd.
1. Scope
This specification is applied to the IEEE802.11a/b/g/n WLAN + Bluetooth®5.2 combo module.
2. Key Features
- NXP IW416 inside
- Compliant with IEEE802.11a/b/g/n, SISO
- Compliant with Bluetooth®specification v5.2 (See PIC for supported Bluetooth functions on Bluetooth SIG site)
- Supports standard SDIO3.0 interface for WLAN
- UART interfaces support for Bluetooth is Host Controller Interface (HCI)
- Surface mount type 9.1 x 8.3 mm(Typical), H = 1.3 mm(Max.)
- Weight :268.8 mg
- MSL : 3
- RoHS compliant
3. Ordering Information
Ordering Part Number
Description
LBEE5CJ1XK-687
MP order
LBEE5CJ1XK-SMP
In case of sample order
LBEE5CJ1XK-EVB
EVB
“LBEE5CJ1XK ” is used in certification test report.
4. Block Diagram
IW416
VLDO1.8V
VDD2.2V
VDD1.1V
PMIC
SPDT
SPDT
LPF
WLAN
5G Tx/Rx
WLAN
2.4G Tx/Rx
Bluetooth
Tx/Rx
DPX
PMIC_EN
VBAT
UART
SDIO
PCM
Sleep Clock
(Option)
Type1XK
26MHz
VIO
PM
823

Specification Number: SP-CJ1XK-L
P. 5/84
Murata Manufacturing Co., Ltd.
5. Certification Information
5.1. Radio Certification
USA
FCC ID: VPYLB1XK
Country Code: US
Tx Power limit file
free RTOS：wlan_txpwrlimit_cfg_US.c
Linux：txpwrlimit_cfg_US.bin
Canada
IC: 772C-LB1XK
Country Code: CA
Tx Power limit file
free RTOS：wlan_txpwrlimit_cfg_CA.c
Linux：txpwrlimit_cfg_CA.bin
Europe
EN300328/301893, EN300440 conducted test report is prepared.
Country Code: DE
Tx Power limit file
free RTOS：wlan_txpwrlimit_cfg_EU.c
Linux：txpwrlimit_cfg_EU.bin
Japan
Japanese type certification is prepared.
001-P01624
Country Code: JP
Tx Power limit file
free RTOS：wlan_txpwrlimit_cfg_JP.c
Linux：txpwrlimit_cfg_JP.bin
The each country code are defined by Murata’s db.txt file.
Please ask your contact person from Murata.
5.2. Bluetooth Qualification
QDID: 169159
*Set Bluetooth Tx Power to Class1 by using “bt_power_config_1.sh”.
**See PICS for supported Bluetooth functions on Bluetooth SIG site

Specification Number: SP-CJ1XK-L
P. 6/84
Murata Manufacturing Co., Ltd.
6. Dimensions, Marking and Terminal Configurations
<TOP VIEW> <BOTTOM VIEW>
<SIDE VIEW>
Marking
Meaning
A
Module Type
B
Inspection Number
C
Serial Number
D
Pin 1 Marking
E
2D code
F
Murata Logo
(unit : mm)
Mark
Dimensions
Mark
Dimensions
Mark
Dimensions
Mark
Dimensions
L
9.1 ± 0.2
W
8.3 ± 0.2
T
1.3 max.
a1
0.25 ± 0.1
a2
0.5 ± 0.1
a3
0.8 ± 0.2
b1
0.3 ± 0.2
b2
0.3 ± 0.2
b3
0.3 ± 0.2
b4
0.3 ± 0.2
c1
0.25 ± 0.1
c2
0.5 ± 0.1
c3
0.8 ± 0.1
e1
0.375 ± 0.1
e2
0.25 ± 0.1
e3
0.475 ± 0.1
e4
0.25 ± 0.1
e5
0.75 ± 0.1
e6
0.5 ± 0.1
e7
0.35 ± 0.1
e8
0.5 ± 0.1
m1
0.5 ± 0.2
m2
0.5 ± 0.2
T1
0.045 typ.
* T dimension does not include height of solder bumps.
Structure
A
F
C
E
B
D
SMD
Diplexer
Switch
PMIC
IW416
Resin
Mold
Shield
Solder Bump
PWB
Substrate
T
T1
LBEE5CJ1XK
SS1234567
XXXXXXXXX

Specification Number: SP-CJ1XK-L
P. 7/84
Murata Manufacturing Co., Ltd.
7. Module Pin Descriptions
7.1. Pin Assignments <TOP VIEW>
No.
Terminal Name
No.
Terminal Name
No.
Terminal Name
1
GND
20
GPIO(3)
TDO
39
GND
2
VIO
21
GND
40
GND
3
SD_D2
22
VBAT
41
GND
4
SD_CLK
23
VBAT
42
RF_CNTL2_N
5
SD_D0
24
GND
43
RF_CNTL3_P
6
SD_CMD
25
GND
44
GND
7
GPIO(9)
UART_RXD
26
GND
45
BT_ANT
SHARED
8
GPIO(6)
27
GND
46
GND
9
GPIO(7)
28
GND
47
BT_ANT
DEDICATED
10
NC
29
GND
48
GND
11
GPIO(4)
30
GND
49
GND
12
GPIO(1)
31
PMIC_EN
50
GND
13
GPIO(15)
TMS
32
WCI_SOUT
51
GPIO(11)
UART_RTS
14
GPIO(5)
33
WCI_SIN
52
GPIO(0)
15
GPIO(8)
UART_CTS
34
GPIO(12)
53
GPIO(13)
16
GND
35
RF_CNTL1_P
54
GPIO(10)
UART_TXD
17
GPIO(14)
TCK
36
RF_CNTL0_N
55
SD_D3
18
GPIO(2)
TDI
37
GND
56
SD_D1
19
SLP_CLK_IN
38
RF_ANT
57-81
GND

Specification Number: SP-CJ1XK-L
P. 8/84
Murata Manufacturing Co., Ltd.
7.2. Pin Descriptions
No.
Pin name
Type
Connection to
Description
IC pin name
1
GND
-
-
Ground
2
VIO
P
VIO
VIO_RF
VIO_SD
Power supply
3
SD_D2
I
SD_DAT[2]
SDIO 4-bit mode: Data line Bit[2] or read wait (optional)
SDIO 1-bit mode: Read wait (optional)
4
SD_CLK
I
SD_CLK
SDIO Clock input
5
SD_D0
I
SD_DAT[0]
SDIO 4-bit mode: Data line Bit[0]
SDIO 1-bit mode: Data line
6
SD_CMD
I/O
SD_CMD
SDIO 4-bit mode: Command/response (input/output)
SDIO 1-bit mode: Command line
7
GPIO(9)
UART_RXD
I/O
GPIO[9]
GPIO mode: GPIO[9] (input/output)
UART mode: UART_SIN (input)
8
GPIO(6)
I/O
GPIO[6]
GPIO mode: GPIO[6] (input/output)
PCM mode: PCM_CLK - PCM data clock (input if slave, output if master).
I2S mode: I2S_BCLK - I2S bit clock (input if slave, output if master).
PTA mode: EXT_PRI - External radio priority signal (input).
9
GPIO(7)
I/O
GPIO[7]
GPIO mode: GPIO[7] (input/output)
PCM mode: PCM_SYNC - PCM frame sync (input if slave, output if master).
I2S mode: I2S_LRCLK - I2S left-right clock (input if slave, output if master).
PTA mode: EXT_REQ - Request from the external radio (input).
10
NC
-
-
NC *Floating terminal pad. Recommended grounding for mechanical strength.
11
GPIO(4)
I/O
GPIO[4]
GPIO mode: GPIO[4] (input/output)
PCM mode: PCM_DOUT[3] - PCM transmit signal (output).
I2S mode: I2S_DOUT/I2S_DIN (depending on the configuration. If GPIO[5] is
configured as I2S_DIN, then GPIO[4] is set
as I2S_DOUT, and vice-verse).
PTA mode: EXT_FREQ - External radio frequency signal (input).
Out-of-band wake-up mode: IW416 Bluetooth to host wake-up signal (output)[4]
12
GPIO(1)
I/O
GPIO[1]
GPIO mode: GPIO[1] (input/output)
This pin is used as a configuration pin: CON[9] (input).
PTA mode: EXT_STATE - External radio state signal (input).
Out-of-band wake-up mode: IW416 Wi-Fi to host wake-up signal (output)
Do not drive this signal during boot-up
13
GPIO(15)
TMS
I/O
GPIO[15]
GPIO mode: GPIO[15] (input/output)
JTAG mode: JTAG_TMS - JTAG test mode select (input).
Reset recovery mode: Independent software reset for Bluetooth subsystem (input)
14
GPIO(5)
I/O
GPIO[5]
GPIO mode: GPIO[5] (input/output)
PCM mode: PCM_DIN[2] - PCM receive signal (input).
I2S mode: I2S_DOUT/I2S_DIN - I2S transmit/receive signal (output/input)
(depending on the configuration). PTA mode: EXT_GNT - External radio grant
signal (output).
15
GPIO(8)
UART_CTS
I/O
GPIO[8]
GPIO mode: GPIO[8] (input/output)
This pin is used as a configuration pin: CON[7] (input)
UART mode: UART_CTSn - UART clear-to-send input signal (input, active low).
Do not drive this signal during boot-up
16
GND
-
-
Ground
17
GPIO(14)
TCK
I/O
GPIO[14]
GPIO mode: GPIO[14] (input/output)
JTAG mode: JTAG_TCK - JTAG test clock (input).
Reset recovery mode: Independent software reset for Wi-Fi subsystem (input)
18
GPIO(2)
TDI
I/O
GPIO[2]
GPIO mode: GPIO[2] (input/output)
Power management mode: DVSC[0], Digital voltage scaling control (output)
JTAG mode: JTAG_TDI, JTAG test data (input).
19
SLP_CLK_IN
I
SLP_CLK_IN
Sleep Clock Input (optional)
Used for lower power operation in sleep mode.
• An external sleep clock of 32.768 kHz can be used for lowest current consumption
in sleep mode.
• An external sleep clock is required if automatic reference clock frequency
detection is used.
• If no external sleep clock is used, leave this pin floating (DNC).
20
GPIO(3)
TDO
I/O
GPIO[3]
GPIO mode: GPIO[3] (input/output)
Power management mode: DVSC[1], Digital voltage scaling control (output)
JTAG mode: JTAG_TDO, JTAG test data (output).
PCM mode: PCM_MCLK (output) - PCM clock signal (output, optional).
I2S mode: I2S_CCLK - I2S clock (output, optional).
21
GND
-
-
Ground
22
VBAT
P
PVIN(PMIC)
Power supply

Specification Number: SP-CJ1XK-L
P. 9/84
Murata Manufacturing Co., Ltd.
23
VBAT
P
PVIN(PMIC)
Power supply
24
GND
-
-
Ground
25
GND
-
-
Ground
26
GND
-
-
Ground
27
GND
-
-
Ground
28
GND
-
-
Ground
29
GND
-
-
Ground
30
GND
-
-
Ground
31
PMIC_EN
I
EN(PMIC)
Enable build-in PMIC.
Logic high enables internal regulators and internal hardware reset is de-asserted.
Logic low disables regulators and internal hardware reset is asserted.
Do not float this pin
32
WCI_SOUT
WCI-2_SOUT (output)
33
WCI_SIN
WCI-2_SIN (input)
34
GPIO(12)
I/O
GPIO[12]
GPIO mode: GPIO[12] (input/output)
UART mode: UART_DSRn - UART data-set-ready (input) (active low).
Host wake-up mode: Host to IW416 Bluetooth wake-up (input)
35
RF_CNTL1_P
O
RF_CNTL1_P
Reserved
Set to 1.
36
RF_CNTL0_N
O
RF_CNTL0_N
RF Control 0—RF Control Output Low (output)
This pin is used as a configuration pin: CON[0] (input).
37
GND
-
-
Ground
38
RF_ANT
39
GND
-
-
Ground
40
GND
-
-
Ground
41
GND
-
-
Ground
42
RF_CNTL2_N
O
RF_CNTL2_N
Reserved
Do not pull-up externally.
43
RF_CNTL3_P
O
RF_CNTL3_P
Reserved
44
GND
-
-
Ground
45
BT_ANT
SHARED
I
-
BT in(Feedback)
46
GND
-
-
Ground
47
BT_ANT
DEDICATED
O
-
BT output
48
GND
-
-
Ground
49
GND
-
-
Ground
50
GND
-
-
Ground
51
GPIO(11)
UART_RTS
I/O
GPIO[11]
GPIO mode: GPIO[11] (input/output)
This pin is used as a configuration pin: CON[8] (input)
UART mode: UART_RTSn - UART request-to-send (output) (active low).
Do not drive this signal during boot-up
52
GPIO(0)
I/O
GPIO[0]
GPIO mode: GPIO[1] (input/output)
This pin is used as a configuration pin: CON[9] (input).
Oscillator enable mode: XOSC_EN (output) (active high)
0 = disable external oscillator
1 = enable external oscillator
PTA mode: EXT_STATE - External radio state signal (input).
Out-of-band wake-up mode: IW416 Wi-Fi to host wake-up signal (output)
53
GPIO(13)
I/O
GPIO[13]
GPIO mode: GPIO[13] (input/output)
UART mode: UART_DTRn - UART data-terminal-ready (output).
Out-of-band wake-up mode: Host to IW416 Wi-Fi wake-up (input)
54
GPIO(10)
UART_TXD
I/O
GPIO[10]
GPIO mode: GPIO[10] (input/output)
UART mode: UART_SOUT - UART serial (output).
55
SD_D3
I
SD_DAT[3]
SDIO 4-bit mode: Data line Bit[3]
SDIO 1-bit mode: Reserved
56
SD_D1
I
SD_DAT[1]
SDIO 4-bit mode: Data line Bit[1]
SDIO 1-bit mode: Interrupt
57-81
GND
-
-
Ground
[1] Not all GPIO pins can be used for Host-to-SoC wake-up signals.
[2] The function can be swapped with GPIO[4] using a software command without affecting the hardware connection.
[3] The function can be swapped with GPIO[5] using a software command without affecting the hardware connection.
[4] If PCM and UART interfaces are used in application, use GPIO[0] as alternative for this wake-up signal

Specification Number: SP-CJ1XK-L
P. 10/84
Murata Manufacturing Co., Ltd.
7.3. Configuration Pins
Configuration Bits
Pin Name
Configuration Function
CON[1]
RF_CNTL2_N
Firmware Boot Options
No hardware impact. Software reads and boots
accordingly. See the table below.
Note: Boot code needs to use this host boot strap status
to decide the correct boot sequence.
CON[0]
RF_CNTL0_N
CON[1]
CON[0]
Wi-Fi
Bluetooth/LE
1
0
SDIO
UART
1
1
Reserved
Reserved

Specification Number: SP-CJ1XK-L
P. 11/84
Murata Manufacturing Co., Ltd.
7.4. Pin States
Pin states information for the tables below include:
◼After firmware is downloaded, the pads (GPIO, Serial interface, RF control) are programmed in
functional mode per the functionality of the pins.
◼For SDIO, once the command is received from the host, the pads are configured accordingly.
◼Pull-up and pull-down are only effective when the pad is in input mode.
◼The power-down state shown is the default configuration. Many pads have programmable
power-down values, which can be set by firmware.
I/O State Table
Pin Name
Supply
No Pad
Power State
Reset
State
HW State
PD State
PD Prog
Internal
PU/PD
Int’l Pull
Value[Ω]
GPIO0
VIO
tristate
output
output
drive low
yes
nominal PU
90K
GPIO1
VIO
tristate
input
input
tristate
yes
weak PU
800K
GPIO2
VIO
tristate
input
input
tristate
yes
weak PU
800K
GPIO3
VIO
tristate
input
input
tristate
yes
weak PU
800K
GPIO4
VIO
tristate
output
input
tristate
yes
nominal PU
90K
GPIO5
VIO
tristate
input
input
tristate
yes
weak PU
800K
GPIO6
VIO
tristate
input
input
tristate
yes
nominal PU
90K
GPIO7
VIO
tristate
input
input
tristate
yes
nominal PU
90K
GPIO8
VIO
tristate
input
input
drive low
yes
weak PU
800K
GPIO9
VIO
tristate
output
input
tristate
yes
nominal PU
90K
GPIO10
VIO
tristate
input
input
tristate
yes
nominal PU
90K
GPIO11
VIO
tristate
output
input
drive high
yes
weak PU
800K
GPIO12
VIO
tristate
input
input
tristate
yes
nominal PU
90K
GPIO13
VIO
tristate
input
input
drive high
yes
nominal PU
90K
SD_CLK
VIO_SD
tristate
input
Input
tristate
no
nominal PD
90K
SD_CMD
VIO_SD
tristate
input
Input
tristate
no
nominal PD
90K
SD_D0
VIO_SD
tristate
input
Input
tristate
no
nominal PD
90K
SD_D1
VIO_SD
tristate
input
Input
tristate
no
nominal PD
90K
SD_D2
VIO_SD
tristate
input
Input
tristate
no
nominal PD
90K
SD_D3
VIO_SD
tristate
input
Input
tristate
no
nominal PD
90K
RF_CNTL0_N
VIO_RF
tristate
input
output
drive low
yes
weak PU
800K
RF_CNTL1_P
VIO_RF
tristate
input
output
drive high
yes
weak PU
800K
RF_CNTL2_N
VIO_RF
tristate
input
output
drive low
yes
weak PU
800K
RF_CNTL3_P
VIO_RF
tristate
input
output
drive high
yes
weak PU
800K
SLP_CLK_IN
AVDD18
tristate
input
input
tristate
no
nominal PU
90K
WCI-2_SIN
AVDD18
tristate
input
input
tristate
no
weak PU
800K
WCI-2_OUT
AVDD18
tristate
output
output
tristate
no
weak PU
800K

Specification Number: SP-CJ1XK-L
P. 12/84
Murata Manufacturing Co., Ltd.
SDIO Pin Descriptions
No.
Pin Name
(i) SD 4-bit Mode
(ii) SD 1-bit Mode
4
SDIO_CLK
CLK
Clock
CLK
Clock
5
SDIO_D0
DATA0
Data line 0
DATA
Data line
45
SDIO_D1
DATA1
Data line 1
IRQ
Interrupt
3
SDIO_D2
DATA2
Data line 2
RW
Read wait (optional)
46
SDIO_D3
DATA3
Data line 3
NC
Reserved
6
SDIO_CMD
CMD
Command/response
CMD
Command line
(i) SD 4-bit Mode (ii) SD 1-bit Mode
SD Host
Type1XK
CLK
CMD
DATA[3:0]
SD Host
CLK
CMD
DATA
IRQ
Type1XK

Specification Number: SP-CJ1XK-L
P. 13/84
Murata Manufacturing Co., Ltd.
8. Absolute Maximum Ratings
Parameter
min.
max.
Unit
Storage Temperature
-40
85
deg.C
Supply Voltage
VBAT
-0.3
6.0
V
VIO
-
4.0
V
* Stresses in excess of the absolute ratings may cause permanent damage. Functional operation
is not implied under these conditions. Exposure to absolute ratings for extended periods of time
may adversely affect reliability. No damage assuming only one parameter is set at limit at a time
with all other parameters are set within operating condition.
9. Operating Conditions
9.1. Operating conditions
Parameter
min.
typ.
max.
unit
Operating Temperature
-40
25
+85
deg.C
Supply Voltage
VBAT
2.7
-
5.5
V
VIO
1.62
1.8
1.98
V
2.97
3.3
3.47
V
IO Current
VIO
-
0.1
0.5
mA
Peak Current*
VBAT
-
550
850
mA
Note) Operation beyond the recommended operating conditions is neither recommended nor
guaranteed.
*Peak current of VBAT (RF portion) is happen during DPD calibration when the firmware is
downloaded.
9.2. External Sleep Clock Requirements
Symbol
Parameter
Min
Typ
Max
Unit
CLK
Clock frequency range/accuracy
CMOS input clock signal type
±250 ppm (initial , aging, temperature)
-
32.768
-
kHz
PN
Phase Noise Requirement (@ 100kHz)
-
-125
-
dBc/Hz
Jc
Cycle jitter
-
1.5
-
ns(RMS)
SR
Slew rate limit (10-90%)
-
-
100
ns
DC
Duty cycle tolerance
20
-
80
%
Voltage input level = 1.8V
9.3. Digital I/O Requirements
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VIH
Input high voltage
-
0.7*VIO
-
VIO+0.4
V
VIL
Input low voltage
-
-0.4
-
0.3*VIO
V
VHYS
Input hysteresis
-
100
-
-
mV
VOH
Output high voltage
-
VIO-0.4
-
-
V
VOL
Output low voltage
-
-
-
0.4
V

Specification Number: SP-CJ1XK-L
P. 14/84
Murata Manufacturing Co., Ltd.
10. Power Sequence
10.1. Power On Sequence
VBAT and VIO must be good (90%) at the same time or before assert PMIC_EN (= 0 to 1).
Rump-up time of VIO must be <100ms
Symbol
Parameter
Min
Typ
Max
Unit
Ta
VBAT to VIO time
0
-
-
msec
Tb
VIO to PMIC_EN time
0
-
-
msec
10.2. Power Off Sequence
VBAT and VIO must be down at the same time or before de-assert PMIC_EN (= 1 to 0).
Rump-down time of VIO must be <100ms
Symbol
Parameter
Min
Typ
Max
Unit
Tc
PMIC_EN to VIO time
0
-
-
msec
Td
VIO to VBAT time
0
-
-
msec
VBAT
VIO
PMIC_EN
Ta
Tb
VBAT
VIO
PMIC_EN
Tc
Td

Specification Number: SP-CJ1XK-L
P. 15/84
Murata Manufacturing Co., Ltd.
11. Interface Timing
11.1. SDIO Timing
11.1.1. Default Speed Mode
SDIO Protocol Timing Diagram-Default Speed Mode
11.1.2. High Speed Mode
SDIO Protocol Timing Diagram-High Speed Mode[1] [2]
[1] For SDIO 2.0 running at 50 MHz clock frequency, VIO_SD must be 3.3V.
For SDIO 2.0 running at 25 MHz and 50 MHz clock frequency, VIO_SD must be 3.3V.

Specification Number: SP-CJ1XK-L
P. 16/84
Murata Manufacturing Co., Ltd.
11.1.3. SDR12,SDR25,SDR50 Modes(up to 100 MHz)(1.8V)
SDIO Protocol Timing Diagram-SDR12,SDR25,SDR50 Mode(up to 100MHz)(1.8V)

Specification Number: SP-CJ1XK-L
P. 17/84
Murata Manufacturing Co., Ltd.
11.1.4. DDR50 Mode(50MHz)(1.8V)
SDIO CMD Timing Diagram-DDR50 Mode (50MHz)
In DDR50 mode, DAT[3:0] lines are sampled on both edges of the clock (not applicable for CMD line).
SDIO DATA Timing Diagram-DDR50 Mode

Specification Number: SP-CJ1XK-L
P. 18/84
Murata Manufacturing Co., Ltd.

Specification Number: SP-CJ1XK-L
P. 19/84
Murata Manufacturing Co., Ltd.
11.2. UART Timing (Default Mode)
Default bard rate is 115200 bps. Baud rate is configurable by the host stack.
Symbol
Parameter
Condition
Min
Typ
Max
Unit
TBAUD
Baud rate
38.4MHz
250
-
-
ns
* The acceptable deviation from the UART Rx target baud rate is ±3%.
11.3. Bluetooth PCM Timing
11.3.1. Master mode
Data signals (Master mode)
PCM_SYNC signal (Master mode)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
FBCLK
Bit clock frequency
--
--
2/2.048
--
MHz
Duty CycleBCLK
Bit clock duty cycle
--
0.4
0.5
0.6
--
TBCLK rise/fall
PCM_CLK rise/fall time
--
--
3
--
ns
TDO
Delay from PCM_CLK rising edge to
PCM_DOUT rising edge
--
--
--
15
ns
TDISU
Setup time for PCM_DIN before
PCM_CLK falling edge
--
20
--
--
ns
TDIHO
Hold time for PCM_DIN after
PCM_CLK falling edge
--
15
--
--
ns
TBF
Delay from PCM_CLK rising edge to
PCM_SYNC rising edge
--
--
--
15
ns