Prestigio NOBILE 159W Operating manual

PRESTIGIO NOBILE 159W
TECHNICAL SERVICE
MANUAL

2
1.1. HardwareSpecification . 3
1.2. SoftwareSpecification .. 17
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1.1 HardwareSpecification.
A. CPU
TheIntel Pentium Mprocessorisahighperformance,lowpowermobileprocessorwith
severalmicro-architecturalenhancementsoverexistingIntelmobileprocessors.
Thefollowing listprovidessomeofthekeyfeaturesonthisprocessor:
SupportsIntel ArchitecturewithDynamicExecution
Highperformance,low-powercore
On-die, primary32-kbyteinstructioncacheand32-kbytewrite-backdatacache
On-die, 1-MBytesecondlevelcachewithAdvancedTransferCacheArchitecture
AdvancedBranchPredictionandDataPrefetchLogic
Streaming SIMDExtensions2(SSE2)
400-MHz, Source-Synchronousprocessorsystembus
AdvancedPowerManagementfeaturesincludingEnhancedIntelSpeedStep technology
Micro-FCPGAandMicro-FCBGApackaging technologies
TheIntelPentiumMprocessorismanufacturedonIntel’sadvanced0.13 micronprocess
technologywithcopperinterconnect.TheprocessormaintainssupportforMMX™technologyand
InternetStreamingSIMDinstructionsandfull compatibilitywithIA-32 software. Thehigh
performancecorefeaturesarchitecturalinnovationshlikeMicro-opFusionandAdvancedStack
Managementthatreduce thenumberofmicro-ops handledbytheprocessor.Theseresultsinmore
efficientscheduling andbetterperformance atlowerpower.Theon-die32-kBLevel1instruction
anddatacachesandthe1-MBLevel2cachewithAdvancedTransferCacheArchitectureenable
significantperformance improvementoverexistingmobileprocessors.Theprocessoralsofeaturesa
veryadvancedbranchpredictionarchitecturethatsignificantlyreducesthenumberofmispredicted
branches. Theprocessor’sDataPrefetchLogicspeculativelyfetchesdatatotheL2cachebeforean
L1cacherequestsoccurs, resultinginreducedbuscyclepenaltiesandimprovedperformance.
TheStreaming SIMDExtensions2(SSE2)enablebreak-throughlevelsofperformancein
multimediaapplicationsincluding 3-Dgraphics,videodecoding/encoding,andspeechrecognition.
Thenewpackeddouble-precisionfloating-pointinstructionsenhanceperformance forapplications
thatrequiregreaterrangeandprecision,including scientificandengineeringapplicationsand
advanced3-Dgeometrytechniques, suchasraytracing.
TheIntelPentiumMprocessor’s400-MHzprocessorsystembusutilizesasplit-transaction,
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deferredreplyprotocol. The400-MHzprocessorsystembususesSource-SynchronousTransfer
(SST)ofaddress anddatatoimproveperformancebytransferringdatafourtimes perbus clock(4X
datatransferrate,as inAGP4X).Alongwiththe4Xdatabus,theaddress bus candeliveraddresses
twotimesperbusclockandisreferredtoasa “double-clocked”or2Xaddress bus.Working
together,the4Xdatabusand2Xaddress busprovideadatabusbandwidthofup to3.2
Gbytes/second. TheprocessorsystembususesAdvancedGunning TransceiverLogic(AGTL+)
signaltechnology, avariantofGTL+signalling technologywithlowpowerenhancements.
Note: ThetermAGTL+hasbeenusedforAssistedGunning TransceiverLogictechnologyonother
Intelproducts.
TheprocessorfeaturesEnhancedIntelSpeedSteptechnology, whichenablesreal-timedynamic
switchingbetweenmultiplevoltageandfrequencypointsinsteadoftwopointssupportedon
previousversionsofIntelSpeedSteptechnology. Thisresultsinoptimalperformance without
compromising lowpower.TheprocessorfeaturestheAutoHalt, Stop-Grant,DeepSleep, and
DeeperSleeplowpowerstates.
TheIntelPentiumMprocessorutilizessocketableMicroFlip-ChipPinGridArray
(Micro-FCPGA)andsurface mountMicroFlip-ChipBallGridArray(Micro-FCBGA)package
technology. TheMicro-FCPGApackageplugsintoa479-hole,surface-mount, ZeroInsertionForce
(ZIF)socket, whichisreferredtoas themPGA479Msocket.
ThisdocumentincludesspecificationsfortheIntelPentiumMprocessoratHighestFrequency
Mode(HFM)corefrequenciesof1.30, 1.40, 1.50, 1.60 and1.70 GHz, theLowVoltageIntel
PentiumM processoratHFM corefrequencyof1.10 and1.20 GHzandtheUltraLowVoltageIntel
PentiumMprocessoratHFMcorefrequencyof900MHzand1.00 GHz.
B. NorthBridge –MCH855PM
Intel Centrino™mobiletechnologywithintegratedwirelessLANcapabilitieswasdesigned
specificallyforwirelessnotebookPCs –deliveringoutstandingmobileperformance andenabling
extendedbatterylifeandthinner,lighterdesigns.
TheIntel 855PMMemoryControllerHub(MCH)isanIntel Centrino™mobiletechnology
component. TheMCHmanagestheflowofinformationbetweenitsfourinterfaces:theprocessor
sidebus(communicationwiththeIntel Pentium Mprocessor),memoryinterface,AGPinterface,
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andhubinterface.TheMCHarbitrates betweenthefourinterfaces wheneachinitiates anoperation.
TheIntel 855PMmemorycontrollerhub(MCH)isdesignedforusewiththeIntel Pentium M
processor.TheMCHsupportsdatacoherencyviasnoopingandmustperformaddress translationfor
accesstoAGPAperturememory. Toincreasesystemperformance, theMCHincorporatesseveral
queues.
TheIntel 855PMMCHmaycontaindesigndefects orerrorsknownaserrata,whichmaycause
theproducttodeviatefrompublishedspecifications. Thisinformationwillbeavailablein
SpecificationUpdates.
Features
Processor/HostBusSupport
Supports theIntel Pentium Mprocessor
2xAddress, 4xData
Supportssystembusat400 MT/s
SupportshostbusDynamicBusInversion(DBI)
Supports32-bithostbusaddressing
12 deepIn-OrderQueue
AGTL+busdrivertechnologywithintegratedGTL terminationresistorsandlowvoltage
operation(1.05 V)
SupportforDPWR#signaltoIntel Pentium MprocessorforPSBpower
management
MemorySystem
Directlysupports oneDDRchannel, 64bwide(72bwithECC)
Supports200-MHzand266-MHzDDRdevices
Supports64-Mb, 128-Mb, 256-Mb, and512-Mbtechnologiesforx16 devicesandx8devices.
Allsupporteddeviceshavefourbanks
ConfigurableoptionalECC operation(singlebitErrorCorrectionandmultiplebitError
Detection)
Supportsup to16 simultaneousopenpages
Supports pagesizes of2kB,4kB, 8kB, and16 kB.Pagesize isindividuallyselectedforevery
row.
Thermalthrottling schemetoselectivelythrottlereadsand/orwrites. Throttlingcanbe
triggeredbypresetread/writebandwidthlimits.
ForDDR,Maxoftwo, double-sidedSODIMMs (fourrowspopulated)withunbuffered
PC1600/PC2100 DDR(withorwithoutECC)
Byusing stacked512-Mbtechnology, thelargestmemorycapacitypossibleis2.0GB
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SystemInterrupts
Supports8259 andprocessorsystembusinterruptdeliverymechanism
SupportsinterruptssignaledasupstreamMemoryWritesfromAGP/PCI(PCIsemanticsonly)
andhubinterface
MSIsenttotheCPUthroughtheSystemBus
FromIOxAPICinICH4-M
SupportspeerMSIbetweenhubinterfaceandAGP
Providesredirectionforupstreaminterrupts totheSystemBus
AcceleratedGraphicsPort(AGP)Interface
SupportsasingleAGPdevice (eitherthroughaconnectororonthemotherboard)
AGPSupport
SupportsAGP2.0including 1x, 2x, and4xAGPdatatransfersand2x/4xFastWriteprotocol
Supports only1.5-VAGPelectricals
32 deepAGPrequestqueue
PCIsemantic(FRAME#initiated)accessestoDRAMaresnooped
AGPsemantic(PIPE#andSBA)accessestoDRAMarenotsnooped
Highpriorityaccesssupport
HierarchicalPCIconfigurationmechanism
DelayedtransactionsupportforAGP-to-DRAMFRAME#semanticreadsthatcannotbe
servicedimmediately
32-bitupstreamaddresssupportforinboundAGPandPCIcycles
32-bitdownstreamaddresssupportforoutboundPCIandFastWritecycles
AGPBusy/StopProtocol
AGPClamping andSenseAmpControl
HubInterface toICH4-M
266 MB/spoint-to-pointhubinterface toICH4-M
66-MHzbaseclock
Supports thefollowing traffictypestotheICH4-M
1Hubinterface-to-AGPmemorywrites
2Hubinterface-to-DRAM
3CPU-to-hubinterface
4Messaging
-MSIInterruptmessages
-PowerManagementstatechange
-SMI, SCI, andSERR errorindication
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PowerManagement
SMRAMspaceremapping toA0000h(128 kB)
SupportsextendedSMRAMspace above256 MB, additional128k/256k/512k/1MBTSEG
fromTopofMemory, cacheable(cacheabilitycontrolledbyCPU)
APMRev1.2compliantpowermanagement
SuspendtoSystemMemory
ACPI1.0b, 2.0Support
EnhancedIntelSpeedStep TechnologySupport
CachecoherencywithCPUinsleepmode
DynamicMemoryPower-down
Package
Packageoptions
593-pinMicro-FCBGA(37.5x37.5mm)
C. SouthBridge –ICH4-M
TheICH4providesextensiveI/Osupport. Functionsandcapabilitiesinclude:
PCILocalBusSpecification,Revision2.2-compliantwithsupportfor33-MHzPCIoperations.
PCIslots(supportsup to6Req/Gntpairs)
ACPIPowerManagementLogicSupport
EnhancedDMAController, InterruptController, andTimerFunctions
IntegratedIDE controllersupportsUltraATA100/66/33
USBhostinterface withsupportfor6USBports;3UHCIhostcontrollers;1EHCIhigh-speed
USB2.0HostController
IntegratedLANController
SystemManagementBus(SMBus)Specification,Version2.0withadditionalsupportforI2C
devices
SupportsAudioCodec ’97,Revision2.3specification(a.k.a.,AC ’97 ComponentSpecification,
Revision2.3).LinkforAudioandTelephonycodecs(up to7channels)
LowPinCount(LPC)interface
FirmwareHub(FWH)interface support
AlertOnLAN*(AOL)andAlertOnLAN2* (AOL2)
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TheICH4incorporates avarietyofPCIfunctions thataredividedintothree logicaldevices (29, 30,
and31)onPCIBus0andonedevice onBus1. Device 30 istheHubInterface-To-PCIbridge.
Device31 contains alltheotherPCIfunctions,excepttheUSBControllers andtheLANController,
asshowninTable1-2.TheLANcontrollerislocatedonBus1.
PCIDevicesandFunctions
Feature
PCIBusInterface
ØSupportsPCIRevision2.2Specificationat33MHz
Ø133 MB/sec maximumthroughput
ØSupportsup to6masterdevicesonPCI
ØOnePCIREQ/GNTpaircanbegivenhigherarbitrationpriority(intendedforexternal
1394 hostcontroller)
ØSupportfor44-bitaddressingonPCIusingDACprotocol
IntegratedLANController
ØWfM2.0andIEEE802.3compliant
ØLANConnectInterface (LCI)
Ø10/100 Mbit/sec ethernetsupport
IntegratedIDE Controller
ØSupports “NativeMode”registerandinterrupts
ØIndependenttiming ofup to4drives, withseparateprimaryandsecondaryIDE cable
connections
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ØUltraATA/100/66/33, BMIDE andPIOmodes
ØTri-statemodestoenableswapbay
USB
ØIncludes3UHCIhostcontrollersthatsupport6externalports
ØNew:Includes1EHCIhigh-speedUSB2.0HostControllerthatsupportsallsixports
ØNew:SupportsaUSB2.0high-speeddebug port
ØSupportswake-up fromsleeping statesS1-M–S5
ØSupportslegacykeyboard/mousesoftware
AC'97 Link forAudioandTelephonyCODECs
ØNew:ThirdAC_SDATA_INlineforthree codec support
ØSupportsAC ’97 2.3
ØNew:Independentbus masterlogicfor7channels(PCMIn/Out,Mic1input,Mic2input,
modemin/out,S/PDIFout)
ØSeparateindependentPCIfunctionsforaudioandmodem
ØSupportforuptosixchannelsofPCMaudiooutput(full AC3decode)
ØSupportswake-up events
InterruptController
ØSupportupto8PCIinterruptpins
ØSupportsPCI2.2messagesignaledinterrupts
ØTwocascaded82C59 with15 interrupts
ØIntegratedI/OAPICcapabilitywith24 interrupts
ØSupportsserialinterruptprotocol
ØSupportsprocessorsystembusinterruptdelivery
New:1.5Voperationwith3.3VI/O
Ø5VtolerantbuffersonIDE, PCI, USBover-currentandlegacysignals
TimersBasedon82C54
ØSystemtimer, refreshrequest, speakertoneoutput
PowerManagementLogic
ØACPI2.0compliant
ØACPI-definedpowerstates(C1–C4,S1-M, S3–S5)
ØACPIpowermanagementtimer
ØSupportfor “Intel SpeedStepTM technology”processorpowercontrol
ØSupportfor “DeeperSleep”powerstate
ØPCICLKRUN#andPME#support
ØSMI#generation
ØAllregistersreadable/restorableforproperresumefrom0Vsuspendstates
ExternalGlueIntegration
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ØIntegratedpull-up, pull-downandseriesterminationresistors onIDE,processorinterface
ØIntegratedPull-downandSeriesresistorsonUSB
EnhancedHubInterface buffersimproveroutingflexibility(NotavailablewithallMemory
ControllerHubs)
FirmwareHub(FWH)Interface supportsBIOSmemorysizeup to8MB
LowPinCount(LPC)Interface
ØSupports twoMaster/DMAdevices.
EnhancedDMAController
ØTwocascaded8237 DMAcontrollers
ØPCIDMA:Supports PC/PCI —IncludestwoPC/PCIREQ#/GNT#pairs
ØSupportsLPCDMA
ØSupportsDMAcollectionbuffertoprovideType-FDMAperformance forallDMA
channels
Real-TimeClock
Ø256-bytebattery-backedCMOSRAM
SystemTCOReductionCircuits
ØTimerstogenerateSMI#andResetupondetectionofsystemhang
ØTimerstodetectimproperprocessorreset
ØSupportsabilitytodisableexternaldevices
SMBus
ØNew:Hardwarepacketerrorchecking
ØNew:SupportsSMBus2.0Specification
ØHostinterface allowsprocessortocommunicateviaSMBus
ØSlaveinterface allowsanexternalmicrocontrollertoaccess systemresources
ØCompatiblewithmost2-wirecomponentsthatarealsoI2Ccompatible
GPIO
ØTTL,open-drain,inversion
Package31x31 mm 421 BGA
D. ClockGenerator
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TheICS950813 isasinglechipclocksolutionfordesktopdesignsusing the
Brookdale/Odem/Montara-GMforP4/Baniasprocessor.
TheICS950813 ispartofawholenewlineofICSclockgeneratorsandbufferscalledTCHTM
(Timing ControlHub).ThispartincorporatesICS’snewestclocktechnologywithoffersmore
robustfeaturesandfunctionality. Employing theuseofaseriallyprogrammableI2Cinterface, this
device canadjusttheoutputclocksbyconfiguring thefrequencysetting, theoutputdividerrations,
selectingtheidealspreadpercentage,theoutputskew,theoutputstrength,theenabling /disabling
eachindividualoutputclock. M/Ncontrolcanconfigureoutputfrequencywithresolutionup to0.1
MHzincrement.
OutputFeatures
3DifferentialCPUClockPairs@3.3V
7PCI(3.3V)@33.3MHzincluding 2earlyPCIclocks
3PCI_F(3.3V)@33.3MHz
1USB(3.3V)@48MHz, 1DOT (3.3V)@48MHz
1REF(3.3V)@14.318MHz
53V66 (3.3V)@66.6MHz
1VCH/3V66 (3.3V)@48MHzor66.6MHz
Features / Benefits
Providesstandardfrequenciesandadditional3%, 5%and10%over-clockedfrequencies
Supportsspreadspectrummodulation:Nospread,CenterSpread(±0.3%, ±0.55%),orDownSpread
(-0.5%,-0.75%)
OffersadjustablePCIearlyclockvialatchinputs
Selectable1Xor2XstrengthforREFviaI2Cinterface
Programmablegroup togroupskew
Linearprogrammablefrequencyandspreading%
EfficientpowermanagementschemethroughPD#, CPU_STOP#andPCI_STOP#.
Usesexternal14.318MHzcrystal
Stopclocksandfunctionalcontrolavailablethrough I2Cinterface.
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KeySpecifications
nCPUOutputJitter<150ps
n3V66 OutputJitter<250ps
nCPUOutputSkew<100ps
E.VideoGraphics –ATiM11P
TheMOBILITYM11 providesoneofthefastestandmostadvanced2D, 3D, andmultimedia
graphicsperformance fornotebooks. Itsarchitectureintroduces thelatestachievementsinthe
graphicsindustry, whichenabletheuseoftheprogressivenewfeaturesinupcoming applications,
butwithoutcompromising performance. ATI’ssupportofDirectX 9features, highlyoptimized
OpenGL support,andflexiblememoryconfigurationsallowimplementationstargetedatthe
gaming enthusiast,consumer, business andworkstationplatforms.
SMARTSHADER™2.0 —AdvancedShaderTechnology
ØProvidescompletehardware-acceleratedsupportforthenewDirectX 9programmable
shadermodel, enabling morecomplexandrealistictextureandlightingeffects thanever
before.
ØSignificantimprovementoverfirst-generationshadersintroducedinDirectX 8, witha
muchmorepowerfulandintuitiveinstructionset.
ØOffersfullsupportforthisfeatureinOpenGL applications.
SMOOTHVISION™2.0 —FlexibleAnti-AliasingandAnisotropicFiltering
Ø2x/4x/6xfull-sceneanti-aliasing modes
ØAdaptivealgorithmwithprogrammablesamplepatterns
Ø2x/4x/8x/16xanisotropicfiltering modes
ØAdaptivealgorithmwithbi-linear(performance)andtri-linear(quality)options
HighPerformance MemorySupport
ØIncorporatessupportforDDRSDRAM/SGRAM.
ØFeatures keyitemsfromATI’s thirdgenerationHYPERZ™III technologythatconserves
memorybandwidthforimprovedperformance indemanding applications.
DualDisplaySupport
ØLeading-edgetechnology,fullyoptimizedwithHYDRAVISION™, flexiblysupports
multiplecombinationsofnotebookLCD,traditionalCRTmonitors,flatpaneldisplaysand
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TV.
ØFeaturesDualChannelDVIsupport.
Ø230MHzLVDStransmittersupportsLCDpanelsup toQXGA(2048x1536)resolution.
ØIntegrated165MHzTMDStransmittersupportsexternalflatpanelsup toUXGA
(1600x1200)resolution.
ØHighperformance DACspeedsof400MHz.
VIDEOAcceleration
ØM11allowstheintegrationofindustryleadingdigitalvideofeatures, including advanced
de-interlacing algorithmsforunprecedentedvideoqualityandintegrateddigitalTV
decodecapability. Includesprogrammable,independentgammacontrolforthevideo
overlay.
ØNewFULLSTREAM™technologyremovesblockyartifactsfromstreaming andInternet
videoandprovidessharperimagequality.
ØIntegratedgeneralpurposexDCT engine(capableofperforming bothforwardandinverse
discretecosinetransform)andmotioncompensation(MC)supportfortheaccelerationof
MPEGencodinganddecodingaswellasDV(digitalvideo)encodinganddecoding.
Features InDetail
2DAccelerationFeatures
ØAhighlyoptimized128-bitengine, capableofprocessing multiplepixels/clock.
ØHardwareaccelerationis providedforBitblt, linedrawing,polygonandrectanglefills, bit
masking,monochromeexpansion,panning andscrolling,scissoring,andfullROPsupport
(including ROP3).
ØOptimizedhandling offontsandtextusingATIproprietarytechniques.
ØGameaccelerationincluding supportforMicrosoft'sDirectDraw:DoubleBuffering,
VirtualSprites,TransparentBlit, andMaskedBlit.
ØAccelerationin8/15/16/32 bpp modes.
ØSupportforWIN2000 &WINXPGDIextensions:AlphaBLT,TransparentBLT,
GradientFill.
ØHardwarecursorsupportup to64x64x32bpp, withalphachannelfordirectsupportof
WIN2000 &WINXPalphacursorstandard.
3DAccelerationFeatures
ØFourparallel3Drendering pipelines.
ØFullDirectX9PixelShader2.0support.
ØFullDX9conformance,including floatingpointpercomponentatfullspeed.
ØSupportfor2xAA, 4xAAand6xAAsubsamples, withlittleperformance loss inmost
cases.
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ØAdvancedAAqualityalgorithms, generatingvisualsthataresuperiortoothersolutions
withanequivalentnumberofsamples.
Ø2x/4x/8x/16xanisotropicfiltering modes.Adaptivealgorithmwithbi-linear(performance)
andtri-linear(quality)options.
ØUpto16uniquetextures, sharing8textureaddresses.
ØDedicatedgeometryaccelerationforDirect3DandOpenGL,whichincorporates2parallel
Vector/ScalarEnginesperforming HWtransformation, clipping andlighting,including:
TextureCoordinateGeneration.
VertexBlending (skinning)with4matrices.
6userdefined clipplanes.
8light support.
DirectionalandLocalLighting.
ØFullycompliantDirectX9,ShaderModel2.0,ProgrammableVertexShader(fulloperand
andoperationsupport)withup to256 instructionsand256 vectors ofconstantstore.This
includes VertexShaderLoops, Branches, andSubroutines, whichallowforvertexshader
programsofaround64,000 instructionsinlength.
MotionVideoAccelerationFeatures
ØVideoscaling andfullyprogrammableYCrCbtoRGBcolorspace conversionfor
full-screen/full-speedvideoplaybackandfullyadjustablecolorcontrols.
ØHardwareI2C.
ØVIP2.0withmultichannelDMAtransfer.
Ø16-bitZoomVideoport.
ØFrontendscalersupportfor8, 15, 16, and32 bpp colordepths.
ØBackendoverlay/scalersupportsupto8x4tapfiltering, andalwaysensuresatleast4x2
tapfiltering eveninextremecases. 4x4tapistypical. Back-endscaleralsosupports
upscaling anddownscaling, filteredscaling ofallsupportedYUVformats, RGB32 and
RGB15/16, andfiltereddisplayofimagesup to1536 pixelswide.
ØEnhancedMPEG-2hardwareencode/decodeacceleration,including supportfor:
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Integrated generalpurposexDCTengine (capableof performing
bothforwardand inversediscretecosinetransform)
Motion compensation (MC)supportforthe acceleration of MPEG
encoding and decoding aswellasDV(digitalvideo)encoding and
decoding.
Paralleloperation ofthe xDCTand MCand high processing rates
withminimalsoftwareoverhead
ØProvidesdramaticallyreducedCPUutilizationwithoutincurring thecostofafull
MPEG-2decoder.
ØMPEG-4simpleprofilesupport.
ØSupportsall formatDTV/HDTVdecodeandtopqualityDVD withlowestCPUusage.
(Note:DTV/HDTVsupportisthroughcomponentoutput, notDVI.)
ØAdaptivede-interlacingfiltereliminatesvideoartifactscausedbydisplaying interlaced
videoonnon-interlaceddisplays, byanalyzing imageandusing optimalde-interlacing
functiononaper-pixelbasis.
DualDisplayFeatures
General
ØHydravisionfordualmonitorsupport.
ØDualindependentdisplays(LCD/DVI, DVI/CRT,LCD/TV, CRT/TV,etc.)
ØTwoindependentCRTcontrollerstosupporttwoasynchronoussimultaneousdisplay
paths.
ØIntegratedsecondDACforthesecondCRT(TV)support.
ØTwotriple10-bitpaletteDACswithgammacorrectionfortrueWYSIWYGcolor. Pixel
ratesupto400MHzstandard.
ØResolution, refreshratesanddisplaydatacanbecompletelyindependent.
ØPrimarydisplaypathsupports VGAandacceleratedmodes, videooverlay, hardware
cursor, andpalettegammacorrection.
ØSecondarydisplaypathsupportsacceleratedmodes, videooverlay,hardwarecursor,and
palettegammacorrection. However, itdoesnotsupportVGA.
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ØSinglevideooverlayusing back-endscalerisswitchablebetweendisplays.
ØSupports twonewgraphicsformats:16bpp aRGB4444 and16bpp alphaandindex88.
Alsosupports8/15/16/24/32 bpp graphicsformats withgammacorrectioninallmodes.
ØSupportforauxiliarywindowsignal.
ØSupportforupto4k x4k resolutiondisplay.
ØSupportforDDC1andDDC2B+forplug andplaymonitors, andAppleSensemonitor
detectionsupport.
Ø8-bitalphablending ofgraphicsandvideooverlay.
ØIndependentDDClinesforDACandTMDSconnections.AlsofullAppleSensesupport
onDACconnection.
ØHardwarecursorupto64x64 pixels in2bpp,fullcolorAND/XORmix,andfullcolor8-bit
alphablend.
ØIndependenth/wicon&h/wcursoronbothdisplaypaths(simultaneoush/wcursor&
icon).
ØVirtualdesktopsupport.
TVOut
AnintegratedTVencoderwithon-chiptripleDACallowssimultaneousCRT/LCD/TV
outputwiththeseoutstandingTV-outcharacteristics:
Ø10-bitDACwith8-tapfilterproducingscaled,flickerremoved, artifactsuppressed
displayonaPALorNTSCTVwithComposite, S-Video, andRGBoutputs.
ØSupportforMacrovision7.02 copyprotectionstandard(requiredbyDVD players)-a
fullyprogrammabletiming capability,itwillaccommodatepotentialchangesinthe
Macrovisionalgorithmwithoutanyhardwarechanges.
ØYUVDirect/Pass throughmodeforvideo/MPEGplaybackandDVD providesthebest
qualitymovieplayback, italsoallows titles tobedisplayedonTVwiththeiroriginalhigh
qualityandwithoutanyartifactfromtheTV-outcircuit.
ØSecondarydisplaysupportfortheRGBmode.
Ø1024x768 32bpp support. Modessupportedinclude800x600 and16:9modessuchas
848x480, withuserflexibilityformovingandsizingthescreen.
ØLine21 ClosedCaptionandExtendedDataServicesupportforencodinginVertical
Blanking Interval(VBI) ofTVsignal.
ØCGMS-ADVD copymanagementsupportinVBIthroughLine-20 and/orExtendedData
Service (Line-21 Field2).
ØUVfiltering basedoncoloraveraging resultsinasharperpictureaswellasreduced
flicker.
ØATI'sexclusive"CompositeDotCrawl"freeze optionforPALandNTSCtoimprove
picturequality.
Componentoutput
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ØComponentoutput(YPbPr)for480i, 480p, 720pand1080i(NTSConly).
ØNosupportforscalingorflickerremovaltocomponentvideooutputs.
ØIncludesNTSCMacrovisionandCGMS.
DigitalDisplaySupport
General
ØSupportforfixedresolutiondisplays(e.g. panels)fromVGA(640x480)towideUXGA
(1600x1200)resolutionwithfullratiometricexpansionabilityforsource modesup to
1280x1024. HigherresolutionpanelsanddigitalCRTsmaybepossiblysupported-
contactATIfordetails.
ØImprovedautoexpansion.
ØOptionalauto-centeringmodetodisplaydesktopatnativesize withoutratiometric
expansion.
ØSupportforVGAtextmodesincenteringpanelmodes(uptoapproximately165 MHz
pixelfrequency).
ØSupportforreducedblanking intervals, asdefinedbyVESA.
ØHDCPready.
LVDS
AnintegratedLVDStransmitterforexcellentLCDimagequality:
ØSingleanddualpixelperclock, up to230MHzdual-channel(115MHzperchannel)
ØSupportsLCDpanelsup toQXGA(2048x1536)60Hzresolution.
ØGeneralpurposeI/OpinsthatallowssupportofLCDpaneldetection.
ØConformance withOpenLDIandVESAFPDIspecifications.
ØCommonPanelInterface Specification(CPIS)compliant.
ØRatiometricexpansionwithimprovedsharpnessfortopimagequalitywhenscaling up
fromanon-nativeresolution.
TMDS
ØIntegratedTMDStransmitterrunning up to165MHz(supportsbothcoherentand
non-coherentclockingsystems)forsupportupto1600x1200 at60Hz.FullyCompliant
withDVIandDFPconnectionstandards. Ratiometricexpansion.
ØSupportforexternalTMDStransmitterviadigitaloutput(configurableasa12 bitor24bit
DDRbus)todrivemostpopularTMDStransmittersup to165MHzfrequency.
ØSupportsDVI,DFP andVESAP&DinterfaceswithintegratedTMDStransmitter.
ØTMDStransmitterfullysupportsreducedblanking.
BusSupportFeatures
ØComprehensiveAGPsupport:
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AGP3.0mode: 4Xand 8X operation.
AGP2.0mode (1.5Vsignalingonly)
Sideband Addressing.
AGPTexturing (Executemode).
BothAGPreadsandwrites(withsupport forthe fast write’
capabilitydefined inrevision 2.0of theAGPspecification).
ØPCI2.3compliance (usingAGPelectricalinterface).
MemorySupportFeatures
Ø128/64-bitmemoryinterface using DDRSGRAM, SDRAMorDDRIISDRAMtobuild
16/32/64/128/256 MBconfigurations.
ØSupportforSSTL-2, andSSTL-1.8(1.8Vself-terminated)memoryinterfaces.
ØSupportsElpidaDDRSDRAM, whichissimilartotheDDRprotocolwiththefollowing
exceptions:
Lowerpowerthroughthe useof datainversionsignalsforboth
writesand reads
Higherclock speedswithnoexternaltermination required
PowerManagementFeatures
ØSinglechipsolutionin0.13 micron, 1.0V-1.2VCMOStechnology
ØFullACPI1.0b, OnNow,andIAPC(InstantlyAvailablePC)powermanagement.
ØPCIbuspowermanagement1.1andAGPBusyand StopsignalsRev1.61 andSolano
2-M.
ØStaticanddynamicPowerManagementsupport(APMaswellasACPI) withfullVESA
DPMandEnergyStarcompliance.
ØAGP_BUSY/STP_AGPpowermanagement.
ØFullPOWERPLAYTM,including enhancedPOWERON DEMAND support.
ØTheChipPowerManagementSupportlogicsupportsfourdevice powerstates-On,
Standby,SuspendandOff-definedfortheOnNowArchitecture.Eachpowerstatecanbe
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achievedbysoftwarecontrolbits.
ØClockstoeverymajorfunctionalblockarecontrolledbyauniquedynamicclock
switchingtechniquewhichiscompletelytransparenttothesoftware.Byturningoff the
clocktotheblockthatisidleornotusedatthatpoint, thepowerconsumptionis
significantlyreducedduringnormaloperation.
InternalLVDSSpreadSpectrumSupport
ØTheMOBILITYM11SpreadSpectrumcontrolleriscapableofgeneratingatriangular
frequencymodulationprofile.Theamountofspreadandthemodulationfrequencyis fully
programmable.
ØOnlytheLVDSdisplayisavailabletobespread(i.e., 1PLL).
ExternalSpreadSpectrumSupport
ØMemoryand/orcoreclockspreadspectrumsupportviatheGPIO16 pin.
ØExternalspreadspectrumsupportedforTMDSorLVDStransmittersviathe
SSIN/SSOUTpin.
PCDesignGuideCompliance
MOBILITYM11complieswithall relevantsectionsofthecurrentPCdesignguidespecifications
fromIntel/Microsoft.
ØFullycompliantwithPC99, PC99a,andPC2001 requirements.
ØFullycompliantwithMobilePCIrev1.0.
ØBi-endiansupportforcompliance onavarietyofprocessorplatforms.
TestCapabilityFeatures
TheMOBILITYM11hasavarietyoftestmodesandcapabilitiesthatprovideaveryhighfault
coverageandlowDPM(defectpermillion)ratio:
ØFullscanimplementationonthedigitalcorelogicwhichprovideshighfaultcoverage
throughATPG(AutomaticTestPatternGenerationVectors).
ØDedicatedtestlogicfortheon-chipcustommemorymacrostoprovidecompletecoverage
onthesemodules.
ØAJTAG testmode(whichisnotentirelycomplianttotheIEEE 1149.1standard)foraccess
tochip-leveltestfunctionsandforboardlevelconnectivitytesting.
ØIntegratedhardwarediagnostictestsperformedautomaticallyuponinitialization.
ØHighqualitycomponentsthroughat-speedtesting, built-inScan, Iddq, CRC, chip
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