Prestigio NOBILE 159W Operating manual

PRESTIGIO NOBILE 159W
TECHNICAL SERVICE
MANUAL

2
1.1. HardwareSpecification . 3
1.2. SoftwareSpecification .. 17
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1.1 HardwareSpecification.
A. CPU
TheIntel Pentium Mprocessorisahighperformance,lowpowermobileprocessorwith
severalmicro-architecturalenhancementsoverexistingIntelmobileprocessors.
Thefollowing listprovidessomeofthekeyfeaturesonthisprocessor:
SupportsIntel ArchitecturewithDynamicExecution
Highperformance,low-powercore
On-die, primary32-kbyteinstructioncacheand32-kbytewrite-backdatacache
On-die, 1-MBytesecondlevelcachewithAdvancedTransferCacheArchitecture
AdvancedBranchPredictionandDataPrefetchLogic
Streaming SIMDExtensions2(SSE2)
400-MHz, Source-Synchronousprocessorsystembus
AdvancedPowerManagementfeaturesincludingEnhancedIntelSpeedStep technology
Micro-FCPGAandMicro-FCBGApackaging technologies
TheIntelPentiumMprocessorismanufacturedonIntel’sadvanced0.13 micronprocess
technologywithcopperinterconnect.TheprocessormaintainssupportforMMX™technologyand
InternetStreamingSIMDinstructionsandfull compatibilitywithIA-32 software. Thehigh
performancecorefeaturesarchitecturalinnovationshlikeMicro-opFusionandAdvancedStack
Managementthatreduce thenumberofmicro-ops handledbytheprocessor.Theseresultsinmore
efficientscheduling andbetterperformance atlowerpower.Theon-die32-kBLevel1instruction
anddatacachesandthe1-MBLevel2cachewithAdvancedTransferCacheArchitectureenable
significantperformance improvementoverexistingmobileprocessors.Theprocessoralsofeaturesa
veryadvancedbranchpredictionarchitecturethatsignificantlyreducesthenumberofmispredicted
branches. Theprocessor’sDataPrefetchLogicspeculativelyfetchesdatatotheL2cachebeforean
L1cacherequestsoccurs, resultinginreducedbuscyclepenaltiesandimprovedperformance.
TheStreaming SIMDExtensions2(SSE2)enablebreak-throughlevelsofperformancein
multimediaapplicationsincluding 3-Dgraphics,videodecoding/encoding,andspeechrecognition.
Thenewpackeddouble-precisionfloating-pointinstructionsenhanceperformance forapplications
thatrequiregreaterrangeandprecision,including scientificandengineeringapplicationsand
advanced3-Dgeometrytechniques, suchasraytracing.
TheIntelPentiumMprocessor’s400-MHzprocessorsystembusutilizesasplit-transaction,
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deferredreplyprotocol. The400-MHzprocessorsystembususesSource-SynchronousTransfer
(SST)ofaddress anddatatoimproveperformancebytransferringdatafourtimes perbus clock(4X
datatransferrate,as inAGP4X).Alongwiththe4Xdatabus,theaddress bus candeliveraddresses
twotimesperbusclockandisreferredtoasa “double-clocked”or2Xaddress bus.Working
together,the4Xdatabusand2Xaddress busprovideadatabusbandwidthofup to3.2
Gbytes/second. TheprocessorsystembususesAdvancedGunning TransceiverLogic(AGTL+)
signaltechnology, avariantofGTL+signalling technologywithlowpowerenhancements.
Note: ThetermAGTL+hasbeenusedforAssistedGunning TransceiverLogictechnologyonother
Intelproducts.
TheprocessorfeaturesEnhancedIntelSpeedSteptechnology, whichenablesreal-timedynamic
switchingbetweenmultiplevoltageandfrequencypointsinsteadoftwopointssupportedon
previousversionsofIntelSpeedSteptechnology. Thisresultsinoptimalperformance without
compromising lowpower.TheprocessorfeaturestheAutoHalt, Stop-Grant,DeepSleep, and
DeeperSleeplowpowerstates.
TheIntelPentiumMprocessorutilizessocketableMicroFlip-ChipPinGridArray
(Micro-FCPGA)andsurface mountMicroFlip-ChipBallGridArray(Micro-FCBGA)package
technology. TheMicro-FCPGApackageplugsintoa479-hole,surface-mount, ZeroInsertionForce
(ZIF)socket, whichisreferredtoas themPGA479Msocket.
ThisdocumentincludesspecificationsfortheIntelPentiumMprocessoratHighestFrequency
Mode(HFM)corefrequenciesof1.30, 1.40, 1.50, 1.60 and1.70 GHz, theLowVoltageIntel
PentiumM processoratHFM corefrequencyof1.10 and1.20 GHzandtheUltraLowVoltageIntel
PentiumMprocessoratHFMcorefrequencyof900MHzand1.00 GHz.
B. NorthBridge –MCH855PM
Intel Centrino™mobiletechnologywithintegratedwirelessLANcapabilitieswasdesigned
specificallyforwirelessnotebookPCs –deliveringoutstandingmobileperformance andenabling
extendedbatterylifeandthinner,lighterdesigns.
TheIntel 855PMMemoryControllerHub(MCH)isanIntel Centrino™mobiletechnology
component. TheMCHmanagestheflowofinformationbetweenitsfourinterfaces:theprocessor
sidebus(communicationwiththeIntel Pentium Mprocessor),memoryinterface,AGPinterface,
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andhubinterface.TheMCHarbitrates betweenthefourinterfaces wheneachinitiates anoperation.
TheIntel 855PMmemorycontrollerhub(MCH)isdesignedforusewiththeIntel Pentium M
processor.TheMCHsupportsdatacoherencyviasnoopingandmustperformaddress translationfor
accesstoAGPAperturememory. Toincreasesystemperformance, theMCHincorporatesseveral
queues.
TheIntel 855PMMCHmaycontaindesigndefects orerrorsknownaserrata,whichmaycause
theproducttodeviatefrompublishedspecifications. Thisinformationwillbeavailablein
SpecificationUpdates.
Features
Processor/HostBusSupport
Supports theIntel Pentium Mprocessor
2xAddress, 4xData
Supportssystembusat400 MT/s
SupportshostbusDynamicBusInversion(DBI)
Supports32-bithostbusaddressing
12 deepIn-OrderQueue
AGTL+busdrivertechnologywithintegratedGTL terminationresistorsandlowvoltage
operation(1.05 V)
SupportforDPWR#signaltoIntel Pentium MprocessorforPSBpower
management
MemorySystem
Directlysupports oneDDRchannel, 64bwide(72bwithECC)
Supports200-MHzand266-MHzDDRdevices
Supports64-Mb, 128-Mb, 256-Mb, and512-Mbtechnologiesforx16 devicesandx8devices.
Allsupporteddeviceshavefourbanks
ConfigurableoptionalECC operation(singlebitErrorCorrectionandmultiplebitError
Detection)
Supportsup to16 simultaneousopenpages
Supports pagesizes of2kB,4kB, 8kB, and16 kB.Pagesize isindividuallyselectedforevery
row.
Thermalthrottling schemetoselectivelythrottlereadsand/orwrites. Throttlingcanbe
triggeredbypresetread/writebandwidthlimits.
ForDDR,Maxoftwo, double-sidedSODIMMs (fourrowspopulated)withunbuffered
PC1600/PC2100 DDR(withorwithoutECC)
Byusing stacked512-Mbtechnology, thelargestmemorycapacitypossibleis2.0GB
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SystemInterrupts
Supports8259 andprocessorsystembusinterruptdeliverymechanism
SupportsinterruptssignaledasupstreamMemoryWritesfromAGP/PCI(PCIsemanticsonly)
andhubinterface
MSIsenttotheCPUthroughtheSystemBus
FromIOxAPICinICH4-M
SupportspeerMSIbetweenhubinterfaceandAGP
Providesredirectionforupstreaminterrupts totheSystemBus
AcceleratedGraphicsPort(AGP)Interface
SupportsasingleAGPdevice (eitherthroughaconnectororonthemotherboard)
AGPSupport
SupportsAGP2.0including 1x, 2x, and4xAGPdatatransfersand2x/4xFastWriteprotocol
Supports only1.5-VAGPelectricals
32 deepAGPrequestqueue
PCIsemantic(FRAME#initiated)accessestoDRAMaresnooped
AGPsemantic(PIPE#andSBA)accessestoDRAMarenotsnooped
Highpriorityaccesssupport
HierarchicalPCIconfigurationmechanism
DelayedtransactionsupportforAGP-to-DRAMFRAME#semanticreadsthatcannotbe
servicedimmediately
32-bitupstreamaddresssupportforinboundAGPandPCIcycles
32-bitdownstreamaddresssupportforoutboundPCIandFastWritecycles
AGPBusy/StopProtocol
AGPClamping andSenseAmpControl
HubInterface toICH4-M
266 MB/spoint-to-pointhubinterface toICH4-M
66-MHzbaseclock
Supports thefollowing traffictypestotheICH4-M
1Hubinterface-to-AGPmemorywrites
2Hubinterface-to-DRAM
3CPU-to-hubinterface
4Messaging
-MSIInterruptmessages
-PowerManagementstatechange
-SMI, SCI, andSERR errorindication
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PowerManagement
SMRAMspaceremapping toA0000h(128 kB)
SupportsextendedSMRAMspace above256 MB, additional128k/256k/512k/1MBTSEG
fromTopofMemory, cacheable(cacheabilitycontrolledbyCPU)
APMRev1.2compliantpowermanagement
SuspendtoSystemMemory
ACPI1.0b, 2.0Support
EnhancedIntelSpeedStep TechnologySupport
CachecoherencywithCPUinsleepmode
DynamicMemoryPower-down
Package
Packageoptions
593-pinMicro-FCBGA(37.5x37.5mm)
C. SouthBridge –ICH4-M
TheICH4providesextensiveI/Osupport. Functionsandcapabilitiesinclude:
PCILocalBusSpecification,Revision2.2-compliantwithsupportfor33-MHzPCIoperations.
PCIslots(supportsup to6Req/Gntpairs)
ACPIPowerManagementLogicSupport
EnhancedDMAController, InterruptController, andTimerFunctions
IntegratedIDE controllersupportsUltraATA100/66/33
USBhostinterface withsupportfor6USBports;3UHCIhostcontrollers;1EHCIhigh-speed
USB2.0HostController
IntegratedLANController
SystemManagementBus(SMBus)Specification,Version2.0withadditionalsupportforI2C
devices
SupportsAudioCodec ’97,Revision2.3specification(a.k.a.,AC ’97 ComponentSpecification,
Revision2.3).LinkforAudioandTelephonycodecs(up to7channels)
LowPinCount(LPC)interface
FirmwareHub(FWH)interface support
AlertOnLAN*(AOL)andAlertOnLAN2* (AOL2)
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TheICH4incorporates avarietyofPCIfunctions thataredividedintothree logicaldevices (29, 30,
and31)onPCIBus0andonedevice onBus1. Device 30 istheHubInterface-To-PCIbridge.
Device31 contains alltheotherPCIfunctions,excepttheUSBControllers andtheLANController,
asshowninTable1-2.TheLANcontrollerislocatedonBus1.
PCIDevicesandFunctions
Feature
PCIBusInterface
ØSupportsPCIRevision2.2Specificationat33MHz
Ø133 MB/sec maximumthroughput
ØSupportsup to6masterdevicesonPCI
ØOnePCIREQ/GNTpaircanbegivenhigherarbitrationpriority(intendedforexternal
1394 hostcontroller)
ØSupportfor44-bitaddressingonPCIusingDACprotocol
IntegratedLANController
ØWfM2.0andIEEE802.3compliant
ØLANConnectInterface (LCI)
Ø10/100 Mbit/sec ethernetsupport
IntegratedIDE Controller
ØSupports “NativeMode”registerandinterrupts
ØIndependenttiming ofup to4drives, withseparateprimaryandsecondaryIDE cable
connections
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ØUltraATA/100/66/33, BMIDE andPIOmodes
ØTri-statemodestoenableswapbay
USB
ØIncludes3UHCIhostcontrollersthatsupport6externalports
ØNew:Includes1EHCIhigh-speedUSB2.0HostControllerthatsupportsallsixports
ØNew:SupportsaUSB2.0high-speeddebug port
ØSupportswake-up fromsleeping statesS1-M–S5
ØSupportslegacykeyboard/mousesoftware
AC'97 Link forAudioandTelephonyCODECs
ØNew:ThirdAC_SDATA_INlineforthree codec support
ØSupportsAC ’97 2.3
ØNew:Independentbus masterlogicfor7channels(PCMIn/Out,Mic1input,Mic2input,
modemin/out,S/PDIFout)
ØSeparateindependentPCIfunctionsforaudioandmodem
ØSupportforuptosixchannelsofPCMaudiooutput(full AC3decode)
ØSupportswake-up events
InterruptController
ØSupportupto8PCIinterruptpins
ØSupportsPCI2.2messagesignaledinterrupts
ØTwocascaded82C59 with15 interrupts
ØIntegratedI/OAPICcapabilitywith24 interrupts
ØSupportsserialinterruptprotocol
ØSupportsprocessorsystembusinterruptdelivery
New:1.5Voperationwith3.3VI/O
Ø5VtolerantbuffersonIDE, PCI, USBover-currentandlegacysignals
TimersBasedon82C54
ØSystemtimer, refreshrequest, speakertoneoutput
PowerManagementLogic
ØACPI2.0compliant
ØACPI-definedpowerstates(C1–C4,S1-M, S3–S5)
ØACPIpowermanagementtimer
ØSupportfor “Intel SpeedStepTM technology”processorpowercontrol
ØSupportfor “DeeperSleep”powerstate
ØPCICLKRUN#andPME#support
ØSMI#generation
ØAllregistersreadable/restorableforproperresumefrom0Vsuspendstates
ExternalGlueIntegration
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