Rohm BU2365FV Specification sheet

TECHNICAL NOTE
High-performance Clock Generator Series
Clock Generator
with Built-in VCXO
for Audio/Video Equipments
BU2365FV
●Description
The ROHM Clock Generator is an IC allowing for the generation of multiple clocks by a single chip through the connection of
a single crystal oscillator. The BU2365FV incorporates the ROHM’s unique PLL technology to provide the generation of
multiple high C/N clocks necessary for the DVD recorder system. This Clock Generator has the built-in high-precision
VCXO function and allows for high-precision synchronization with DVD Video clocks. It also has a built-in buffer having high
driving force and allows the supply of multiple 27MHz Video clocks for the system, thus providing the reduced number of the
system components.
●Features
1) The ROHM’s unique PLL technology allows for the generation of high C/N clocks.
2) Built-in high precision VCXO, which is essential for the DVD recorder system
3) Built-in buffer having high driving force (Load capacity/output CL=50pF, 27MHz drive, 1×input / 2×outputs)
4) Built-in half pulse clock protection [HPC]
5) Built-in power down function, Icc=0 uA(typ.)
6) SSOP-B24 package
7) Single power supply of 3.3 V
●Application
DVD recorder
●Absolute Maximum Ratings（Ta=2 5℃）
Parameter Symbol Limit Unit
Supply voltage VDD －0.3～7.0 Ｖ
Input voltage VIN －0.3～VDD+0.3 Ｖ
Storage temperature range Tst g －30～125 ℃
Power dissipation PD 820 mW
*1 Operation is not guaranteed.
*2 In the case of exceeding Ta = 25℃, 8.2mW should be reduced per 1℃.
*3 The radiation-resistance design is not carried out.
*4 Power dissipation is measured when the IC is mounted to the printed circuit board.
Sep. 2008

2/16
●Recommended Operating Range
Parameter Symbol Limit Unit
Supply voltage VDD 3.0～3.6 Ｖ
Input H voltage VINH 0.8VDD～VDD Ｖ
Input L voltage VINL 0.0～0.2VDD Ｖ
Operating temperature Topr －10～70 ℃
Output load
22Pin / 19Pin CL_CLK768FS/384FS 32(MAX) pF
13Pin , 14Pin CL_BUFOUT 50(MAX) pF
18Pin / 24Pin CL_CLK512FS/54M 15(MAX) pF
● Electrical characteristics
VDD=3.3V, Ta=25℃, Crystal frequency (XTAL_IN)=27.000000MHz, at no load, unless otherwise specified.
Parameter Symbol Limit Unit Condition
Min. Typ. Max.
【Consumption circuit current】IDD －55 71.5 mA At no output loads
【Output H voltage】VOH 2.4 －－V When current load =-4.0mA
【Output L voltage】VOL －－0.4 V When current load =4.0mA
【Pull-Up resistance value】
FSEL、OE Pull-Up
R 168 260 578 kΩ
Specified by a current value running
when a voltage of 0V is applied to a
measuring pin. (R=DD/I)
【Pull-Down resistance value】
TEST Pull-down
R 31 48 106 kΩ
Specified by a current value running
when a VDD is applied to a measuring
pin. (R=VDD/I)
【Output frequency】
CLK768FS：FSEL=L CLK768
FS_L －33.868800 －MHz
XTAL_IN×(3136/625)/4
CLK768FS：FSEL=H CLK768
FS_H －36.864000 －MHz
XTAL_IN×(2048/375)/4
CLK384FS CLK384
FS －18.432000 －MHz
XTAL_IN×(2048/375)/8
CLK512FS CLK512
FS －24.576000 －MHz
XTAL_IN×(2048/375)/6
CLK54M CLK54M －54.000000 －MHz XTAL_IN×(32/4)/4
【Output waveform】
Duty Duty1 45 50 55 ％Measured at a voltage of 1/2 of VDD
Rise time Tr －2.5 －nsec Period of time required for the output
to reach 80% from 20% of VDD
Fall time Tf －2.5 －nsec Period of time required for the output
to reach 20% from 80% of VDD
【Jitter】
Period-Jitter 1σP-J1σ－50 －psec ※1
Period-Jitter MIN-MAX P-J
MIN-MAX －300 －psec
※2
【Output Lock-Time】Tlock －－1 msec ※3
【Frequency stability】ΔF/F0 －15 －15 ppm T=-10～70 ℃、VDD=3.3V ±
0.15V ※4
【Frequency sensitivity】ΔF/Fc ±30 ±45 ±60 ppm ※5
【Frequency sensitivity linearity】Linearity －10 10 ppm
※5
【Buffer skew】Tskew
_BUF －500 －500 psec
Phase difference between
BUF_OUT1 and BUF_OUT26
【Buffer delay】Td_BUF －4 8 nsec Phase difference between
BUF_IN and BUF_OUT
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to XTAL_IN.

3/16
※1 Period-Jitter 1σ
This parameter represents standard deviation (=1σ) on cycle distribution data at the time when the output clock cycles are
sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd.
※2 Period-Jitter MIN-MAX
This parameter represents a maximum distribution width on cycle distribution data at the time when the output clock cycles are
sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd.
※3 Output Lock-Time
This parameter represents elapsed time after power supply turns ON to reach a voltage of 3.0 V, after the system is switched from
Power-Down state to normal operation state, or after the output frequency is switched, until it is stabilized at a specified frequency,
respectively.
※4 Frequency stability
f0 : This parameter means an optimum frequency at T=25℃(27.000000 MHz), which represents a value of a single piece of IC.
Since no consideration is given to the stability of the crystal oscillator, it should be separately studied according to the system in
use.
※5 Frequency sensitivity/Frequency sensitivity linearity
These parameters represents that the frequency falls within the area shown in Fig. 2 in the control circuit of control voltage shown
in Fig. 1. It shows the value of IC itself. Since no consideration is given to the stability of the crystal oscillator, it should be
separately studied according to the system in use.
※Common – Recommended crystal oscillators
The electrical characteristics shown above have been all evaluated with the use of the crystal oscillator NX5032GA (Spec. No.
EXS00A-00278) manufactured by NIHON DEMPA KOGYO CO., LTD., under the conditions of Limiting resistance Rd=30Ωand
Crystal oscillator load CL=10pF. Consequently, in order to use the BU2365FV, the said crystal oscillator is recommended.
Fig.1 Control Circuit of Control Voltage
Frequency sensitivity dispersion range: fL =－45±15ppm, fC= 0±15ppm, fH= 45±15ppm
However, frequency sensitivity linearity: －10ppm≦(fH－f
C) －( fC－f L) ≦＋10ppm
Fig. 2 Frequency Sensitivity Dispersion Range
※6 Buffer skew
This parameter is only functional when the BUF_OUT1 and the BUF_OUT2 are driven at the same load capacitance.
Δf/f0
Hi-ZL H
0ppm
+60ppm
－60ppm
+15ppm
－15ppm
Vc
+30ppm
－30ppm
+45ppm
－45ppm
fH
fC
fL
R2
Vc
BU2365FV
R1：R2=1：0.875
R1
R1
10Pin：VCT R L
9Pin：VDD_V
Δf/f0

4/16
●Reference data (Basic data)
Fig.5 33.8688MHz spectrum
VDD=3.3V,CL=32pF
Fig.6 36.864MHz output
waveform
VDD=3.3V,CL=32pF
Fig.7 36.864MHz Period-Jitter
VDD=3.3V,CL=32pF
Fig.8 36.864MHz spectrum
VDD=3.3V,CL=32pF
Fig.9 18.432MHz output
waveform
VDD=3.3V,CL=32pF
Fig.10 18.432MHz Period-Jitter
VDD=3.3V,CL=32pF
Fig.11 18.432MHz spectrum
VDD=3.3V,CL=32pF
Fig.12 24.576MHz output
waveform
VDD=3.3V,CL=15pF
Fig.13 24.576MHz Period-Jitter
VDD=3.3V,CL=15pF
Fig.14 24.576MHz spectrum
VDD=3.3V,CL=15pF
Fig.3 33.8688MHz output
waveform
VDD=3.3V,CL=32pF
Fig.4 33.8688MHz Period-Jitter
VDD=3.3V,CL=32pF
1.0V／div
5.0nsec／div
1.0V／div
500psec／div
10dB／div
10KHz／div
RBW=1KHz
VBW=100Hz
1.0V／div
5.0nsec／div
1.0V／div
500psec／div
10dB／div
10KHz／div
RBW=1KHz
VBW=100Hz
1.0V／div
10.0nsec／div
1.0V／div
500psec／div
10dB／div
10KHz／div
RBW=1KHz
VBW=100Hz
1.0V／div
5.0nsec／div
1.0V／div
500psec／div
10dB／div
10KHz／div
RBW=1KHz
VBW=100Hz

5/16
●Reference data (Basic data)
Fig.23 VCXO_OUT(27MHz) spectrum
VDD=3.3V,CL=4pF
Fig.20 BUF_OUT(27MHz) spectrum
VDD=3.3V,CL=50pF
Fig.15 54MHz output
waveform
VDD=3.3V,CL=15pF
Fig.16 54MHz Period-Jitter
VDD=3.3V,CL=15pF
Fig.17 54MHz spectrum
VDD=3.3V,CL=15pF
Fig.18 BUF_OUT(27MHz) output
waveform
VDD=3.3V,CL=50pF
Fig.19 BUF_OUT(27MHz) Period-Jitter
VDD=3.3V,CL=50pF
Fig.21 VCXO_OUT(27MHz) output
waveform
VDD=3.3V,CL=4pF
Fig.22 VCXO_OUT(27MHz) Period-Jitter
VDD=3.3V,CL=4pF
Fig.24 Buffer skew output
waveform
VDD=3.3V,CL=50pF
Fig.25 Buffer delay(IN→OUT1)
VDD=3.3V,CL=50pF
Fig.26 Buffer delay(IN→OUT2)
VDD=3.3V,CL=50pF
1.0V／div
5.0nsec／div
1.0V／div
500psec／div
10dB／div
10KHz／div
RBW=1KHz
VBW=100Hz
1.0V／div
5.0nsec／div
1.0V／div
500psec／div
10dB／div
10KHz／div
RBW=1KHz
VBW=100Hz
1.0V／div
5.0nsec／div
1.0V／div
500psec／div
10dB／div
10KHz／div
RBW=1KHz
VBW=100Hz
0.5V／div
5.0nsec／div
0.5V／div
5.0nsec／div
0.5V／div
5.0nsec／div

6/16
●Reference data (PLL: 33.8688MHz output Temperature and Supply voltage variations data)
特性データ)
Fig.28 33.8688MHz
Temperature－rise-time
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-25 0 25 50 75 100
Temperature：T [℃]
Rise Time：Tr [nsec]
Fig.27 33.8688MHz
Temperature－Duty
Fig.29 33.8688MHz
Temperature－fall-time
Fig.30 33.8688MHz
Temperature－Period-Jitter 1σFig.31 33.8688MHz
Temperature－Period-Jitter MIN-MAX
Fig.32 36.864MHz
Temperature－Duty Fig.33 36.864MHz
Temperature－rise-time
Fig.34 36.864MHz
Temperature－fall-time
Fig.35 36.864MHz
Temperature－Period-Jitter 1σ
Fig.36 36.864MHz
Temperature－Period-Jitter MIN-MAX
45
46
47
48
49
50
51
52
53
54
55
-25 0 25 50 75 100
Temperature：T [℃]
Duty：Duty [%]
VDD=2.9V
VDD=3.3V
VDD=3.7V
VDD=2.9V
VDD=3.3V
VDD=3.7V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-25 0 25 50 75 100
Temperature：T [℃]
Fall Time ：Tf [nsec]
VDD=2.9V
VDD=3.3V
VDD=3.7V
0
10
20
30
40
50
60
70
80
90
100
-25 0 25 50 75 100
Temperature：T [℃]
Period-Jitter 1σ：P-J1σ[psec]
0
100
200
300
400
500
600
-25 0 25 50 75 100
Temperature：T [℃]
Period-Jitter MIN-MAX：
P-JMIN-MAX [psec]
VDD=2.9V
VDD=3.3V
VDD=3.7V
45
46
47
48
49
50
51
52
53
54
55
-25 0 25 50 75 100
Temperature：T [℃]
Duty：Duty [%]
VDD=3.7V
VDD=2.9V
VDD=3.3V
VDD=2.9V
VDD=3.3V
VDD=3.7V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-25 0 25 50 75 100
Temperature：T [℃]
Rise Time：Tr [nsec]
VDD=2.9V
VDD=3.3V
VDD=3.7V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-25 0 25 50 75 100
Temperature：T [℃]
Fall Time：Tf [nsec]
VDD=2.9V
VDD=3.3V
VDD=3.7V
0
100
200
300
400
500
600
-25 0 25 50 75 100
Temperature：T [℃]
Period-Jitter MIN-MAX：
P-JMIN-MAX [psec]
VDD=2.9V
VDD=3.3V
VDD=3.7V
VDD=2.9V
VDD=3.7V
VDD=3.3V
0
10
20
30
40
50
60
70
80
90
100
-25 0 25 50 75 100
Temperature：T [℃]
Period-Jitter 1σ：P-J1σ[psec]
●Reference data (PLL: 36.864MHz output Temperature and Supply voltage variations data)

7/16
●Reference data (PLL: 18.432MHz output Temperature and Supply voltage variations data)
●Reference data (PLL: 24.576MHz output Temperature and Supply voltage variations data)
Fig.46 24.576MHz
Temperature－Period-Jitter MIN-MAX
0
100
200
300
400
500
600
-25 0 25 50 75 100
Temperature：T [℃]
Period-Jitter MIN-MAX：
P-JMIN-MAX [psec]
Fig.42 24.576MHz
Temperature－Duty
45
46
47
48
49
50
51
52
53
54
55
-25 0 25 50 75 100
Temperature：T [℃]
Duty：Duty [%]
Fig.38 18.432MHz
Temperature－rise-time
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-25 0 25 50 75 100
Temperature：T [℃]
Rise Time：Tr [nsec]
Fig.37 18.432MHz
Temperature－Duty
45
46
47
48
49
50
51
52
53
54
55
-25 0 25 50 75 100
Temperature：T [℃]
Duty ：Duty [%]
Fig.39 18.432MHz
Temperature－fall-time
Fig.40 18.432MHz
Temperature－Period-Jitter 1σ
Fig.41 18.432MHz
Temperature－Period-Jitter MIN-MAX
Fig.43 24.576MHz
Temperature－rise-time
Fig.44 24.576MHz
Temperature－fall-time
Fig.45 24.576MHz
Temperature－Period-Jitter 1σ
VDD=3.3V
VDD=2.9V
VDD=3.7V
VDD=2.9V
VDD=3.3V
VDD=3.7V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-25 0 25 50 75 100
Temperature：T [℃]
Fall Time：Tf [nsec]
VDD=2.9V
VDD=3.3V
VDD=3.7V
0
10
20
30
40
50
60
70
80
90
100
-25 0 25 50 75 100
Temperature：T [℃]
Period-Jitter 1σ：P-J1σ [psec]
0
100
200
300
400
500
600
-25 0 25 50 75 100
Temperature：T [℃]
Period-Jitter MIN-MAX：
P-JMIN-MAX [psec]
VDD=2.9V
VDD=3.3V
VDD=3.7V
VDD=2.9V
VDD=3.3V
VDD=3.7V
VDD=2.9V
VDD=3.3V
VDD=3.7V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-25 0 25 50 75 100
Temperature：T [℃]
Rise Time：Tr [nsec]
VDD=2.9V
VDD=3.3V
VDD=3.7V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-25 0 25 50 75 100
Temperature：T [℃]
Fall Time ：Tf [nsec]
VDD=2.9V
VDD=3.3V
VDD=3.7V
0
10
20
30
40
50
60
70
80
90
100
-25 0 25 50 75 100
Temperature：T [℃]
Period-Jitter 1σ：P-J1σ[psec]
VDD=2.9V
VDD=3.3V
VDD=3.7V
VDD=2.9V
VDD=3.3V
VDD=3.7V

8/16
●Reference data (PLL: 54MHz output Temperature and Supply voltage variations data)
●Reference data (CLOCK-BUFFER : 27MHz output Temperature and Supply voltage variations data)
Fig.57 27MHz BUFFER
Temperature – Skew
(BUF_OUT2 Phase Delay)
Fig.56 27MHz BUFFER
Temperature – Skew
(BUF_OUT2 Phase Lead)
-500
-400
-300
-200
-100
0
100
200
300
400
500
-25 0 25 50 75 100
Temperature：T [℃]
Buffer Skew：Tskew_BUF [psec]
Fig.55 27MHz BUFFER
Temperature－Delay
0
1
2
3
4
5
6
7
8
-25 0 25 50 75 100
Temperature：T [℃]
Buffer Delay：Td_BUF [nsec]
Fig.48 54MHz
Temperature－rise-time
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-25 0 25 50 75 100
Temperature：T [℃]
Rise Time：Tr [nsec]
Fig.47 54MHz
Temperature－Duty
45
46
47
48
49
50
51
52
53
54
55
-25 0 25 50 75 100
Temperature：T [℃]
Duty ：Duty [%]
Fig.49 54MHz
Temperature－fall-time
Fig.50 54MHz
Temperature－Period-Jitter 1σ
Fig.51 54MHz
Temperature－Period-Jitter MIN-MAX
Fig.52 27MHz BUFFER
Temperature－Duty
Fig.53 27MHz BUFFER
Temperature－rise-time
Fig.54 27MHz BUFFER
Temperature－fall-time
VDD=2.9V
VDD=3.3V
VDD=3.7V
VDD=2.9V
VDD=3.3V
VDD=3.7V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-25 0 25 50 75 100
Temperature：T [℃]
Fall Time：Tf [nsec]
VDD=2.9V
VDD=3.3V
VDD=3.7V
0
10
20
30
40
50
60
70
80
90
100
-25 0 25 50 75 100
Temperature：T [℃]
Period-Jitter 1σ：P-J1σ[psec]
0
100
200
300
400
500
600
-25 0 25 50 75 100
Temperature：T [℃]
Period-Jitter MIN-MAX：
P-JMIN-MAX [psec]
VDD=2.9V
VDD=3.3V
VDD=3.7V
VDD=2.9V
VDD=3.3V
VDD=3.7V
45
46
47
48
49
50
51
52
53
54
55
-25 0 25 50 75 100
Temperature：T [℃]
Duty：Duty [%]
VDD=2.9V
VDD=3.3V
VDD=3.7V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-25 0 25 50 75 100
Temperature：T [℃]
Rise Time ：Tr [nsec]
VDD=2.9V
VDD=3.3V
VDD=3.7V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-25 0 25 50 75 100
Temperature：T [℃]
Fall Time：Tf [nsec]
VDD=2.9V
VDD=3.3V
VDD=3.7V
VDD=2.9V
VDD=3.3V
VDD=3.7V
VDD=2.9V
VDD=3.3V
VDD=3.7V
-500
-400
-300
-200
-100
0
100
200
300
400
500
-25 0 25 50 75 100
Temperature：T [℃]
Buffer Skew：Tskew_BUF [psec]
VDD=2.9V
VDD=3.3V
VDD=3.7V

9/16
●Reference data (VCXO:27MHz output Temperature and Supply voltage variations data)
This data represents the central frequency as a deviation to the optimum frequency of 27.000000MHz.
●Reference data (VCXO : 27MHz output Control voltage – Frequency data)
This data represents the central frequency as a deviation to the optimum frequency of 27.000000MHz.
●Reference data (BU2365FV consumption current Temperature and Supply voltage variations data)
Fig.60 27MHz VCXO
Temperature－fall-time
Fig.65 Maximum Load
Operating Circuit Current
Fig.63 27MHz VCXO
Temperature – Central frequency fc
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-25 0 25 50 75 100
Temperature：T [℃]
Fall Time：Tf [nsec]
Fig.58 27MHz VCXO
Temperature－Duty
Fig.59 27MHz VCXO
Temperature－rise-time
Fig.61 27MHz VCXO
Temperature－Period-Jitter 1σ
Fig.62 27MHz VCXO
Temperature－Period-Jitter MIN-MAX
Fig.64 27MHz VCXO
Control voltage – Frequency data
Fig.66 Power-down
Standby Current
45
46
47
48
49
50
51
52
53
54
55
-25 0 25 50 75 100
Temperature：T [℃]
Duty：Duty [%]
VDD=2.9V
VDD=3.3V
VDD=3.7V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-25 0 25 50 75 100
Temperature：T [℃]
Rise Time：Tr [nsec]
VDD=2.9V
VDD=3.3V
VDD=3.7V
VDD=2.9V
VDD=3.3V
VDD=3.7V
-15
-12
-9
-6
-3
0
3
6
9
12
15
-25 0 25 50 75 100
Temperature：T [℃]
Center freq.：fc [ppm]
VDD=3.45V
VDD=3.15V
VDD=3.30V
0
10
20
30
40
50
60
70
80
90
100
-25 0 25 50 75 100
Temperature：T [℃]
Period-Jitter 1σ：P-J1σ [psec]
0
100
200
300
400
500
600
-25 0 25 50 75 100
Temperature：T [℃]
Period-Jitter MIN-MAX ：
P-JMIN-MAX [psec]
VDD=2.9V
VDD=3.7V
VDD=3.3V
VDD=2.9V
VDD=3.3V
VDD=3.7V
-100
-80
-60
-40
-20
0
20
40
60
80
100
0 0.55 1.1 1.65 2.2 2.75 3.3
Control Voltage：Vc [V]
Frequency：f [ppm]
VDD=3.3V
50
55
60
65
70
75
80
85
90
95
100
-25 0 25 50 75 100
Temperature：T [℃]
Circuit Current：Icc [mA]
VDD=3.7V
VDD=3.3V
VDD=2.9V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-25 0 25 50 75 100
Temperature：T [℃]
Standby Current ：Iccs [μA]
VDD=3.7V
VDD=3.3V
VDD=2.9V

10/16
●Reference data (PLL : Long Term Jitter data)
This data represents Period-Jitter at the 1000th cycle.
●Reference data (Period-Jitter MIN-MAX Output load CL dependence data)
This data represents the output load up to two times as high as the maximum load of each output.
Since the 27-MHz buffer is dependent on the jitter of a clock input, the output is represented by the ratio to the jitter at 50pF.
Fig.67 33.8688MHz
Long Term Jitter
Fig.68 36.864MHz
Long Term Jitter
Fig.69 54MHz
Long Term Jitter
Fig.70 33.8688MHz
CL－Period-Jitter MIN-MAX
Fig.71 36.864MHz
CL－Period-Jitter MIN-MAX
Fig.72 18.432MHz
CL－Period-Jitter MIN-MAX
Fig.73 24.576MHz
CL－Period-Jitter MIN-MAX
Fig.74 54MHz
CL－Period-Jitter MIN-MAX
Fig.75 27MHz VCXO
CL－Period-Jitter MIN-MAX
0
100
200
300
400
500
600
700
0 10203040506070
Output Load：CL [pF]
Period-Jitter MIN-MAX：
P-JMIN-MAX [psec]
VDD=3.3V
0
100
200
300
400
500
600
700
0 10203040506070
Output Load：CL [pF]
Period-Jitter MIN-MAX ：
P-JMIN-MAX [psec]
VDD=3.3V
0
100
200
300
400
500
600
700
0 10203040506070
Output Load：CL [pF]
Period-Jitter MIN-MAX ：
P-JMIN-MAX [psec]
VDD=3.3V
0
100
200
300
400
500
600
700
0 5 10 15 20 25 30
Output Load：CL [pF]
Period-Jitter MIN-MAX：
P-JMIN-MAX [psec]
VDD=3.3V
0
100
200
300
400
500
600
700
0 5 10 15 20 25 30
Output Load：CL [pF]
Period-Jitter MIN-MAX：
P-JMIN-MAX [psec]
VDD=3.3V
0
100
200
300
400
500
600
700
012345678
Output Load：CL [pF]
Period-Jitter MIN-MAX：
P-JMIN-MAX [psec]
VDD=3.3V
Fig.76 27MHz BUFFER
CL－Period-Jitter MIN-MAX
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0 25 50 75 100
Output Load：CL [pF]
Period-Jitter MIN-MAX ：
P-JMIN-MAX
VDD=3.3V
0.5V／div
2.0nsec／div
0.5V／div
2.0nsec／div
0.5V／div
2.0nsec／div