Siemens CPU 412-1 User manual

S7-400 Instruction List
CPU 412, 414, 416, 417
This Instruction List has the order number:
6ES7498-8AA04-8BN0
Edition 04/2004
A5E00267845-01

We have checked the contents of this manual for agreement with the
hardware and software described. Since deviations cannot be
precludedentirely, we cannot guarantee full agreement. However,
the data in this manual are reviewed regularly and any necessary
corrections included in subsequent editions. Suggestions for
improvementare welcomed.
Disclaimer of LiabilityCopyright Siemens AG 2004 All rights reserved
The reproduction, transmission or use of this document or its
contents is not permitted without express written authority.
Offenders will be liable for damages. All rights, including rights
createdby patent grant or registration of a utility model or design, are
reserved.
SiemensAG
Bereich Automation and Drives
Geschaeftsgebiet Industrial Automation Systems
Postfach 4848, D- 90327 Nuernberg SiemensAG 2004
Subject to change without prior notice
Siemens Aktiengesellschaft 6ES7498-8AA04-8BN0

Contents
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Contents
Contents 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Applicability 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Identifier and Parameter Ranges 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Identifier and Parameter Ranges, continued 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Identifier and Parameter Ranges, continued 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Constants and Ranges 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations and Mnemonics 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations and Mnemonics, continued 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Examples of Addressing 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Examples of Addressing, continued 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Examples of how to calculate the pointer 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Execution Times with Indirect Addressing1 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Examples of Calculations 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Instructions 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Logic Instructions 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Logic Instructions with Parenthetical Expressions 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Logic Instructions with Parenthetical Expressions, continued 29. . . . . . . . . . . . . . . . . . . . . .

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ORing of AND Instructions 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Instructions with Timers and Counters 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Word Logic Instructions with the Contents of Accumulator 1 33. . . . . . . . . . . . . . . . . . . . . . . . .
Evaluating Conditions Using AND, OR and EXCLUSIVE OR 35. . . . . . . . . . . . . . . . . . . . . . . . .
Edge-Triggered Instructions 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting/Resetting Bit Addresses 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instructions Directly Affecting the RLO 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Instructions 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter Instructions 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Load Instructions 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Load Instructions for Timers and Counters 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transfer Instructions 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Load and Transfer Instructions for Address Registers 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Load and Transfer Instructions for the Status Word 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Load Instructions for DB Number and DB Length 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Integer Math (16 Bits) 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Integer Math (32 Bits) 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Floating-Point Math (32 Bits) 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Square Root and Square Instructions (32 Bits) 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logarithmic Function (32 Bits) 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trigonometrical Functions (32 Bits) 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding Constants 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding Using Address Registers 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Comparison Instructions (16-Bit Integers) 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Comparison Instructions (32-Bit Integers) 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Comparison Instructions (32-Bit Real Numbers) 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shift Instructions 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rotate Instructions 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accumulator Transfer Instructions, Incrementing and Decrementing 79. . . . . . . . . . . . . . . . . .
Accumulator Transfer Instructions, Incrementing and Decrementing, continued 80. . . . . . . . .
Program Display and Null Operation Instructions 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Type Conversion Instructions 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Forming the Ones and Twos Complements 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Call Instructions 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Block End Instructions 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exchanging Shared Data Block and Instance Data Block 90. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jump Instructions 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instructions for the Master Control Relay (MCR) 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oganization Blocks (OB) 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Function Blocks (FB) 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functions (FC) and Data Blocks 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Functions 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Function Blocks 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sublist of the System Status List (SSL) 148. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alphabetical Index of Instructions 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Applicability
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Applicability
This list of instructions applies to the CPUs listed below.
Name Order number subsequently described as*
CPU 412-1 6ES7412-1XF04-0AB0
CPU 412
CPU 412-2 6ES7412-2XG04-0AB0
CPU 412
CPU 414-2 6ES7414-2XG04-0AB0
CPU 414-3 6ES7414-3XJ04-0AB0 CPU 414
CPU 414-4H 6ES7414-4HJ04-0AB0
CPU 414
CPU 416-2 6ES7416-2XK04-0AB0
CPU 416F-2 6ES7416-2FK04-0AB0 CPU 416
CPU 416-3 6ES7416-3XL04-0AB0
CPU 416
CPU 417-4 6ES7417-4XL04-0AB0
CPU 417
CPU 417-4 H 6ES7417-4HL04-0AB0
CPU 417
* except in the tables, where a detailled differentiation is necessary

Address Identifier and Parameter Ranges
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Address Identifier and Parameter Ranges
Addr. ParameterRange Description
ID CPU 412 CPU 414 CPU 416 CPU 417
Description
Q** 0.0 to 127.7 0.0 to 255.7 0.0 to 511.7 0.0 to 1023.7 Output (in PIQ)
QB** 0 to 127 0 to 255 0 to 511 0 to 1023 Output byte (in PIQ)
QW** 0 to 126 0 to 254 0 to 510 0 to 1022 Output word (in PIQ)
QD** 0 to 124 0 to 252 0 to 508 0 to 1020 Output double word (in PIQ)
DBX 0.0 to 65533.7* 0.0 to 65533.7 0.0 to 65533.7 0.0 to 65533.7 Data bit in data block
DB 1 to 511 1 to 4095 1 to 4095 1 to 8191 Data block
DBB 0 to 65533* 0 to 65533 0 to 65533 0 to 65533 Data byte in DB
DBW 0 to 65532* 0 to 65532 0 to 65532 0 to 65532 Data word in DB
DBD 0 to 65530* 0 to 65530 0 to 65530 0 to 65530 Data double word in DB
DIX 0.0 to 65533.7* 0.0 to 65533.7 0.0 to 65533.7 0.0 to 65533.7 Data bit in instance DB
DI 1 to 511 1 to 4095 1 to 4095 1 to 8191 Instance data block
DIB 0 to 65533* 0 to 65533 0 to 65533 0 to 65533 Data byte in instance DB
DIW 0 to 65532* 0 to 65532 0 to 65532 0 to 65532 Data word in instance DB
DID 0 to 65530* 0 to 65530 0 to 65530 0 to 65530 Data double word instance DB
*Also restricted by the size of the working memory.
** Default setting can be changed, see Technical Specifications

Address Identifier and Parameter Ranges
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Address Identifier and Parameter Ranges, continued
Addr. ParameterRange Description
ID CPU 412 CPU 414 CPU 416 CPU 417
Description
I** 0.0 to 127.7 0.0 to 255.7 0.0 to 511.7 0.0 to 1023.7 Input bit (in PII)
IB** 0 to 127 0 to 255 0 to 511 0 to 1023 Input byte (in PII)
IW** 0 to 126 0 to 254 0 to 510 0 to 1022 Input word (in PII)
ID** 0 to 124 0 to 252 0 to 508 0 to 1020 Input double word (in PII)
L** 0.0 to 4095.7 0.0 to 8191.7 0.0 to 16383.7 0.0 to 32767.7 Local data
LB** 0 to 4095 0 to 8191 0 to 16383 0 to 32767 Local data byte
LW** 0 to 4094 0 to
8190 0 to 16382 0 to 32766 Local data word
LD** 0 to 4092 0 to 8188 0 to 16380 0 to 32764 Local data double word
M0.0 to 4095.7 0.0 to 8191.7 0.0 to 16383.7 0.0 to 16383.7 Bit memory
MB 0 to 4095 0 to 8191 0 to 16383 0 to 16383 memory byte
MW 0 to 4094 0 to 8190 0 to 16382 0 to 16382 memory word
MD 0 to 4092 0 to 8188 0 to 16380 0 to 16380 memory double word
** Default setting can be changed, see Technical Specifications

Address Identifier and Parameter Ranges
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Address Identifier and Parameter Ranges, continued
Addr. ParameterRange Description
ID CPU 412 CPU 414 CPU 416 CPU 417
Description
PQB 0 to 4095 0 to 8191 0 to 16383 0 to 16383 Peripheral output byte
(direct I/O access)
PQW 0 to 4094 0 to 8190 0 to 16382 0 to 16382 Peripheral output word
(direct I/O access)
PQD 0 to 4092 0 to 8188 0 to 16380 0 to 16380 Peripheral output double word
(direct I/O access)
PIB 0 to 4095 0 to 8191 0 to 16383 0 to 16383 Peripheral input byte
(direct I/O access)
PIW 0 to 4094 0 to 8190 0 to 16382 0 to 16382 Peripheral input word
(direct I/O access)
PID 0 to 4092 0 to 8188 0 to 16380 0 to 16380 Peripheral output double word
(direct I/O access)
T0 to 2047 0 to 2047 0 to 2047 0 to 2047 Timer
C0 to 2047 0 to 2047 0 to 2047 0 to 2047 Counter