Phytec phyCORE-i.MX31 User manual

phyCORE-i.MX31
HARDWARE MANUAL
EDITION JULY 2007
A product of a PHYTEC Technology Holding company

phyCOREi.MX31
©PHYTEC Messtechnik GmbH 2007 L-700e_0
In this manual are descriptions for copyrighted products that are not explicitly indicated
as such. The absence of the trademark (™) and copyright (©) symbols does not imply
that a product is not protected. Additionally, registered patents and trademarks are
similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is believed to be
entirely reliable. However, PHYTEC Messtechnik GmbH assumes no responsibility for
any inaccuracies. PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts
any liability whatsoever for consequential damages resulting from the use of this manual
or its associated product. PHYTEC Messtechnik GmbH reserves the right to alter the
information contained herein without prior notification and accepts no responsibility for
any damages which might result.
Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability
for damages arising from the improper usage or improper installation of the hardware or
software. PHYTEC Messtechnik GmbH further reserves the right to alter the layout
and/or design of the hardware without prior notification and accepts no liability for doing
so.
©Copyright 2007 PHYTEC Messtechnik GmbH, D-55129 Mainz.
Rights - including those of translation, reprint, broadcast, photomechanical or similar
reproduction and storage or processing in computer systems, in whole or in part - are
reserved. No reproduction may occur without the express written consent from PHYTEC
Messtechnik GmbH.
EUROPE NORTH AMERICA
Address: PHYTEC Technologie Holding AG
Robert-Koch-Str. 39
D-55129 Mainz
GERMANY
PHYTEC America LLC
203 Parfitt Way SW, Suite G100
Bainbridge Island, WA 98110
USA
Ordering
Information: [phone]
[email protected] 1 [phone] [email protected]
Technical
Support: [phone]
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Fax: [phone] [phone]
Web Site: http://www.phytec.de http://www.phytec.com
Preliminary Edition Juni 2007

Contents
©PHYTEC Messtechnik GmbH 2007 L-700e_0
1Preface.......................................................................................1
1.1 Introduction.........................................................................2
1.2 Block Diagram....................................................................4
1.3 View of the phyCORE-i.MX31............................................5
2Pin Description.........................................................................7
3Jumpers...................................................................................21
4Power Requirements..............................................................26
5Real Time Clock U18 / SRAM U19 Battery ...........................28
6System Configuration............................................................29
7System Memory......................................................................30
7.1 Memory Model..................................................................31
7.2 LP-DDR-SDRAM (U5-U8)................................................32
7.3 NOR-Flash (U15)..............................................................33
7.4 NAND Flash Memory (U14) .............................................34
7.4.1 8/16-Bit NAND Flash Usage (JN1,JN2,RN41,RN42) 35
7.5 I²C EEPROM (U17)..........................................................36
7.5.1 Setting the EEPROM Lower Address Bits (J4, J5, J6) 37
7.5.2 EEPROM Write Protection Control (J8)................38
7.6 RS-232 Transceiver (U21) ...............................................39
7.6.1 UART3 Routing (RN47)........................................40
8USB-OTG Transceiver (U22)..................................................41
9Ethernet Controller (U3).........................................................42
10 JTAG Interface (X2)................................................................43
11 Technical Specifications .......................................................48
12 Hints for Handling the phyCORE-i.MX31 .............................50
13 The phyCORE i.MX31 on the i.MX Carrier Board................51
13.1 Concept of the phyCORE-i.MX Carrier Board..................52
13.2 Connectors.......................................................................54
13.3 Jumpers............................................................................56
13.4 phyMAP-i.MX31................................................................60
13.5 Functional Components on the phyCORE-i.MX Carrier Board 62
13.5.1 Power Supply (X26)..............................................63
13.5.2 Fuse Jumper (JP14 – Attention see manual).......65
13.5.3 RS-232 Interfaces (P1).........................................66
13.5.4 CAN Interface (P2) ...............................................70
13.5.5 Push Buttons and LEDs .......................................72
13.5.6 Keypad (X18)........................................................77
13.5.7 Compact Flash Card (X10)...................................79
13.5.8 Security Digital Card/ MultiMedia Card (X15).......81
13.5.9 Ethernet Interface (X27) .......................................82
13.5.10 Zigbee (X19)...........................................84

phyCOREi.MX31
©PHYTEC Messtechnik GmbH 2007 L-700e_0
13.5.11 One-Wire (X9).........................................86
13.5.12 USB Host (X17) ......................................87
13.5.13 USB OTG (X16)......................................88
13.5.14 Universal LCD Pin Header (X23)............89
13.5.15 Serial LCD (X24).....................................93
13.5.16 Camera Interface (X7,X8).......................95
13.5.17 JTAG Interface (X6)..............................100
13.5.18 Expansion Bus Connectors ..................102
13.5.19 Carrier Board Physical Dimensions......115
13.6 Sharp LQ035Q7DH06 LCD Adapter..............................116
13.6.1 LCD-004 Physical Dimensions...........................118
14 Revision History...................................................................119
15 Component Placement Diagram.........................................120
Index..............................................................................................122

Contents
©PHYTEC Messtechnik GmbH 2007 L-700e_0
Index of Figures
Figure 1: Block Diagram phyCORE-i.MX31 ....................................4
Figure 2: Top View of the phyCORE-i.MX31 (controller side).........5
Figure 3: Bottom View of the phyCORE-i.MX31 (connector side)...6
Figure 4: Pinout of the phyCORE-Connector (Top View, with Cross Section
Insert)................................................................................8
Figure 5: Numbering of the Jumper Pads......................................21
Figure 6: Location of the Jumpers (Top View)...............................22
Figure 7: Location of the Jumpers (Bottom View) .........................23
Figure 8: JTAG Interface X2 (Top View)........................................43
Figure 9: JTAG Interface X2 (Bottom View) ..................................44
Figure 10: Physical Dimensions ......................................................48
Figure 11: phyCORE-i.MX31 Carrier Board Connection Using the
phyMAPPER-i.MX31......................................................52
Figure 12: Modular Development and Expansion Board Concept with
phyCORE-i.MX31...........................................................53
Figure 13: Carrier Board Connector Locations................................55
Figure 14: Typical Jumper Numbering Scheme..............................56
Figure 15: Carrier Board Jumper Locations ....................................57
Figure 16: phyMAP-i.MX31 Jumper Placement and Numbering.....61
Figure 17: Power Adapter................................................................64
Figure 18: UART1 and UART3 Connection Interface at Connector P1 66
Figure 19: UART1 Connector P1B Signal Description....................67
Figure 20: UART3 Connector P1A Signal Description....................69
Figure 21: Socket P2 Signal Diagram..............................................71
Figure 22 - LED and Button Locations.............................................72
Figure 23: Freescale daughter card.................................................85
Figure 24: LCD-004 Adapter Board for the Sharp LQ035Q7DH06 LCD 116
Figure 25 - LCD Adapter connector locationFehler! Textmarke nicht
definiert.

phyCOREi.MX31
©PHYTEC Messtechnik GmbH 2007 L-700e_0
Figure 26: phyCORE-i.MX31 Component Placement, Top View..120
Figure 27: phyCORE-i.MX31 Component Placement, Bottom View121

Contents
©PHYTEC Messtechnik GmbH 2007 L-700e_0
Index of Tables
Table 1: Pinout of the phyCORE-Connector X1.............................9
Table 2: Jumper Settings..............................................................24
Table 3: i.MX31 Default Power Input Voltages.............................26
Table 4: x_VBAT Operating Limits...............................................28
Table 5: i.MX31 Memory Map ......................................................31
Table 6: Compatible NOR Flash Devices.....................................33
Table 7: Compatible NAND Flash Devices ..................................34
Table 8: JN1/2,RN41/42 NAND Flash Bit Width Selection...........35
Table 9: J4, J5, J6 EEPROM Lower Address Bits ......................37
Table 10: J8, EEPROM Write Protection States ............................38
Table 11: RN47 UART3 Routing....................................................40
Table 12: Ethernet Controller Memory Map ...................................42
Table 13: JTAG Connector X2 Signal Assignment ........................46
Table 14: Carrier Board Connectors...............................................54
Table 15: Carrier Board Jumper Descriptions................................57
Table 16: phyMAP-i.MX31 Solder Jumpers and Signal Routing....61
Table 17: FUSE Jumper.................................................................65
Table 18: UART1 Jumper Settings.................................................68
Table 21: CAN On-board Supply....................................................71
Table 22: CAN External Supply......................................................71
Table 23: System Control Buttons..................................................73
Table 25: Carrier Board LEDs ........................................................74
Table 26: Clock Selection...............................................................75
Table 27: Boot_Mode2 selection....................................................75
Table 28: Boot_Mode4 selection....................................................75
Table 29: x_switch (not used).........................................................75
Table 30: Keypad Connector X18 Signal Map ...............................78

phyCOREi.MX31
©PHYTEC Messtechnik GmbH 2007 L-700e_0
Table 31: Zigbee Connector...........................................................85
Table 29: Universal Display Pin Header.........................................90
Table 30: Display switch (Universal pin header)............................92
Table 34: Serial LCD pin header....................................................93
Table 35: PHYTEC Camera Connector X7....................................97
Table 36: Universal Camera pin header X8 ...................................98
Table 37: JTAG Connector...........................................................100

Contents
©PHYTEC Messtechnik GmbH 2007 L-700e_0

Preface
1Preface
This hardware manual describes the phyCORE-i.MX31 Single Board Computer’s design and function.
Precise specifications for the Freescale i.MX31 microcontrollers can be found in the enclosed
microcontroller Data Sheet/User's Manual.
In this hardware manual and in the attached schematics, active low signals are denoted by a "/" or “#”
preceding the signal name (e.g.: /RD or #RD). A "0" indicates a logic zero or low-level signal, while a
"1" represents a logic one or high-level signal.
Declaration of Electro Magnetic Conformity of the PHYTEC
©PHYTEC Messtechnik GmbH 2007 L-700e_0 1
phyCORE-I.MX31
PHYTEC Single Board Computers (henceforth products) are designed for installation
in electrical appliances or as dedicated Evaluation Boards (i.e.: for use as a test and prototype
platform for hardware/software development) in laboratory environments.
Caution:
PHYTEC products lacking protective enclosures are subject to damage by ESD and, hence, may only
be unpacked, handled or operated in environments in which sufficient precautionary measures have
been taken in respect to ESD-dangers. It is also necessary that only appropriately trained personnel
(such as electricians, technicians and engineers) handle and/or operate these products. Moreover,
PHYTEC products should not be operated without protection circuitry if connections to the product's
pin header rows are longer than 3 m.
PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic Conformity
only in accordance to the descriptions and rules of usage indicated in this hardware manual
(particularly in respect to the pin header row connectors, power connector and serial interface to a
host-PC).
Implementation of PHYTEC products into target devices, as well as user modifications and extensions
of PHYTEC products, is subject to renewed establishment of conformity to, and certification of,
Electro Magnetic Directives. Users should ensure conformance following any modifications to the
products as well as implementation of the products into target systems.
The phyCORE-i.MX31 is one of a series of PHYTEC Single Board Computers that can be populated
with different controllers and, hence, offers various functions and configurations. PHYTEC supports a
variety of 8-/16- and 32-bit controllers in two ways:
(1) as the basis for Rapid Development Kits which serve as a reference and evaluation platform
(2) as insert-ready, fully functional phyCORE OEM modules, which can be embedded directly
into the user’s peripheral hardware design.
PHYTEC's microcontroller modules allow engineers to shorten development horizons, reduce design
costs and speed project concepts from design to market. For more information go to:
http://www.phytec.com/services/phytec-advantage.html

phyCOREi.MX31
2 ©PHYTEC Messtechnik GmbH 2007 L-700e_0
1.1 Introduction
The phyCORE-i.MX31 belongs to PHYTEC’s phyCORE Single Board Computer module family. The
phyCORE SBCs represent the continuous development of PHYTEC Single Board Computer
technology. Like its mini-, micro- and nanoMODUL predecessors, the phyCORE boards integrate all
core elements of a microcontroller system on a subminiature board and are designed in a manner
that ensures their easy expansion and embedding in peripheral hardware developments.
As independent research indicates that approximately 70 % of all EMI (Electro Magnetic Interference)
problems stem from insufficient supply voltage grounding of electronic components in high frequency
environments the phyCORE board design features an increased pin package. The increased pin
package allows dedication of approximately 20 % of all pin header connectors on the phyCORE
boards to Ground. This improves EMI and EMC characteristics and makes it easier to design complex
applications meeting EMI and EMC guidelines using phyCORE boards even in high noise
environments.
phyCORE boards achieve their small size through modern SMD technology and multi-layer design. In
accordance with the complexity of the module, 0402-packaged SMD components and laser-drilled
microvias are used on the boards, providing phyCORE users with access to this cutting edge
miniaturization technology for integration into their own design.
The phyCORE-i.MX31 is a subminiature (84 x 58 mm) insert-ready Single Board Computer populated
with the Freescale i.MX31 microcontroller. Its universal design enables its insertion in a wide range of
embedded applications. All controller signals and ports extend from the controller to high-density pitch
(0.635 mm) connectors aligning two sides of the board, allowing it to be plugged like a "big chip" into
a target application.
Precise specifications for the controller populating the board can be found in the applicable controller
User’s Manual or datasheet. The descriptions in this manual are based on the Freescale i.MX31. No
description of compatible microcontroller derivative functions is included, as such functions are not
relevant for the basic functioning of the phyCORE-i.MX31.

Introduction
©PHYTEC Messtechnik GmbH 2007 L-700e_0 3
The phyCORE-I.MX31 offers the following features:
•Subminiature Single Board Computer (84 x 58 mm) achieved through modern SMD technology
•Populated with the Freescale i.MX31 microcontroller (BGA457 packaging)
•Improved interference safety achieved through multi-layer PCB technology and dedicated ground
pins
•Controller signals and ports extend to two 200-pin high-density (0.635 mm) Molex connectors
aligning two sides of the board, enabling it to be plugged like a "big chip" into target application
•Max. 400 MHz (532 MHz in overdrive Mode) core clock frequency
•Boot from NOR or NAND Flash
•32MByte (up to 64MByte) Intel Strata NOR Flash
•64 MByte (up to 1 GByte) on-board NAND Flash1
•128 MByte (up to 512 MByte) Mobile DDR SDRAM on-board
•RS-232 transceiver supporting one UART at data rates of up to 460kbps
•Two full featured UART Interfaces without transceiver
•32KB I2C EEPROM
•Separate I²C RTC with backup function
•512Kbyte (up to 2MByte SRAM) with backup function
•Battery buffered controller based RTC with automatic battery switchover
•High-Speed USB OTG transceiver
•Auto FDX/MDX 100MBit Ethernet Controller
•All controller required supplies generated on board by PMIC
•Synchronous 18Bit LCD-Interface
•PCMCIA/CF card Interface
•ATA-Interface DMA-Mode 3 (up to DMA-mode 5 without level-shifter) / CMOS Camera Interface
•Support of standard 20 pin debug interface through JTAG connector
•Keyboard support for up to 24 keys in a 4 * 6 matrix
•Two I2C interfaces
•SD/MMC card interface with DMA
•Special Power-Management IC which includes:
oStereo line-in
oStereo line-out / pre-amplified mono-out
oStereo mic-in
o4-Wire touch interface
oRTC
oLCD-Backlight control
oBattery charger
o6 AD-Inputs
1Please contact PHYTEC for more information about additional module configurations.

phyCOREi.MX31
1.2 Block Diagram
Figure 1: Block Diagram of the phyCORE-i.MX31
4 ©PHYTEC Messtechnik GmbH 2007 L-700e_0

Introduction
1.3 View of the phyCORE-i.MX31
C193
C189
C152
C190
C194
U19
RN26
X3
C2
C17
R42
RN37
C157
R92
C22
C117
D4
U3
R70
CB552
C131
RN19
R64
RN17
R71
J20
RN5
C166
R100
C175
CB503
C155
RN39
D5
RN18
R25
R28
R11
CB400
RN24
CB307
CB310
C24
C182
X2
R86R89
RN22
RN15
C181
C100
C133
D3
R87
RN23
R26
L2
C13
R94
RN12
RN27
U10
R91
C60
RN13
C146
RN4
C124
U12
C32
C23
R85
R22
RN30
C159
C135
C134
R2
R80
R32
C165
R93
C151
U11
C163
RN21
TP1
C153
R57
R79
C1
D2
J18
D7
C101
R38
RN6
CB301
C10
CB401
R56
XT1
R37
RN43
CB502
RN35
C3
R90
R88
R49
RN14
R74
CB501
R58
RN36
RN25
CB100
C156
R40
RN28
R81
C95
OZ1
RN40
CB500
R60
CB402
RN29
R41
C147
R14
R95
R69
R50
C7
C161
R72
C116
C174
J19
J16
L1
C98
C122
R39
R43
C158
C123
C177
RN3
U7
C25
U8
R33
L3
R84
CB312
C164
CB313
C20
U9
C5
U14
U6
C149
R59
RN38
RN7
C16
R68
RN16
C176
R5
C35
RN20
RN11
CB300
U5
R82
J17
U2
U1
U15
Figure 2: Top view of the phyCORE-i.MX31 (controller side)
©PHYTEC Messtechnik GmbH 2007 L-700e_0 5

phyCOREi.MX31
R75
R61
C36
R65
C103
C72
R97
R13
C47
TP3
C46
C85
R77
C65
CB450
C33
C80
C41
TP4
C37
C187
U23
CB550
U4
C34
C69
C132
RN41
R12
R98
C56
C109
C31
J2
CB350
CB309
R9
C38
C30
CB553
J3
CB308
C48
R1
C118
J8
C125
R44
C113
R48
C28
C29
R23
C73
CB306
R4
R67
C88
C112
C111
C39
U17
C119
U13
C94
R99
R24
C55
R10
C44
U18
XT3
C188
TP5
R83
Q3
CB351
TP2
C11
D1
C54
JN2
C102
C43
R21
R15
C53
CB304
R17
C21
R46
C185
L4
C108
C49
C180
C66
C136
R54
C18
C9
U20
C140
R76
RN42
C99
R96
J6
RN47
R55
CB250
JN1
R73
J4
C107
C51
R34
C4
C86
C114
RN1
R35
C50
C148
RN34
C150
C138
C45
C27
R36
J1
CB305
J21
Q4
C61
CB251
RN45
R51
R47
R19
Q1
C93
U16
RN46
C59
RN2
C52
C139
C14
RN31
C137
C87
C67
XT2
CB302
RN44
RN33
RN8
C6
R52
C70
R53
R6
C12
C64
C92
J5
C19
R29
C186
C110
C104
C40
C96 C90
C106
C42
U22
C141
C129
C62
R16
C97
TP6
CB150
C71
C15 R66
C26
RN32
R18
Q2
R20
C57
CB201
R63
C58
CB303
C91
C68
J13
J10J11
J14
J15
J12
J9
R45
R31
R8
C142
C143
R7
C8
R30
C145
C144
R27
CB200
C160
C191
R78
R3
C192 R62
X1
J22
D6
J7
Q5
U21
C115
C77
C79
C89
C63
C154
C162
C126
CB311
C170
C171
C173 C172
C168
C169
C184
C128
C178
C179
C183
C167
C130
C127
CB551
C78
Figure 3: Bottom view of the phyCORE-i.MX31 (connector side)
6 ©PHYTEC Messtechnik GmbH 2007 L-700e_0

System Memory
©PHYTEC Messtechnik GmbH 2007 L-700e_0 7
2Pin Description
Please note that all module connections are not to exceed their expressed maximum voltage or
current. Maximum signal input values are indicated in the corresponding controller manuals/data
sheets. As damage from improper connections varies according to use and application, it is the user's
responsibility to take appropriate safety measures to ensure that the module connections are
protected from overloading through connected peripherals.
As Figure 4 indicates, all controller signals extend to surface mount technology (SMT) connectors
(0.635 mm) lining two sides of the module (referred to as phyCORE-connector). This allows the
phyCORE-i.MX31 to be plugged into any target application like a "big chip".
A new numbering scheme for the pins on the phyCORE-connector has been introduced with the
phyCORE specifications. This enables quick and easy identification of desired pins and minimizes
errors when matching pins on the phyCORE-module with the phyCORE-connector on the appropriate
PHYTEC Development Board or in user target circuitry.
The numbering scheme for the phyCORE-connector is based on a two dimensional matrix in which
column positions are identified by a letter and row position by a number. Pin 1A, for example, is
always located in the upper left hand corner of the matrix. The pin numbering values increase moving
down on the board. Lettering of the pin connector rows progresses alphabetically from left to right
(refer to Figure 4).
The numbered matrix can be aligned with the phyCORE-i.MX31 (viewed from above;
phyCORE-connector pointing down) or with the socket of the corresponding phyCORE Development
Board/user target circuitry. The upper left-hand corner of the numbered matrix (pin 1A) is thus
covered with the corner of the phyCORE-i.MX31 marked with a triangle. The numbering scheme is
always in relation to the PCB as viewed from above, even if all connector contacts extend to the
bottom of the module.
The numbering scheme is thus consistent for both the module’s phyCORE-connector as well as
mating connectors on the phyCORE Development Board or target hardware, thereby considerably
reducing the risk of pin identification errors.
Since the pins are exactly defined according to the numbered matrix previously described, the
phyCORE-connector is usually assigned a single designator for its position (X1 for example). In this
manner the phyCORE-connector comprises a single, logical unit regardless of the fact that it could
consist of more than one physical socketed connector. The location of row 1 on the board is marked
by a triangle on the PCB to allow easy identification.
The following figure (Figure 4) illustrates the numbered matrix system. It shows a phyCORE-i.MX31
with SMT phyCORE-connectors on its underside (defined as dotted lines) mounted on a Development
Board. In order to facilitate understanding of the pin assignment scheme, the diagram presents a
cross-view of the phyCORE-module showing these phyCORE-connectors mounted on the underside
of the module’s PCB.

phyCOREi.MX31
Figure 4: Pin-out of the phyCORE-Connector (top view, with cross section
insert)
Table 1 provides an overview of the pin-out of the phyCORE-connector, as well as descriptions of
possible alternative functions. Table 1 also provides the appropriate signal level interface voltages
listed in the SL (Signal Level) column. The Freescale i.MX31 is a multi-voltage operated
microcontroller and as such special attention should be paid to the interface voltage levels to avoid
unintentional damage to the microcontroller and other on-board components. Please refer to the
Freescale i.MX31 User’s Manual/Data Sheet for details on the functions and features of controller
signals and port pins.
8 ©PHYTEC Messtechnik GmbH 2007 L-700e_0

System Memory
©PHYTEC Messtechnik GmbH 2007 L-700e_0 9
Note: SL is short for Signal Level (V) and is the applicable logic level to interface a given
pin. Those pins marked as “N/A” have a range of applicable values that constitute proper
operation.
Table 1: Pin-out of the phyCORE-Connector X1
PIN ROW X1A
PIN # SIGNAL I/O SL DESCRIPTION
1A NVCC_7 O NVCC_7 LCD reference voltage (1,5V-3,0V )
2A GND - 0 Ground 0V
3A x_LC_SD_D_CLK O NVCC_7 LCD serial interface clock
4A x_LC_PAR_RS O NVCC_7 Data/command select for parallel LCD interface
5A x_LC_VSYNC0 I/O NVCC_7 Display 0 vertical synchronization pulse
6A x_LC_READ O NVCC_7 System-80: READ
System 68K: ENABLE
In byte enable mode
System-80: READ_L
System-68K: ENABLE_L
7A GND - 0 Ground 0V
8A x_LC_D3_REV O NVCC_7 REV signal for Sharp display 3
9A x_LC_ D3_SPL O NVCC_7 SPL signal for Sharp display 3
10A x_LC_ DRDY0 O NVCC_7 Keyboard row 4 scan output pin of the µC
11A x_LC_FPLINE O NVCC_7 Display 3 horizontal synchronization pulse
(FPLINE/HSYNC/LP)
12A GND - 0 Ground 0V
13A x_LC_D0 I/O NVCC_7 Input/Output data to display.
14A x_LC_D2 I/O NVCC_7 Input/Output data to display.
15A x_LC_D3 I/O NVCC_7 Input/Output data to display.
16A x_LC_D5 I/O NVCC_7 Input/Output data to display.
17A GND - 0 Ground 0V
18A x_LC_D8 I/O NVCC_7 Input/Output data to display.
19A x_LC_D10 I/O NVCC_7 Input/Output data to display.
20A x_LC_D11 I/O NVCC_7 Input/Output data to display.
21A x_LC_D13 I/O NVCC_7 Input/Output data to display.
22A GND - 0 Ground 0V
23A x_LC_D17 O NVCC_7 Output data to display.
In byte enable mode, READ_H (for sys80) or
ENABLE_H (for sys68k)
24A x_/CS0 O 3.3V /CS0 output (per default used by NOR-Flash)
25A x_/CS1 O 3.3V /CS1 output (per default used by Ethernet)
26A x_/CS4 O 3.3V /CS4 output (per default used by SRAM)
27A GND - 0 Ground 0V

phyCOREi.MX31
10 ©PHYTEC Messtechnik GmbH 2007 L-700e_0
28A x_/EB1 O 3.3V X_/EB1 corresponds to DATA_OUT[15:8] and
M_DATA_OUT[15:8].
29A x_/OE O 3.3V Output Enable.
30A x_/LBA O 3.3V Load Burst Address
31A x_/CLK O 3.3V Burst Clock
32A GND - 0 Ground 0V
33A x_A2 O 3.3V Address-Line A2
34A x_A4 O 3.3V Address-Line A4
35A x_A5 O 3.3V Address-Line A5
36A x_A7 O 3.3V Address-Line A7
37A GND - 0 Ground 0V
38A x_A10 O 3.3V Address-Line A10
39A x_A12 O 3.3V Address-Line A12
40A x_A13 O 3.3V Address-Line A13
41A x_A15 O 3.3V Address-Line A15
42A GND - 0 Ground 0V
43A x_A18 O 3.3V Address-Line A18
44A x_A20 O 3.3V Address-Line A20
45A x_A21 O 3.3V Address-Line A21
46A x_A23 O 3.3V Address-Line A23
47A GND - 0 Ground 0V
48A x_D0 I/O 3.3V Data-Bus D0
49A x_D2 I/O 3.3V Data-Bus D2
50A x_D3 I/O 3.3V Data-Bus D3
51A x_D5 I/O 3.3V Data-Bus D4
52A GND - 0 Ground 0V
53A x_D8 I/O 3.3V Data-Bus D8
54A x_D10 I/O 3.3V Data-Bus D10
55A x_D11 I/O 3.3V Data-Bus D11
56A x_D13 I/O 3.3V Data-Bus D13
57A GND - 0 Ground 0V
58A x_PC_BVD1 I 3.3V PCMCIA Battery Voltage Detect Input 1
59A x_PC_BVD2 I 3.3V PCMCIA Battery Voltage Detect Input 2
60A x_/PC_CD1 I 3.3V PCMCIA Card Detect Input 1
61A x_PC_PWRON I 3.3V PCMCIA Power is On Signal
62A GND - 0 Ground 0V
63A x_PCnRW O 3.3V PCMCIA External Transceiver Direction Signal
64A x_PC_VS1 I NVCC_3_4_6 PCMCIA Voltage sense Input 1
65A x_PC_VS2 I NVCC_3_4_6 PCMCIA Voltage sense Input 2
66A x_/CE1 O NVCC_3_4_6 PCMCIA Card Enable 1 Signal
67A GND - 0 Ground 0V