ST L6917BD User manual

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L6917B
September 2002
■2 PHASE OPERATION WITH
SYNCRHONOUS RECTIFIER CONTROL
■ULTRA FAST LOAD TRANSIENT RESPONSE
■INTEGRATED HIGH CURRENT GATE
DRIVERS: UP TO 2A GATE CURRENT
■TTL-COMPATIBLE 5 BIT PROGRAMMABLE
OUTPUT COMPLIANT WITH VRM 9.0
■0.8% INTERNAL REFERENCE ACCURACY
■10% ACTIVE CURRENT SHARING
ACCURACY
■DIGITAL 2048 STEP SOFT-START
■OVERVOLTAGE PROTECTION
■OVERCURRENT PROTECTION REALIZED
USING THE LOWER MOSFET'S RdsON OR A
SENSE RESISTOR
■300 kHz INTERNAL OSCILLATOR
■OSCILLATOR EXTERNALLY ADJUSTABLE
UP TO 600kHz
■POWER GOOD OUTPUT AND INHIBIT
FUNCTION
■REMOTE SENSE BUFFER
■PACKAGE: SO-28
APPLICATIONS
■POWER SUPPLY FOR SERVERS AND
WORKSTATIONS
■POWER SUPPLY FOR HIGH CURRENT
MICROPROCESSORS
■DISTRIBUTED DC-DC CONVERTERS
DESCRIPTION
The device is a power supply controller specifically
designed to provide a high performance DC/DC con-
version for high current microprocessors.
The device implements a dual-phase step-down con-
troller with a 180° phase-shift between each phase.
A precise 5-bit digital to analog converter (DAC) al-
lows adjusting the output voltage from 1.100V to
1.850V with 25mV binary steps.
The high precision internal reference assures the se-
lected output voltage to be within ±0.8%. The high
peak current gate drive affords to have fast switching
to the external power mos providing low switching
losses.
The device assures a fast protection against load
over current and load over/under voltage. An internal
crowbar is provided turning on the low side mosfet if
an over-voltage is detected. In case of over-current,
the system works in Constant Current mode.
SO-28
ORDERING NUMBERS:L6917BD
L6917BDTR (Tape & Reel)
5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER
BLOCK DIAGRAM
CURRENT
READING
CURRENT
READING
IFB
TOTAL
CURRENT
AVG
CURRENT
CH 1OVER
CURRENT
CH 2OVER
CURRENT
DAC
DIGITAL
SOFT START
LOGIC PWM
ADAPTIVE ANTI
CROSS-CONDUCTION
LOGIC PWM
ADAPTIVE ANTI
CROSS-CONDUCTION
CH1OVER
CURRENT
CH2OVER
CURRENT
LOGIC
AND
PROTECTIONS
2PHASE
OSCILLATOR PWM1
CURRENT
CORRECTION
PWM2
CURRENT
CORRECTION
ERROR
AMPLIFIER
REMOTE
BUFFER
10k
10k
10k
LS
LS
HS
Vcc
HS
BOOT1
UGATE1
PHASE1
LGATE1
ISEN1
PGNDS1
PGND
PGNDS2
ISEN2
LGATE2
PHASE2
UGATE2
BOOT2
VccCOMP
FB
VSEN
FBG
FBR
VID0
VID1
VID2
VID3
VID4
PGOOD
ROSC / INH SGND VCCDR
10k
< >
+
-
+
+
-
VCCDR
VCC
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ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
PIN CONNECTION
Symbol Parameter Value Unit
Vcc, VCCDR to PGND 15 V
VBOOT-VPHASE Boot Voltage 15 V
VUGATE1-VPHASE1
VUGATE2-VPHASE2 15 V
LGATE1, PHASE1, LGATE2, PHASE2 to PGND -0.3 to Vcc+0.3 V
All other pins to PGND -0.3 to 7 V
Vphase Sustainable Peak Voltage t < 20ns @ 600kHz 26 V
Symbol Parameter Value Unit
Rth j-amb Thermal Resistance Junction to Ambient 60 °C/W
Tmax Maximum junction temperature 150 °C
Tstorage Storage temperature range -40 to 150 °C
TjJunction Temperature Range -25 to 125 °C
PMAX Max power dissipation at Tamb = 25°C 2 W
LGATE1
VCCDR
PHASE1
VID3
VID2
VID1
FB
BOOT1
UGATE1
VID4
BOOT2
PGOOD
UGATE2
PHASE2
LGATE2
PGND1
3
2
4
5
6
7
8
9
18
17
16
15
19
20
10VSEN
VCC
GND
COMP
SO28
11
12
13
14
24
23
22
21
25
26
27
28
FBG
ISEN1
PGNDS1
FBR
OSC / INH / FAUL
T
ISEN2
PGNDS2
VID0
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ELECTRICAL CHARACTERISTICS
VCC = 12V
± 10%, TJ= 0 to 70°C unless otherwise specified
Symbol Parameter Test Condition Min Typ Max Unit
Vcc SUPPLY CURRENT
ICC Vcc supply current HGATEx and LGATEx open
VCCDR=VBOOT=12V 7.5 10 12.5 mA
ICCDR VCCDR supply current LGATEx open; VCCDR=12V 2 3 4 mA
IBOOTx Boot supply current HGATEx open; PHASEx to PGND
VCC=VBOOT=12V 0.5 1 1.5 mA
POWER-ON
Turn-On VCC threshold VCC Rising; VCCDR=5V 7.8 9 10.2 V
Turn-Off VCC threshold VCC Falling; VCCDR=5V 6.5 7.5 8.5 V
Turn-On VCCDR
Threshold VCCDR Rising VCC=12V 4.2 4.4 4.6 V
Turn-Off VCCDR
Threshold VCCDR Falling VCC=12V 4.0 4.2 4.4 V
OSCILLATOR/INHIBIT/FAULT
fOSC Initial Accuracy OSC = OPEN
OSC = OPEN; Tj=0°C to 125°C278 270 300 322 330 kHz kHz
f
OSC,Rosc
Total Accuracy RTto GND=74kΩ450 500 550 kHz
INH Inhibit threshold ISINK=5mA 0.8 0.85 0.9 V
dMAX Maximum duty cycle OSC = OPEN 70 75 %
∆Vosc Ramp Amplitude 1.8 2 2.2 V
FAULT Voltage at pin OSC OVP or UVP Active 4.75 5.0 5.25 V
REFERENCE AND DAC
Output Voltage
Accuracy VID0, VID1, VID2, VID3, VID4 see Table1;
FBR = VOUT; FBG = GND
-0.8 - 0.8 %
IDAC VID pull-up Current VIDx = GND 4 5 6 µA
VID pull-up Voltage VIDx = OPEN 3.1 - 3.4 V
ERROR AMPLIFIER
DC Gain 80 dB
SR Slew-Rate COMP=10pF 15 V/µs
DIFFERENTIAL AMPLIFIER (REMOTE BUFFER)
DC Gain 1 V/V
CMRR Common Mode Rejection Ratio 40 dB
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Input Offset FBR=1.100V to1.850V;
FBG=GND -12 12 mV
SR Slew Rate VSEN=10pF 15 V/µs
DIFFERENTIAL CURRENT SENSING
IISEN1,
IISEN2 Bias Current Iload=0 45 50 55 µA
IPGNDSx Bias Current 45 50 55 µA
IISEN1,
IISEN2 Bias Current at
Over Current Threshold 80 85 90 µA
IFB Active Droop Current Iload<0%
Iload=100% 47.5 0 50 1 52.5 µA
µA
GATE DRIVERS
tRISE
HGATE High Side
Rise Time VBOOTx-VPHASEx=10V;
CHGATEx to PHASEx=3.3nF 15 30 ns
IHGATEx High Side
Source Current VBOOTx-VPHASEx=10V 2 A
RHGATEx High Side
Sink Resistance VBOOTx-VPHASEx=12V; 1.5 2 2.5 Ω
tRISE
LGATE Low Side
Rise Time VCCDR=10V;
CLGATEx to PGNDx=5.6nF 30 55 ns
ILGATEx Low Side
Source Current VCCDR=10V 1.8 A
RLGATEx Low Side
Sink Resistance VCCDR=12V 0.7 1.1 1.5 Ω
P GOOD and OVP/UVP PROTECTIONS
PGOOD Upper Threshold
(VSEN/DACOUT) VSEN Rising 108 112 116 %
PGOOD Lower Threshold
(VSEN/DACOUT) VSEN Falling 84 88 92 %
OVP Over Voltage Threshold
(VSEN)VSEN Rising 2.0 2.25 V
UVP Under Voltage Trip
(VSEN/DACOUT) VSEN Falling 56 60 64 %
VPGOOD PGOOD Voltage Low IPGOOD = -4mA 0.3 0.4 0.5 V
ELECTRICAL CHARACTERISTICS (continued)
VCC = 12V
± 10%, TJ= 0 to 70°C unless otherwise specified
Symbol Parameter Test Condition Min Typ Max Unit
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Table 1. VID Settings
VID4 VID3 VID2 VID1 VID0 Output Voltage (V)
1 1 1 1 1 OUTPUT OFF
11110 1.100
11101 1.125
11100 1.150
11011 1.175
11010 1.200
11001 1.225
11000 1.250
10111 1.275
10110 1.300
10101 1.325
10100 1.350
10011 1.375
10010 1.400
10001 1.425
10000 1.450
01111 1.475
01110 1.500
01101 1.525
01100 1.550
01011 1.575
01010 1.600
01001 1.625
01000 1.650
00111 1.675
00110 1.700
00101 1.725
00100 1.750
00011 1.775
00010 1.800
00001 1.825
00000 1.850
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PIN FUNCTION
N Name Description
1 LGATE1 Channel 1 low side gate driver output.
2 VCCDR Mosfet driver supply. It can be varied from 5V to 12V.
3 PHASE1 This pin is connected to the source of the upper mosfet and provides the return path for the high
side driver of channel 1.
4 UGATE1 Channel 1 high side gate driver output.
5 BOOT1 Channel 1 bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper
mosfet. Connect through a capacitor to the PHASE1 pin and through a diode to Vcc (cathode vs.
boot).
6 VCC Device supply voltage. The operative supply voltage is 12V.
7 GND All the internal references are referred to this pin. Connect it to the PCB signal ground.
8 COMP This pin is connected to the error amplifier output and is used to compensate the control
feedback loop.
9 FB This pin is connected to the error amplifier inverting input and is used to compensate the voltage
control feedback loop.
A current proportional to the sum of the current sensed in both channel is sourced from this pin
(50µA at full load, 70µA at the Over Current threshold). Connecting a resistor between this pin
and VSEN pin allows programming the droop effect.
10 VSEN Connected to the output voltage it is able to manage Over & Under-voltage conditions and the
PGOOD signal. It is internally connected with the output of the Remote Sense Buffer for Remote
Sense of the regulated voltage.
If no Remote Sense is implemented, connect it directly to the regulated voltage in order to
manage OVP, UVP and PGOOD.
11 FBR Remote sense buffer non-inverting input. It has to be connected to the positive side of the load to
perform a remote sense.
If no remote sense is implemented, connect directly to the output voltage (in this case connect
also the VSEN pin directly to the output regulated voltage).
12 FBG Remote sense buffer inverting input. It has to be connected to the negative side of the load to
perform a remote sense.
Pull-down to ground if no remote sense is implemented.
13 ISEN1 Channel 1 current sense pin. The output current may be sensed across a sense resistor or
across the low-side mosfet RdsON. This pin has to be connected to the low-side mosfet drain or
to the sense resistor through a resistor Rg in order to program the positive current limit at 140%
as follow:
Where 35µA is the current offset information relative to the Over Current condition (offset at OC
threshold minus offset at zero load).
The net connecting the pin to the sense point must be routed as close as possible to the
PGNDS1 net in order to couple in common mode any picked-up noise.
14
PGNDS1 Channel 1 Power Ground sense pin. The net connecting the pin to the sense point (*) must be
routed as close as possible to the ISEN1 net in order to couple in common mode any picked-up
noise.
15
PGNDS2 Channel 2 Power Ground sense pin. The net connecting the pin to the sense point (*) must be
routed as close as possible to the ISEN2 net in order to couple in common mode any picked-up
noise.
IMAX 35µAR
g
⋅
R
sense
--------------------------=
(*) Through a resistor Rg.
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16 ISEN2 Channel 2 current sense pin. The output current may be sensed across a sense resistor or
across the low-side mosfet RdsON. This pin has to be connected to the low-side mosfet drain or
to the sense resistor through a resistor Rg in order to program the positive current limit at 140%
as follow:
Where 35µA is the current offset information relative to the Over Current condition (offset at OC
threshold minus offset at zero load).
The net connecting the pin to the sense point must be routed as close as possible to the
PGNDS2 net in order to couple in common mode any picked-up noise.
17
OSC/
INH/
FAULT
Oscillator switching frequency pin. Connecting an external resistor from this pin to GND, the
external frequency is increased according to the equation:
Connecting a resistor from this pin to Vcc (12V), the switching frequency is reduced according to
the equation:
If the pin is not connected, the switching frequency is 300KHz.
Forcing the pin to a voltage lower than 0.8V, the device stop operation and enter the inhibit state.
The pin is forced high when an over or under voltage is detected. This condition is latched; to
recover it is necessary turn off and on VCC.
18-22 VID4-0 Voltage IDentification pins. These input are internally pulled-up and TTL compatible. They are
used to program the output voltage as specified in Table 1 and to set the power good thresholds.
Connect to GND to program a ‘0’ while leave floating to program a ‘1’.
23 PGOOD This pin is an open collector output and is pulled low if the output voltage is not within the above
specified thresholds.
If not used may be left floating.
24 BOOT2 Channel 2 bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper
mosfet. Connect through a capacitor to the PHASE2 pin and through a diode to Vcc (cathode vs.
boot).
25 UGATE2 Channel 2 high side gate driver output.
26 PHASE2 This pin is connected to the source of the upper mosfet and provides the return path for the high
side driver of channel 2.
27 LGATE2 Channel 2 low side gate driver output.
28 PGND Power ground pin. This pin is common to both sections and it must be connected through the
closest path to the low side mosfets source pins in order to reduce the noise injection into the
device.
PIN FUNCTION
(continued)
N Name Description
IMAX 35µAR
g
⋅
R
sense
--------------------------=
fS300KHz 14.82 106
⋅
ROSC KΩ()
-----------------------------+=
fS300KHz 12.91 107
⋅
ROSC KΩ()
-----------------------------–=
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Device Description
The device is an integrated circuit realized in BCD technology. It provides complete control logicand protections
for a high performance dual-phase step-down DC-DC converter optimized for microprocessor power supply. It
is designed to drive N Channel MOSFETs in a dual-phase synchronous-rectified buck topology. A 180 deg
phase shift is provided between the two phases allowing reduction in the input capacitor current ripple, reducing
also the size and the losses. The output voltage of the converter can be precisely regulated, programming the
VID pins, from 1.100V to 1.850V with 25mV binary steps, with a maximum tolerance of ±0.8% over temperature
and line voltage variations. The device provides an average current-mode control with fast transient response.
It includesa 300kHz free-running oscillator adjustable up to 600kHz. The error amplifier features a 15V/
µ
s slew
rate that permits high converter bandwidth for fast transient performances. Current information is read across
the lower mosfets r
DSON
or across a sense resistor in fully differential mode. The current information corrects
the PWM output in order to equalize the average current carried by each phase. Current sharing between the
two phases is then limited at ±10% over static and dynamic conditions. The device protects against over-cur-
rent, with an OC threshold for each phase, entering in constant current mode. Since the current is read across
the low side mosfets, the constant current keeps constant the bottom of the inductors current triangular wave-
form. When an under voltage is detected the device latches and the FAULT pin is driven high. The device per-
forms also over voltage protection that disable immediately the device turning ON the lower driver and driving
high the FAULT pin.
Oscillator
Thedevice hasbeen designedinorder tooperate aneach phaseat thesame switching frequencyofthe internal
oscillator. So, input and output resulting frequency is doubled.
The switching frequency is internally fixed to 300kHz. The internal oscillator generates the triangular waveform
for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the
oscillator is typically 25
µ
A and may be varied using an external resistor (R
OSC
) connected between OSC pin
and GND or Vcc. Since the OSC pin is maintained at fixed voltage (typ). 1.235V, the frequency is varied pro-
portionally to the current sunk (forced) from (into) the pin considering the internal gain of 12KHz/
µ
A.
In particular connecting it to GND the frequency is increased (current is sunk from the pin), while connecting ROSC
to Vcc=12V the frequency is reduced (current is forced into the pin), according to the following relationships:
Note that forcing a 25
µ
A current into this pin, the device stops switching because no current is delivered to the
oscillator.
Figure 1. ROSC vs. Switching Frequency
ROSCvs.GND: fS300kHz 1.237
ROSC KΩ()
------------------------------ 12kHz
µA
-----------⋅+300kHz 14.82 106
⋅
ROSC KΩ()
------------------------------+==
R
OSCvs.12V: fS300kHz 12 1.237
–
ROSC KΩ()
------------------------------ 12kHz
µA
-----------
⋅–300kHz 12.918 107
⋅
ROSC KΩ()
--------------------------------–==
0
1000
2000
3000
4000
5000
6000
7000
0 100 200 300
Frequency (KHz)
Rosc(KΩ) vs. 12V
0
100
200
300
400
500
600
700
800
900
1000
300 400 500 600 700 800 900 1000
Frequency (KHz)
Rosc(KΩ) vs. GND
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Digital to Analog Converter
The built-in digital to analog converter allows the adjustment of the output voltage from 1.100V to 1.850V with
25mV as shown in the previous table 1. The internal reference is trimmed to ensure the precision of 0.8% and
a zero temperature coefficient around 70°C. The internal reference voltage for the regulationis programmed by
the voltage identification (VID) pins. These are TTL compatible inputs of an internal DAC that is realized by
means of a series of resistors providing a partition of the internal voltage reference. The VID code drives a mul-
tiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an amplifier ob-
taining the VPROG voltage reference (i.e. the set-point of the error amplifier). Internal pull-ups are provided
(realized with a 5
µ
A current generator up to 3.3V max); in this way, to program a logic "1" it is enough to leave
the pin floating, while to program a logic "0" it is enough to short the pin to GND. VID code “11111” programs
the NOCPU state: all mosfets are turned OFF and the condition is latched.
The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the over-
voltage protection (OVP) thresholds.
Soft Start and INHIBIT
At start-up a ramp is generated increasing the loop reference from 0V to the final value programmed by VID in
2048 clock periods as shown in figure 2.
Beforesoft start, thelower power MOS are turned ON after that V
CCDR
reaches 2V (independently byVccvalue)
to discharge the output capacitor and to protect the load from high side mosfet failures. Once soft start begins,
the reference is increased; when it reaches the bottom of the oscillator triangular waveform (1V typ) also the
upper MOS begins to switch and the output voltage starts to increase with closed loop regulation.. At the end of
the digital soft start, the Power Good comparator is enabled and the PGOOD signal is then driven high (See fig.
2). The Under Voltage comparator enabled when the reference voltage reaches 0.8V.
The Soft-Start will not take place, if both V
CC
and VCCDR pins are not above their own turn-on thresholds. Dur-
ing normal operation, if any under-voltage is detected on one of the two supplies the device shuts down.
Forcing the OSC/INH/FAULT pin to a voltage lower than 0.8V the device enter in INHIBIT mode: all the power
mosfets are turned off until this condition is removed. When this pin is freed, the OSC/INH/FAULT pin reaches
the band-gap voltage and the soft start begins.
Figure 2. Soft Start
VIN=VCCDR
VLGATEx
PGOOD
VOUT
t
t
t
t
2V Turn ON threshold
2048 Clock Cycles
Timing Diagram Acquisition:
CH1 = PGOOD; CH2 = VOUT; CH4 = LGATEx
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Driver Section
The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce the
RDSON), maintaining fast switching transition.
The drivers for the high-side mosfets use BOOTx pins for supply and PHASEx pins for return. The drivers for
the low-side mosfets use VCCDRV pin for supply and PGND pin for return. A minimum voltage of 4.6V at VC-
CDRV pin is required to start operations of the device.
The controllerembodies a sophisticated anti-shoot-through system to minimize low side body diode conduction
time maintaining good efficiency saving the use of Schottky diodes. The dead time is reduced to few nanosec-
onds assuring that high-side and low-side mosfets are never switched on simultaneously: when the high-side
mosfet turns off, the voltage on its source begins to fall; when the voltage reaches 2V, the low-side mosfet gate
drive is appliedwith 30ns delay. Whenthe low-side mosfet turns off, the voltage at LGATEx pin is sensed. When
it drops below 1V, the high-side mosfet gate drive is applied with a delay of 30ns. If the current flowing in the
inductor is negative, the source of high-side mosfet will never drop. To allow the turning on of the low-side mos-
fet even in this case, a watchdog controller is enabled: if the source of the high-side mosfet don't drop for more
than 240ns, the low side mosfet is switched on so allowing the negative current of the inductor to recirculate.
This mechanism allows the system to regulate even if the current is negative.
The BOOTx and VCCDR pins are separated from IC's power supply (VCC pin) as well as signal ground (SGND
pin) and power ground (PGND pin) in order to maximize the switching noise immunity. The separated supply
forthe different driversgives high flexibility inmosfet choice,allowingthe useof logic-level mosfet. Severalcom-
bination of supply can be chosen to optimize performance and efficiency of the application. Power conversion
is also flexible, 5V or 12V bus can be chosen freely.
The peak current is shown for both the upper and the lower driver of the two phases in figure 3. A 10nF capac-
itive load has been used. For the upper drivers, the source current is 1.9A while the sink current is 1.5A with
V
BOOT
-V
PHASE
= 12V; similarly, forthe lower drivers, the source current is 2.4A while thesink current is2A with
VCCDR = 12V.
Figure 3. Drivers peak current: High Side (left) and Low Side (right)
Current Reading and Over Current
The current flowing trough each phase is read using the voltage drop across the low side mosfets r
DSON
or
across a sense resistor (R
SENSE
) and internally converted into a current. The transconductance ratio is issued
by the external resistorRg placed outside the chip between ISENx and PGNDSx pins toward the reading points.
The full differential current reading rejects noise and allows to place sensing element in different locations with-
out affecting the measurement's accuracy. The current reading circuitry reads the current during the time in
CH3 = HGATE1; CH4 = HGATE2 CH3 = LGATE1; CH4 = LGATE2
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which the low-side mosfet is on (OFF Time). During this time, the reaction keeps the pin ISENx and PGNDSx
at the same voltage while during the time in which the reading circuitry is off, an internal clamp keeps these two
pins at the same voltage sinking from the ISENx pin the necessary current.
The proprietary current reading circuit allows a very precise and high bandwidth reading for both positive and
negative current. This circuit reproduces the current flowing through the sensing element using a high speed
Track & Hold transconductance amplifier. In particular, it reads the current during the second half of the OFF
time reducing noise injection into the device due to the mosfet turn-on (See fig. 4). Track time must be at least
200ns to make proper reading of the delivered current.
Figure 4. Current Reading Timing (Left) and Circuit (Right)
This circuit sources a constant 50
µ
A current from the PGNDSx pin and keeps the pins ISENx and PGNDSx at
the same voltage. Referring to figure 4, the current that flows in the ISENx pin is then given by the following
equation:
Where R
SENSE
is an external sense resistor or the rds,on of the low side mosfet and Rg is the transconductance
resistor usedbetween ISENxand PGNDSx pinstoward the reading points; I
PHASE
is the current carried by each
phase and, in particular, the current measured in the middle of the oscillator period
The current information reproduced internally is represented by the second term of the previous equation as
follow:
Since the current is read in differential mode, also negative current information is kept; this allow the device to
check for dangerous returning current between the two phases assuring the complete equalization between the
phase's currents.
From the current information of each phase, information about the total current delivered (I
FB
= I
INFO1
+ I
INFO2
)
and the average current for each phase (I
AVG
= (I
INFO1
+ I
INFO2
)/2 ) is taken. I
INFOX
is then compared to I
AVG
to give the correction to the PWM output in order to equalize the current carried by the two phases.
The transconductance resistor Rg has to be designed in order to have current information of 25
µ
A per phase
at full nominal load; the over current intervention threshold is set at 140% of the nominal (IINFOx = 35
µ
A).
According to the above relationship, the limiting current (I
LIM
) for each phase, which has to be placed at one half
of the total delivered maximum current, results:
An over current is detected when the current flowing into the sense element is greater than 140% of the nominal
RSENSE
Rg
50
µµ
A
IISENx
IPHASE
Rg
LGATEX
ISENX
PGNDSX
ILS1
ILS2
Track &Hold
Total current
information
IISENx 50µARSENSE IPHASE
⋅
Rg
----------------------------------------------+ 50µAI
INFOx
+==
I
INFOx RSENSE IPHASE
⋅
Rg
----------------------------------------------=
ILIM 35µARg
⋅
R
SENSE
---------------------------= Rg ILIM RSENSE
⋅
35µA
-------------------------------------=
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current (I
INFOx
>35
µ
A): the device enters in Quasi-Constant-Current operation. The low-side mosfets stays ON
until I
INFO
becomes lower than 35
µ
A skipping clockcycles. Thehigh side mosfets can be turned ON with a T
ON
imposed by the control loop at the next available clock cycle and the device works in the usual way until another
OCP event is detected.
The device limits the bottom of the inductor current triangular waveform. So the average current delivered can
slightly increase also in Over Current condition since the current ripple increases. In fact, the ON time increases
due to the OFF time rise because of the current has to reach the 140% bottom. The worst-case condition is
when the duty cycle reaches its maximum value (d=75% internally limited). When this happens, the device
works in Constant Current and the output voltage decrease as the load increase. Crossing the UVP threshold
causes the device to latch (FAULT pin is driven high).
Figure 5 shows this working condition
Figure 5. Constant Current operation
It can be observed that the peak current (Ipeak) is greater than the 140% but it can be determined as follow:
Where I
NOM
is the nominal current and Vout
MIN
is the minimum output voltage (VID-40% as explained below).
The device works in Constant-Current, and the output voltage decreases as the load increase, until the output
voltage reaches the under-voltage threshold (Vout
MIN
). When this threshold is crossed, all mosfets are turned
off, the FAULT pin is driven high and the device stops working. Cycle the power supply to restart operation.
The maximum average current during the Constant-Current behavior results:
In this particular situation, the switching frequency results reduced. The ON time is the maximum allowed (Ton-
MAX) while the OFF time depends on the application:
Over current is set anyway when I
INFOx
reaches 35
µ
A. The full load value is only a convention to work with con-
venient values for I
FB
. Since the OCP intervention threshold is fixed, to modify the percentage with respect to
the load value, it can be simply considered that, for example, to have on OCP threshold of 170%, this will cor-
respond to I
INFOx
=35
µ
A (I
FB
= 70
µ
A). The full load current will then correspond toI
INFOx
= 20.5
µ
A (I
FB
= 41
µ
A).
TonMAX TonMAX
140%
I
p
eak
IMAX
Vout
Iout
Inom IOCP IMAX
UVP
Droop
effect
Ipeak 1.4 INOM VIN VoutMIN
–L
--------------------------------------- TonMAX
⋅+⋅=
IMAX 1.4 INOM 2Ipeak 1.4 INOM
⋅–2
-------------------------------------------------
⋅+⋅=
TOFF LIpeak 1.4 INOM
⋅–
Vout
-------------------------------------------------
⋅=
f1
TonMAX TOFF
+
-------------------------------------------=
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L6917B
Integrated Droop Function
The device uses a droop function to satisfy the requirements of high performance microprocessors, reducing
the size and the cost of the output capacitor.
This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a de-
pendence of the output voltage on the load current
As shown in figure 6, the ESR drop is present in any case, but using the droop function the total deviation of the
output voltage is minimized. In practice the droop function introduces a static error (Vdroop in figure 6) propor-
tional tothe output current. Since the device has an average current mode regulation, the information about the
total current delivered is used to implement the Droop Function. This current (equal to the sum of both I
INFOx
)
is sourced from the FB pin. Connecting a resistor between this pin and Vout, the total current information flows
only in this resistor because the compensation network between FB and COMP has always a capacitor in series
(See fig. 7). The voltage regulated is then equal to:
V
OUT
= V
ID
- R
FB
· I
FB
Since I
FB
depends on the current information about the two phases, the output characteristic vs. load current is
given by:
Figure 6. Output transient response without (a) and with (b) the droop function
Figure 7. Active Droop Function Circuit
The feedback current is equalto 50
µ
A at nominal full load (I
FB
= I
INFO1
+ I
INFO2
) and 70
µ
A at the OC threshold,
so the maximum output voltage deviation is equal to:
∆
V
FULL_POSITIVE_LOAD
= +R
FB
· 50
µ
A
∆
V
POSITIVE_OC_THRESHOLD
= +R
FB
· 70
µ
A
Droop function is provided only for positive load; if negative load is applied, and then I
INFOx
< 0, no current is
sunk from the FB pin. The device regulates at the voltage programmed by the VID.
VOUT VID RFB RSENSE
Rg
---------------------- IOUT
⋅⋅–=
V
MAX
VMIN
VNOM
(
a
) (
b
)
ESR DROP ESR DROP
VDROOP
VPROG
COMP FB
To VOUT
IFB
RFB
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Output Voltage Protection and Power Good
The output voltage is monitored by pin VSEN. If it is not within +12/-10% (typ.) of the programmed value, the
powergood output is forced low. Power good is an open drain output and it is enabled only after the soft start is
finished (2048 clock cycles after start-up).
The device provides over voltage protection; when the voltage sensed by the V
SEN
pin reaches 2.1V (typ.), the
controller permanently switches on both the low-side mosfets and switchesoff both the high-side mosfets in or-
der to protect the CPU. The OSC/INH/FAULT pin is driven high (5V) and power supply (Vcc) turn off and on is
required to restart operations. The over Voltage percentage is set by the ratio between the OVP threshold (set
at 2.1V) and the reference programmed by VID.
Under voltage protection is also provided. If the output voltage drops below the 60% of the reference voltage for
more than one clock period the device turns off and the FAULT pin is driven high.
Both Over Voltage and Under Voltage are active also during soft start (Under Voltage after than Vout reaches
0.8V). During soft-start the referencevoltage used todetermine the OV andUV thresholds isthe increasing volt-
age driven by the 2048 soft start digital counter.
Remote Voltage Sense
A remote sense buffer is integrated into the device to allow output voltage remote sense implementation without
any additional external components. In this way, the output voltage programmed is regulated between the re-
mote buffer inputs compensating motherboard trace losses or connector losses if the device is used for a VRM
module. The very low offset amplifier senses the output voltage remotely through the pins FBR and FBG (FBR
is for the regulated voltage sense while FBG is for the ground sense)and reports this voltage internally at VSEN
pin with unity gain eliminating the errors.
If remote sense is not required, the output voltage is sensed by the VSEN pin connecting it directly to the output
voltage. In this case the FBG and FBR pins must be connected anyway to the regulated voltage.
Input Capacitor
The input capacitor is designed considering mainly the input rms current that depends on the duty cycle as re-
ported in figure 8. Considering the dual-phase topology, the input rms current is highly reduced comparing with
a single phase operation.
Figure 8. Input rms Current vs. Duty Cycle (D) and Driving Relationships
It can be observed that the input rms value is one half of the single-phase equivalent input current in the worst
case condition that happens for D = 0.25 and D = 0.75.
OVP[%] 2.1V
Reference Voltage VID
()
----------------------------------------------------------------------------- 100
⋅=
0.50 0.750.25
0.50
0.25
Single Phase
Dual Phase
Duty Cycle (VOUT/VIN)
Rms Current Normalized (IRMS/IOUT)





>−⋅⋅
<−⋅⋅
=
0.5DifD)2(21)-(2D
2
OUT
I
5.0DifD)2(12D
2
OUT
I
rms
I
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L6917B
The power dissipated by the input capacitance is then equal to:
Input capacitor is designed in order to sustain the ripple relative to the maximum load duty cycle. To reach the
high rms value needed by the CPU power supply application and also to minimize components cost, the input
capacitance is realized by more than one physical capacitor. The equivalent rms current is simply the sum of
the single capacitor's rms current.
Input bulk capacitor must be equally divided between high-side drain mosfets and placed as close as possible
to reduce switching noise above all during load transient. Ceramic capacitor can also introduce benefits in high
frequency noise decoupling, noise generated by parasitic components along power path.
Output Capacitor
Since the microprocessors require a current variation beyond 50A doing load transients, with a slope in the
range of tenth A/
µ
s, the output capacitor is a basic component for the fast response of the power supply.
Dual phase topology reduces the amount of output capacitance needed because of faster load transient re-
sponse (switching frequency is doubled at the load connections). Current ripple cancellation due to the 180°
phase shiftbetween the twophases also reduces requirements on the output ESR to sustain a specified voltage
ripple.
When a load transient is applied to the converter's output, for first few microseconds the current to the load is
supplied by the output capacitors. The controller recognizes immediately the load transient and increases the
duty cycle, but the current slope is limited by the inductor value.
The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the
ESL):
∆
V
OUT
=
∆
I
OUT
· ESR
A minimum capacitor value is required to sustain the current during the load transient without discharge it. The
voltage drop due to the output capacitor discharge is given by the following equation:
Where D
MAX
is the maximum duty cycle value. The lower is the ESR, the lower is the output drop during load
transient and the lower is the output voltage static ripple.
Inductor design
The inductance value is defined by a compromise between the transient response time, the efficiency, the cost
and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain
the ripple current
∆
IL between 20% and 30% of the maximum output current. The inductance value can be cal-
culated with this relationship:
Where f
SW
is the switching frequency, V
IN
is the input voltage and V
OUT
is the output voltage.
Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter
response time to a load transient. The response time is the time required by the inductor to change its current
from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by
the output capacitors. Minimizing the response time can minimize the output capacitance required.
The response time to a load transient is different for the application or the removal of the load: if during the ap-
plicationof the load the inductoris charged by avoltageequal to the difference between the input and the output
PRMS ESR IRMS
()
2
⋅=
V
OUT
∆IOUT
2
∆L ⋅
2C
OUT VINMIN DMAX VOUT
–⋅()⋅⋅
---------------------------------------------------------------------------------------------=
LVIN VOUT
–
fs IL
∆⋅
------------------------------ VOUT
VIN
---------------⋅=
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16/33
voltage, during the removal it is discharged only by the output voltage. The following expressions give approx-
imate response time for
∆
I load transient in case of enough fast compensation network response:
The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst
case is the response time after removal of the load with the minimum output voltage programmed and the max-
imum input voltage available.
Figure 9. Inductor ripple current vs Vout
MAIN CONTROL LOOP
The L6917B control loop is composed by the Current Sharing control loop and the Average Current Mode con-
trol loop. Each loop gives, with a proper gain, the correction to the PWM in order to minimize the error in its
regulation: the Current Sharing control loop equalize the currents in the inductors while the Average Current
Mode control loop fixes the output voltage equal to the reference programmed by VID. Figure 10 reports the
block diagram of the main control loop.
Figure 10. Main Control Loop Diagram
tapplication LI
∆⋅
V
IN VOUT
–
------------------------------= tremoval LI
∆⋅
V
OUT
---------------=
0
1
2
3
4
5
6
7
8
9
0.5 1.5 2.5 3.5
Output Volta
g
e [V]
Inductor Ripple [A]
L=3µH,
Vin=12V
L=2µH,
Vin=12V
L=1.5µH, Vin=12V
L=2µH,
Vin=5V
L=1.5µH,
Vin=5V
L=3µH, Vin=5V
L1
L2
+
+
PWM1
1/5
+
-
1/5
IINFO2
IINFO1
4/5
ZF(S)
PWM2
CO
FBCOMP
RO ERROR
AMPLIFIER REFERENCE
PROGRAMMED
BY VID
CURRENT
SHARING
DUTY CYCLE
CORRECTION
ZFB
D02IN1392
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L6917B
■Current Sharing (CS) Control Loop
Active current sharing is implemented using the information from Tran conductance differential amplifier in an
average current mode control scheme. A current reference equal to the average of the read current (I
AVG
) is
internally built; the error between the read current and this reference is converted to a voltage with a proper gain
and it is used to adjust the duty cycle whose dominant value is set by the error amplifier at COMP pin (See fig.
11).
Thecurrentsharing control isa high bandwidthcontrol loopallowingcurrent sharing even during load transients.
The current sharing error is affected by the choice of external components; choose precise Rg resistor (±1% is
necessary) to sense the current. The current sharing error is internally dominated by the voltage offset of Tran
conductance differential amplifier; considering a voltage offset equal to 2mV across the sense resistor, the cur-
rent reading error is given by the following equation:
Where
∆
I
READ
is the difference between one phase current and the ideal current (I
MAX
/2).
For Rsense = 4m
Ω
and Imax = 40A the current sharing error is equal to 2.5%, neglecting errors due to Rg and
Rsense mismatches.
Figure 11. Current Sharing Control Loop
■Average Current Mode (ACM) Control Loop
The average current mode control loop is reported in figure 12. The current information IFB sourced by the FB
pin flows into RFB implementing the dependence of the output voltage from the read current.
The ACM control loop gain results (obtained opening the loop after the COMP pin):
Where:
– is the equivalent output resistance determined by the droop function;
–Z
P
(s) is the impedance resulting by the parallel of the output capacitor (and its ESR) and the applied
load Ro;
IREAD
∆IMAX
-------------------- 2mV
RSENSE IMAX
⋅
----------------------------------------=
L1
L2
+
+
PWM1
1/5
1/5
IINFO2
IINFO1
PWM2
COMP VOUT
CURRENT
SHARING
DUTY CYCLE
CORRECTION
D02IN1393
GLOOP s
() PWM ZFs
() R
DROOP ZPs
()+()⋅⋅
Z
P
s
() Z
Ls
()+()
Z
F
s
()
As
()
--------------- 11
As
()
------------+


R
FB
⋅+⋅
--------------------------------------------------------------------------------------------------------------------=
RDROOP Rsense
Rg
------------------- RFB
⋅=
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–Z
F
(s) is the compensation network impedance;
–Z
L
(s) is the parallel of the two inductor impedance;
– A(s) is the error amplifier gain;
– · is the ACM PWM transfer function where DVosc is the oscillator ramp amplitude
and has a typical value of 2V
Removing the dependence from the Error Amplifier gain, so assuming this gain high enough, the control loop
gain results:
With further simplifications, it results:
Considering now that in the application of interest it can be assumed that Ro>>R
L
; ESR<<Ro and
R
DROOP
<<Ro, it results:
The ACM control loop gain is designedto obtain a high DC gain to minimize static error and cross the 0dB axes
with a constant -20dB/dec slope with the desired crossover frequency
ω
T
. Neglecting the effect of Z
F
(s), the
transfer function has one zero and two poles. Both the poles are fixed once the output filter is designed and the
zero is fixed by ESR and the Droop resistance. To obtain the desired shape an R
F
-C
F
series network is consid-
ered for the Z
F
(s) implementation. A zero at
ω
F
=1/R
F
C
F
is then introduced together with an integrator. This in-
tegrator minimizes the static error while placing the zero in correspondence with the L-C resonance a simple -
20dB/dec shape of the gain is assured (See Figure 12). In fact, considering the usual value for the output filter,
the LC resonance results to be at frequency lower than the above reported zero.
Figure 12. ACM Control Loop Gain Block Diagram (left) and Bode Diagram (right)
Compensation network can be simply designedplacing
ω
Z
=
ω
LC
and imposing the cross-over frequency
ω
T
as
desired obtaining:
PWM 4
5
--- VIN
∆
VOSC
∆
-------------------
⋅=
GLOOP s
() 4
5
--- VIN
VOSC
∆
------------------- ZFs
()
Z
Ps
() Z
Ls
()+
------------------------------------ Rs
Rg
-------- ZPs
()
R
FB
---------------+



⋅⋅ ⋅–=
G
LOOP s
() 4
5
--- VIN
VOSC
∆
------------------- ZFs
()
R
FB
--------------- Ro RDROOP
+
Ro RL
2
-------+
-------------------------------------- 1sCoR
DROOP//Ro ESR
+()⋅⋅+
s
2
Co L
2
--- sL
2Ro
⋅
--------------- Co ESR Co RL
2
-------
⋅+⋅+1 +⋅+⋅⋅
----------------------------------------------------------------------------------------------------------------------------------
⋅⋅⋅ ⋅–=
G
LOOP s
() 4
5
--- VIN
VOSC
∆
------------------- ZFs
()
R
FB
--------------- 1sCoR
DROOP ESR
+()⋅⋅+
s
2
Co L
2
--- sL
2Ro
⋅
--------------- Co ESR Co RL
2
-------⋅+⋅+1 +⋅+⋅⋅
----------------------------------------------------------------------------------------------------------------------------------
⋅⋅⋅–=
Rout
Cout
ESR
L/2
RFB
RF CF
REF
PWM
IFB
VCOMP
VOUT
d•VIN
ZFdB
ω
ωT
ωZ ωLC
GLOOP
ZF(s)
K
K4
5
--- VIN
Vosc
∆
--------------- 1
RFB
----------
⋅⋅
dB
=
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L6917B
LAYOUT GUIDELINES
Since the device manages control functions and high-current drivers, layout is one of the most important things
to consider when designing such high current applications.
A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing radi-
ation and a proper connection between signal and power ground can optimise the performance of the control
loops.
Integrated power drivers reduce components count and interconnections between control functions and drivers,
reducing the board space.
Here below are listed the main points to focus on when starting a new layout and rules are suggested for a cor-
rect implementation.
■Power Connections.
These are the connections where switching and continuous current flows fromthe input supplytowardsthe load.
The first priority when placing components has to be reserved to this power section, minimizing the length of
each connection as much as possible.
To minimize noise and voltage spikes (EMI and losses) these interconnections must be a part of a power plane
and anyway realized by wide and thick copper traces. The critical components, i.e. the power transistors, must
be located as close as possible, together and to the controller. Considering that the "electrical" components re-
ported in fig. 13 are composed by more than one "physical" component, a ground plane or "star" grounding con-
nection is suggested to minimize effects due to multiple connections.
Figure 13. Power connections and related connections layout guidelines (same for both phases)
Fig. 13a shows the details of the power connections involved and the current loops. The input capacitance
(CIN), or at least a portion of the total capacitance needed, has to be placed close to the power section in order
to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors (electrolytic or
Ceramic or both) are required.
■Power Connections Related.
Fig.13b shows some small signal components placement, and how and where to mix signal and power ground
planes.
The distance from drivers and mosfet gates should be reduced as much as possible. Propagation delay times
RFRFB VOSC
∆⋅
VIN
---------------------------------- ωTL
2R
DROOP ESR
+()⋅
-------------------------------------------------------- 5
4
---
⋅⋅ ⋅=
C
F
Co L
2
---
⋅
R
F
--------------------=
V
IN
LOAD
HS
Rgat e
LS
Rgate
HGATEx
PHASEx
LGATEx
PGNDx
CIN
COUT
L
D
CBOOTx VIN
LOAD
HS
LS
BOOTx
PHASEx
VCC
SGND
CIN
COUT
L
D
+VCC
CVCC
a. PCB power and ground planes areas b. PCB small signal components placement
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as well as for the voltage spikes generated by the distributed inductance along the copper traces are so mini-
mized.
In fact, the further the mosfet is from the device, the longer is the interconnecting gate trace and as a conse-
quence, the higher are the voltage spikes corresponding to the gatepwm rising and falling signals. Even if these
spikes are clamped by inherent internal diodes, propagation delays, noise and potential causes of instabilities
are introduced jeopardizing good system behavior. One important consequence is that the switching losses for
the high side mosfet are significantly increased.
For this reason, it is suggested to have the device oriented with the driver side towards the mosfets and the
GATEx and PHASEx traces walking together toward the high side mosfet in order to minimize distance (see fig
14). In addition, since the PHASEx pin is the return path for the high side driver, this pin must be connected
directly to the High Side mosfet Source pin to have a proper driving for this mosfet. For the LS mosfets, the re-
turn path is the PGND pin: it can be connected directly to the power ground plane (if implemented) or in the
same way to the LS mosfets Source pin. GATEx and PHASEx connections (and also PGND when no power
ground plane is implemented) must also be designed to handle current peaks in excess of 2A (30 mils wide is
suggested).
Gate resistors of few ohms help in reducing the power dissipated by the IC without compromising the system
efficiency.
Figure 14. Device orientation (left) and sense nets routing (right)
The placement of other components is also important:
– The bootstrap capacitor must be placed as close as possible to the BOOTx and PHASEx pins to mini-
mize the loop that is created.
– Decoupling capacitor from Vcc and SGND placed as close as possible to the involved pins.
– Decoupling capacitor from VCCDR and PGND placed as close aspossible to those pins. This capacitor
sustains the peak currents requested by the low-side mosfet drivers.
– Refer to SGND all the sensible components such as frequency set-up resistor (when present) and also
the optional resistor from FB to GND used to give the positive droop effect.
– Connect SGND to PGND on the load side (output capacitor) to avoid undesirable load regulation effect
and to ensure the right precision to the regulation when the remote sense buffer is not used.
– An additional 100nF ceramic capacitor is suggested to place near HS mosfet drain. This helps in reduc-
ing noise.
– PHASE pin spikes. Since the HS mosfet switches in hard mode, heavy voltage spikes can be observed
on the PHASE pins. If these voltage spikes overcome the max breakdown voltage of the pin, the device
can absorb energy and it can cause damages. The voltage spikes must be limited by proper layout, the
use of gate resistors, Schottky diodes in parallel to the low side mosfets and/or snubber network on the
low side mosfets, to a value lower than 26V, for 20nSec, at Fosc of 600kHz max.
■Current Sense Connections.
Remote Buffer:
The input connections for this component must be routed as parallel nets from the FBG/FBR
Towards HS mosfet
(30 mils wide)
Towards LS mosfet
(30 mils wide)
Towards HS mosfet
(30 mils wide)
To LS mosfet
(or sense resistor)
To regulated output
To LS mosfet
(or sense resistor)
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